2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
38 #include "opt_comconsole.h"
39 #include "opt_compat.h"
45 * Serial driver, based on 386BSD-0.1 com driver.
46 * Mostly rewritten to use pseudo-DMA.
47 * Works for National Semiconductor NS8250-NS16550AF UARTs.
48 * COM driver, based on HP dca driver.
50 * Changes for PC-Card integration:
51 * - Added PC-Card driver table and handlers
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/reboot.h>
56 #include <sys/malloc.h>
59 #include <sys/module.h>
61 #include <sys/dkstat.h>
62 #include <sys/fcntl.h>
63 #include <sys/interrupt.h>
64 #include <sys/kernel.h>
65 #include <sys/syslog.h>
66 #include <sys/sysctl.h>
68 #include <machine/bus.h>
70 #include <sys/timepps.h>
72 #include <isa/isareg.h>
73 #include <isa/isavar.h>
74 #include <machine/lock.h>
76 #include <machine/clock.h>
77 #include <machine/ipl.h>
79 #include <machine/lock.h>
81 #include <machine/resource.h>
83 #include <isa/sioreg.h>
86 #include <isa/ic/esp.h>
88 #include <isa/ic/ns16550.h>
94 #include <sys/module.h>
95 #include <pccard/cardinfo.h>
96 #include <pccard/slot.h>
102 #define disable_intr()
103 #define enable_intr()
107 #define disable_intr() COM_DISABLE_INTR()
108 #define enable_intr() COM_ENABLE_INTR()
112 #define EXTRA_SIO 4 /* XXX shouldn't need NSIO */
115 #define NSIOTOT (NSIO + EXTRA_SIO)
117 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
119 #define CALLOUT_MASK 0x80
120 #define CONTROL_MASK 0x60
121 #define CONTROL_INIT_STATE 0x20
122 #define CONTROL_LOCK_STATE 0x40
123 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
124 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
125 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
128 /* checks in flags for multiport and which is multiport "master chip"
131 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
132 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
133 #define COM_NOTAST4(flags) ((flags) & 0x04)
134 #endif /* COM_MULTIPORT */
136 #define COM_CONSOLE(flags) ((flags) & 0x10)
137 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
138 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
139 #define COM_DEBUGGER(flags) ((flags) & 0x80)
140 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
141 #define COM_NOFIFO(flags) ((flags) & 0x02)
142 #define COM_ST16650A(flags) ((flags) & 0x20000)
143 #define COM_C_NOPROBE (0x40000)
144 #define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
145 #define COM_C_IIR_TXRDYBUG (0x80000)
146 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
147 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
149 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
153 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
154 * than the other bits so that they can be tested as a group without masking
157 * The following com and tty flags correspond closely:
158 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
160 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
161 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
162 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
163 * TS_FLUSH is not used.
164 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
165 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
167 #define CS_BUSY 0x80 /* output in progress */
168 #define CS_TTGO 0x40 /* output not stopped by XOFF */
169 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
170 #define CS_CHECKMSR 1 /* check of MSR scheduled */
171 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
172 #define CS_DTR_OFF 0x10 /* DTR held off */
173 #define CS_ODONE 4 /* output completed */
174 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
175 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
177 static char const * const error_desc[] = {
180 #define CE_INTERRUPT_BUF_OVERFLOW 1
181 "interrupt-level buffer overflow",
182 #define CE_TTY_BUF_OVERFLOW 2
183 "tty-level buffer overflow",
187 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
189 /* types. XXX - should be elsewhere */
190 typedef u_int Port_t; /* hardware port */
191 typedef u_char bool_t; /* boolean */
193 /* queue of linear buffers */
195 u_char *l_head; /* next char to process */
196 u_char *l_tail; /* one past the last char to process */
197 struct lbq *l_next; /* next in queue */
198 bool_t l_queued; /* nonzero if queued */
201 /* com device structure */
203 u_int flags; /* Copy isa device flags */
204 u_char state; /* miscellaneous flag bits */
205 bool_t active_out; /* nonzero if the callout device is open */
206 u_char cfcr_image; /* copy of value written to CFCR */
208 bool_t esp; /* is this unit a hayes esp board? */
210 u_char extra_state; /* more flag bits, separate for order trick */
211 u_char fifo_image; /* copy of value written to FIFO */
212 bool_t hasfifo; /* nonzero for 16550 UARTs */
213 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
214 bool_t loses_outints; /* nonzero if device loses output interrupts */
215 u_char mcr_image; /* copy of value written to MCR */
217 bool_t multiport; /* is this unit part of a multiport device? */
218 #endif /* COM_MULTIPORT */
219 bool_t no_irq; /* nonzero if irq is not attached */
220 bool_t gone; /* hardware disappeared */
221 bool_t poll; /* nonzero if polling is required */
222 bool_t poll_output; /* nonzero if polling for output is required */
223 int unit; /* unit number */
224 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
226 u_int wopeners; /* # processes waiting for DCD in open() */
229 * The high level of the driver never reads status registers directly
230 * because there would be too many side effects to handle conveniently.
231 * Instead, it reads copies of the registers stored here by the
234 u_char last_modem_status; /* last MSR read by intr handler */
235 u_char prev_modem_status; /* last MSR handled by high level */
237 u_char hotchar; /* ldisc-specific char to be handled ASAP */
238 u_char *ibuf; /* start of input buffer */
239 u_char *ibufend; /* end of input buffer */
240 u_char *ibufold; /* old input buffer, to be freed */
241 u_char *ihighwater; /* threshold in input buffer */
242 u_char *iptr; /* next free spot in input buffer */
243 int ibufsize; /* size of ibuf (not include error bytes) */
244 int ierroff; /* offset of error bytes in ibuf */
246 struct lbq obufq; /* head of queue of output buffers */
247 struct lbq obufs[2]; /* output buffers */
249 Port_t data_port; /* i/o ports */
255 Port_t modem_ctl_port;
256 Port_t line_status_port;
257 Port_t modem_status_port;
258 Port_t intr_ctl_port; /* Ports of IIR register */
260 struct tty *tp; /* cross reference */
263 struct termios it_in; /* should be in struct tty */
264 struct termios it_out;
267 struct termios lt_in; /* should be in struct tty */
268 struct termios lt_out;
271 bool_t do_dcd_timestamp;
272 struct timeval timestamp;
273 struct timeval dcd_timestamp;
274 struct pps_state pps;
276 u_long bytes_in; /* statistics */
278 u_int delta_error_counts[CE_NTYPES];
279 u_long error_counts[CE_NTYPES];
282 * Data area for output buffers. Someday we should build the output
283 * buffer queue without copying data.
290 static int espattach __P((struct com_s *com, Port_t esp_port));
292 static int sioattach __P((device_t dev));
294 static timeout_t siobusycheck;
295 static timeout_t siodtrwakeup;
296 static void comhardclose __P((struct com_s *com));
297 static void sioinput __P((struct com_s *com));
298 static void siointr1 __P((struct com_s *com));
299 static void siointr __P((void *arg));
300 static int commctl __P((struct com_s *com, int bits, int how));
301 static int comparam __P((struct tty *tp, struct termios *t));
302 static swihand_t siopoll;
303 static int sioprobe __P((device_t dev));
304 static void siosettimeout __P((void));
305 static int siosetwater __P((struct com_s *com, speed_t speed));
306 static void comstart __P((struct tty *tp));
307 static timeout_t comwakeup;
308 static void disc_optim __P((struct tty *tp, struct termios *t,
312 static char driver_name[] = "sio";
314 /* table and macro for fast conversion from a unit number to its com struct */
315 static devclass_t sio_devclass;
316 #define com_addr(unit) ((struct com_s *) \
317 devclass_get_softc(sio_devclass, unit))
319 static device_method_t sio_methods[] = {
320 /* Device interface */
321 DEVMETHOD(device_probe, sioprobe),
322 DEVMETHOD(device_attach, sioattach),
327 static driver_t sio_driver = {
330 sizeof(struct com_s),
333 static d_open_t sioopen;
334 static d_close_t sioclose;
335 static d_read_t sioread;
336 static d_write_t siowrite;
337 static d_ioctl_t sioioctl;
338 static d_stop_t siostop;
339 static d_devtotty_t siodevtotty;
341 #define CDEV_MAJOR 28
342 static struct cdevsw sio_cdevsw = {
344 /* close */ sioclose,
346 /* write */ siowrite,
347 /* ioctl */ sioioctl,
350 /* devtotty */ siodevtotty,
353 /* strategy */ nostrategy,
354 /* name */ driver_name,
356 /* maj */ CDEV_MAJOR,
365 static volatile speed_t comdefaultrate = CONSPEED;
367 static volatile speed_t gdbdefaultrate = CONSPEED;
369 static u_int com_events; /* input chars + weighted output completions */
370 static Port_t siocniobase;
371 static int siocnunit;
372 static Port_t siogdbiobase;
373 static int siogdbunit = -1;
374 static bool_t sio_registered;
375 static int sio_timeout;
376 static int sio_timeouts_until_log;
377 static struct callout_handle sio_timeout_handle
378 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
380 static struct speedtab comspeedtab[] = {
384 { 110, COMBRD(110) },
385 { 134, COMBRD(134) },
386 { 150, COMBRD(150) },
387 { 200, COMBRD(200) },
388 { 300, COMBRD(300) },
389 { 600, COMBRD(600) },
390 { 1200, COMBRD(1200) },
391 { 1800, COMBRD(1800) },
392 { 2400, COMBRD(2400) },
393 { 4800, COMBRD(4800) },
394 { 9600, COMBRD(9600) },
395 { 19200, COMBRD(19200) },
396 { 38400, COMBRD(38400) },
397 { 57600, COMBRD(57600) },
398 { 115200, COMBRD(115200) },
403 /* XXX configure this properly. */
404 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
405 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
409 * handle sysctl read/write requests for console speed
411 * In addition to setting comdefaultrate for I/O through /dev/console,
412 * also set the initial and lock values for the /dev/ttyXX device
413 * if there is one associated with the console. Finally, if the /dev/tty
414 * device has already been open, change the speed on the open running port
419 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
426 newspeed = comdefaultrate;
428 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
429 if (error || !req->newptr)
432 comdefaultrate = newspeed;
434 if (comconsole < 0) /* serial console not selected? */
437 com = com_addr(comconsole);
442 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
443 * (note, the lock rates really are boolean -- if non-zero, disallow
446 com->it_in.c_ispeed = com->it_in.c_ospeed =
447 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
448 com->it_out.c_ispeed = com->it_out.c_ospeed =
449 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
452 * if we're open, change the running rate too
455 if (tp && (tp->t_state & TS_ISOPEN)) {
456 tp->t_termios.c_ispeed =
457 tp->t_termios.c_ospeed = comdefaultrate;
459 error = comparam(tp, &tp->t_termios);
465 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
466 0, 0, sysctl_machdep_comdefaultrate, "I", "");
470 * PC-Card (PCMCIA) specific code.
472 static int sioinit __P((struct pccard_devinfo *));
473 static void siounload __P((struct pccard_devinfo *));
474 static int card_intr __P((struct pccard_devinfo *));
476 PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
479 * Initialize the device - called from Slot manager.
482 sioinit(struct pccard_devinfo *devi)
485 /* validate unit number. */
486 if (devi->isahd.id_unit >= (NSIOTOT))
488 /* Make sure it isn't already probed. */
489 if (com_addr(devi->isahd.id_unit))
492 /* It's already probed as serial by Upper */
493 devi->isahd.id_flags |= COM_C_NOPROBE;
496 * Probe the device. If a value is returned, the
497 * device was found at the location.
499 if (sioprobe(&devi->isahd) == 0)
501 if (sioattach(&devi->isahd) == 0)
508 * siounload - unload the driver and clear the table.
510 * This is usually called when the card is ejected, but
511 * can be caused by a modunload of a controller driver.
512 * The idea is to reset the driver's view of the device
513 * and ensure that any driver entry points such as
514 * read and write do not hang.
517 siounload(struct pccard_devinfo *devi)
522 printf("NULL devi in siounload\n");
525 com = com_addr(devi->isahd.id_unit);
527 printf("NULL com in siounload\n");
531 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
534 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
536 printf("sio%d: unload\n", devi->isahd.id_unit);
542 if (com->ibuf != NULL)
543 free(com->ibuf, M_DEVBUF);
545 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
550 * card_intr - Shared interrupt called from
551 * front end of PC-Card handler.
554 card_intr(struct pccard_devinfo *devi)
559 com = com_addr(devi->isahd.id_unit);
560 if (com && !com->gone)
561 siointr1(com_addr(devi->isahd.id_unit));
565 #endif /* NCARD > 0 */
567 #define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit))
568 #define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit))
570 static struct isa_pnp_id sio_ids[] = {
571 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
572 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
573 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
574 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
575 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
583 static bool_t already_init;
588 intrmask_t irqmap[4];
593 u_int flags = isa_get_flags(dev);
595 struct resource *port;
597 /* Check isapnp ids */
598 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
602 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
603 0, ~0, IO_COMSIZE, RF_ACTIVE);
609 * Turn off MCR_IENABLE for all likely serial ports. An unused
610 * port with its MCR_IENABLE gate open will inhibit interrupts
611 * from any used port that shares the interrupt vector.
612 * XXX the gate enable is elsewhere for some multiports.
617 devclass_get_devices(sio_devclass, &devs, &count);
618 for (i = 0; i < count; i++) {
620 if (device_is_enabled(xdev))
621 outb(isa_get_port(xdev) + com_mcr, 0);
627 if (COM_LLCONSOLE(flags)) {
628 printf("sio%d: reserved for low-level i/o\n",
629 device_get_unit(dev));
634 * If the device is on a multiport card and has an AST/4
635 * compatible interrupt control register, initialize this
636 * register and prepare to leave MCR_IENABLE clear in the mcr.
637 * Otherwise, prepare to set MCR_IENABLE in the mcr.
638 * Point idev to the device struct giving the correct id_irq.
639 * This is the struct for the master device if there is one.
642 mcr_image = MCR_IENABLE;
644 if (COM_ISMULTIPORT(flags)) {
645 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
647 printf("sio%d: master device %d not configured\n",
648 device_get_unit(dev), COM_MPMASTER(flags));
651 if (!COM_NOTAST4(flags)) {
652 outb(isa_get_port(idev) + com_scr,
653 isa_get_irq(idev) >= 0 ? 0x80 : 0);
657 #endif /* COM_MULTIPORT */
658 if (isa_get_irq(idev) < 0)
661 bzero(failures, sizeof failures);
662 iobase = rman_get_start(port);
665 * We don't want to get actual interrupts, just masked ones.
666 * Interrupts from this line should already be masked in the ICU,
667 * but mask them in the processor as well in case there are some
668 * (misconfigured) shared interrupts.
674 * Initialize the speed and the word size and wait long enough to
675 * drain the maximum of 16 bytes of junk in device output queues.
676 * The speed is undefined after a master reset and must be set
677 * before relying on anything related to output. There may be
678 * junk after a (very fast) soft reboot and (apparently) after
680 * XXX what about the UART bug avoided by waiting in comparam()?
681 * We don't want to to wait long enough to drain at 2 bps.
683 if (iobase == siocniobase)
684 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
686 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
687 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
688 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
689 outb(iobase + com_cfcr, CFCR_8BITS);
690 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
694 * Enable the interrupt gate and disable device interupts. This
695 * should leave the device driving the interrupt line low and
696 * guarantee an edge trigger if an interrupt can be generated.
699 outb(iobase + com_mcr, mcr_image);
700 outb(iobase + com_ier, 0);
701 DELAY(1000); /* XXX */
702 irqmap[0] = isa_irq_pending();
705 * Attempt to set loopback mode so that we can send a null byte
706 * without annoying any external device.
709 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
712 * Attempt to generate an output interrupt. On 8250's, setting
713 * IER_ETXRDY generates an interrupt independent of the current
714 * setting and independent of whether the THR is empty. On 16450's,
715 * setting IER_ETXRDY generates an interrupt independent of the
716 * current setting. On 16550A's, setting IER_ETXRDY only
717 * generates an interrupt when IER_ETXRDY is not already set.
719 outb(iobase + com_ier, IER_ETXRDY);
722 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
723 * an interrupt. They'd better generate one for actually doing
724 * output. Loopback may be broken on the same incompatibles but
725 * it's unlikely to do more than allow the null byte out.
727 outb(iobase + com_data, 0);
728 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
731 * Turn off loopback mode so that the interrupt gate works again
732 * (MCR_IENABLE was hidden). This should leave the device driving
733 * an interrupt line high. It doesn't matter if the interrupt
734 * line oscillates while we are not looking at it, since interrupts
738 outb(iobase + com_mcr, mcr_image);
741 * It's a definitly Serial PCMCIA(16550A), but still be required
742 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
744 if ( COM_NOPROBE(flags) ) {
745 /* Reading IIR register twice */
746 for ( fn = 0; fn < 2; fn ++ ) {
748 failures[6] = inb(iobase + com_iir);
750 /* Check IIR_TXRDY clear ? */
752 if ( failures[6] & IIR_TXRDY ) {
753 /* Nop, Double check with clearing IER */
754 outb(iobase + com_ier, 0);
755 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
756 /* Ok. we're familia this gang */
757 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
759 /* Unknow, Just omit this chip.. XXX*/
763 /* OK. this is well-known guys */
764 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
766 outb(iobase + com_cfcr, CFCR_8BITS);
768 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
769 return (iobase == siocniobase ? 0 : result);
774 * o the CFCR, IER and MCR in UART hold the values written to them
775 * (the values happen to be all distinct - this is good for
776 * avoiding false positive tests from bus echoes).
777 * o an output interrupt is generated and its vector is correct.
778 * o the interrupt goes away when the IIR in the UART is read.
781 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
782 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
783 failures[2] = inb(iobase + com_mcr) - mcr_image;
784 DELAY(10000); /* Some internal modems need this time */
785 irqmap[1] = isa_irq_pending();
786 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
787 DELAY(1000); /* XXX */
788 irqmap[2] = isa_irq_pending();
789 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
792 * Turn off all device interrupts and check that they go off properly.
793 * Leave MCR_IENABLE alone. For ports without a master port, it gates
794 * the OUT2 output of the UART to
795 * the ICU input. Closing the gate would give a floating ICU input
796 * (unless there is another device driving it) and spurious interrupts.
797 * (On the system that this was first tested on, the input floats high
798 * and gives a (masked) interrupt as soon as the gate is closed.)
800 outb(iobase + com_ier, 0);
801 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
802 failures[7] = inb(iobase + com_ier);
803 DELAY(1000); /* XXX */
804 irqmap[3] = isa_irq_pending();
805 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
809 irqs = irqmap[1] & ~irqmap[0];
810 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
812 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
813 device_get_unit(dev), isa_get_irq(idev), irqs);
815 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
816 device_get_unit(dev),
817 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
820 for (fn = 0; fn < sizeof failures; ++fn)
822 outb(iobase + com_mcr, 0);
825 printf("sio%d: probe failed test(s):",
826 device_get_unit(dev));
827 for (fn = 0; fn < sizeof failures; ++fn)
834 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
835 return (iobase == siocniobase ? 0 : result);
840 espattach(com, esp_port)
848 * Check the ESP-specific I/O port to see if we're an ESP
849 * card. If not, return failure immediately.
851 if ((inb(esp_port) & 0xf3) == 0) {
852 printf(" port 0x%x is not an ESP board?\n", esp_port);
857 * We've got something that claims to be a Hayes ESP card.
861 /* Get the dip-switch configuration */
862 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
863 dips = inb(esp_port + ESP_STATUS1);
866 * Bits 0,1 of dips say which COM port we are.
868 if (com->iobase == likely_com_ports[dips & 0x03])
871 printf(" esp_port has com %d\n", dips & 0x03);
876 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
878 outb(esp_port + ESP_CMD1, ESP_GETTEST);
879 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
880 val = inb(esp_port + ESP_STATUS2);
881 if ((val & 0x70) < 0x20) {
882 printf("-old (%o)", val & 0x70);
887 * Check for ability to emulate 16550: bit 7 == 1
889 if ((dips & 0x80) == 0) {
895 * Okay, we seem to be a Hayes ESP card. Whee.
898 com->esp_port = esp_port;
914 struct resource *res;
916 u_int flags = isa_get_flags(dev);
918 struct resource *port;
921 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
922 0, ~0, IO_COMSIZE, RF_ACTIVE);
926 iobase = rman_get_start(port);
927 unit = device_get_unit(dev);
928 com = device_get_softc(dev);
931 * sioprobe() has initialized the device registers as follows:
932 * o cfcr = CFCR_8BITS.
933 * It is most important that CFCR_DLAB is off, so that the
934 * data port is not hidden when we enable interrupts.
936 * Interrupts are only enabled when the line is open.
937 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
938 * interrupt control register or the config specifies no irq.
939 * Keeping MCR_DTR and MCR_RTS off might stop the external
940 * device from sending before we are ready.
942 bzero(com, sizeof *com);
944 com->cfcr_image = CFCR_8BITS;
945 com->dtr_wait = 3 * hz;
946 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
947 com->no_irq = isa_get_irq(dev) < 0;
948 com->tx_fifo_size = 1;
949 com->obufs[0].l_head = com->obuf1;
950 com->obufs[1].l_head = com->obuf2;
952 com->iobase = iobase;
953 com->data_port = iobase + com_data;
954 com->int_id_port = iobase + com_iir;
955 com->modem_ctl_port = iobase + com_mcr;
956 com->mcr_image = inb(com->modem_ctl_port);
957 com->line_status_port = iobase + com_lsr;
958 com->modem_status_port = iobase + com_msr;
959 com->intr_ctl_port = iobase + com_ier;
962 * We don't use all the flags from <sys/ttydefaults.h> since they
963 * are only relevant for logins. It's important to have echo off
964 * initially so that the line doesn't start blathering before the
965 * echo flag can be turned off.
967 com->it_in.c_iflag = 0;
968 com->it_in.c_oflag = 0;
969 com->it_in.c_cflag = TTYDEF_CFLAG;
970 com->it_in.c_lflag = 0;
971 if (unit == comconsole) {
972 com->it_in.c_iflag = TTYDEF_IFLAG;
973 com->it_in.c_oflag = TTYDEF_OFLAG;
974 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
975 com->it_in.c_lflag = TTYDEF_LFLAG;
976 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
977 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
978 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
979 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
981 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
982 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
988 termioschars(&com->it_in);
989 com->it_out = com->it_in;
991 /* attempt to determine UART type */
992 printf("sio%d: type", unit);
996 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
998 if (!COM_IIR_TXRDYBUG(flags))
1005 scr = inb(iobase + com_scr);
1006 outb(iobase + com_scr, 0xa5);
1007 scr1 = inb(iobase + com_scr);
1008 outb(iobase + com_scr, 0x5a);
1009 scr2 = inb(iobase + com_scr);
1010 outb(iobase + com_scr, scr);
1011 if (scr1 != 0xa5 || scr2 != 0x5a) {
1013 goto determined_type;
1016 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1019 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1030 if (COM_NOFIFO(flags)) {
1031 printf(" 16550A fifo disabled");
1033 com->hasfifo = TRUE;
1034 if (COM_ST16650A(flags)) {
1036 com->tx_fifo_size = 32;
1037 printf(" ST16650A");
1039 com->tx_fifo_size = COM_FIFOSIZE(flags);
1044 for (espp = likely_esp_ports; *espp != 0; espp++)
1045 if (espattach(com, *espp)) {
1046 com->tx_fifo_size = 1024;
1050 if (!com->st16650a) {
1051 if (!com->tx_fifo_size)
1052 com->tx_fifo_size = 16;
1054 printf(" lookalike with %d bytes FIFO",
1064 * Set 16550 compatibility mode.
1065 * We don't use the ESP_MODE_SCALE bit to increase the
1066 * fifo trigger levels because we can't handle large
1068 * XXX flow control should be set in comparam(), not here.
1070 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1071 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1073 /* Set RTS/CTS flow control. */
1074 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1075 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1076 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1078 /* Set flow-control levels. */
1079 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1080 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1081 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1082 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1083 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1085 #endif /* COM_ESP */
1086 outb(iobase + com_fifo, 0);
1089 #ifdef COM_MULTIPORT
1090 if (COM_ISMULTIPORT(flags)) {
1091 com->multiport = TRUE;
1092 printf(" (multiport");
1093 if (unit == COM_MPMASTER(flags))
1097 isa_get_irq(devclass_get_device
1098 (sio_devclass, COM_MPMASTER(flags))) < 0;
1100 #endif /* COM_MULTIPORT */
1101 if (unit == comconsole)
1102 printf(", console");
1103 if ( COM_IIR_TXRDYBUG(flags) )
1104 printf(" with a bogus IIR_TXRDY register");
1107 if (!sio_registered) {
1108 register_swi(SWI_TTY, siopoll);
1109 sio_registered = TRUE;
1111 make_dev(&sio_cdevsw, unit,
1112 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1113 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
1114 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1115 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
1116 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1117 make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
1118 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1119 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE,
1120 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1121 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
1122 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1123 com->flags = isa_get_flags(dev); /* Heritate id_flags for later */
1124 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1125 pps_init(&com->pps);
1127 res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1,
1128 RF_SHAREABLE | RF_ACTIVE);
1129 BUS_SETUP_INTR(device_get_parent(dev), dev, res,
1130 INTR_TYPE_TTY | INTR_TYPE_FAST,
1137 sioopen(dev, flag, mode, p)
1152 unit = MINOR_TO_UNIT(mynor);
1153 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1157 if (mynor & CONTROL_MASK)
1159 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1162 * We jump to this label after all non-interrupted sleeps to pick
1163 * up any changes of the device state.
1166 while (com->state & CS_DTR_OFF) {
1167 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1168 if (com_addr(unit) == NULL)
1170 if (error != 0 || com->gone)
1173 if (tp->t_state & TS_ISOPEN) {
1175 * The device is open, so everything has been initialized.
1178 if (mynor & CALLOUT_MASK) {
1179 if (!com->active_out) {
1184 if (com->active_out) {
1185 if (flag & O_NONBLOCK) {
1189 error = tsleep(&com->active_out,
1190 TTIPRI | PCATCH, "siobi", 0);
1191 if (com_addr(unit) == NULL)
1193 if (error != 0 || com->gone)
1198 if (tp->t_state & TS_XCLUDE &&
1205 * The device isn't open, so there are no conflicts.
1206 * Initialize it. Initialization is done twice in many
1207 * cases: to preempt sleeping callin opens if we are
1208 * callout, and to complete a callin open after DCD rises.
1210 tp->t_oproc = comstart;
1211 tp->t_param = comparam;
1213 tp->t_termios = mynor & CALLOUT_MASK
1214 ? com->it_out : com->it_in;
1215 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1216 com->poll = com->no_irq;
1217 com->poll_output = com->loses_outints;
1219 error = comparam(tp, &tp->t_termios);
1224 * XXX we should goto open_top if comparam() slept.
1226 iobase = com->iobase;
1229 * (Re)enable and drain fifos.
1231 * Certain SMC chips cause problems if the fifos
1232 * are enabled while input is ready. Turn off the
1233 * fifo if necessary to clear the input. We test
1234 * the input ready bit after enabling the fifos
1235 * since we've already enabled them in comparam()
1236 * and to handle races between enabling and fresh
1240 outb(iobase + com_fifo,
1241 FIFO_RCV_RST | FIFO_XMT_RST
1244 * XXX the delays are for superstitious
1245 * historical reasons. It must be less than
1246 * the character time at the maximum
1247 * supported speed (87 usec at 115200 bps
1248 * 8N1). Otherwise we might loop endlessly
1249 * if data is streaming in. We used to use
1250 * delays of 100. That usually worked
1251 * because DELAY(100) used to usually delay
1252 * for about 85 usec instead of 100.
1255 if (!(inb(com->line_status_port) & LSR_RXRDY))
1257 outb(iobase + com_fifo, 0);
1259 (void) inb(com->data_port);
1264 (void) inb(com->line_status_port);
1265 (void) inb(com->data_port);
1266 com->prev_modem_status = com->last_modem_status
1267 = inb(com->modem_status_port);
1268 if (COM_IIR_TXRDYBUG(com->flags)) {
1269 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
1272 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
1273 | IER_ERLS | IER_EMSC);
1277 * Handle initial DCD. Callout devices get a fake initial
1278 * DCD (trapdoor DCD). If we are callout, then any sleeping
1279 * callin opens get woken up and resume sleeping on "siobi"
1280 * instead of "siodcd".
1283 * XXX `mynor & CALLOUT_MASK' should be
1284 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
1285 * TRAPDOOR_CARRIER is the default initial state for callout
1286 * devices and SOFT_CARRIER is like CLOCAL except it hides
1289 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
1290 (*linesw[tp->t_line].l_modem)(tp, 1);
1293 * Wait for DCD if necessary.
1295 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
1296 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
1298 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
1299 if (com_addr(unit) == NULL)
1302 if (error != 0 || com->gone)
1306 error = (*linesw[tp->t_line].l_open)(dev, tp);
1307 disc_optim(tp, &tp->t_termios, com);
1308 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
1309 com->active_out = TRUE;
1313 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
1319 sioclose(dev, flag, mode, p)
1331 if (mynor & CONTROL_MASK)
1333 com = com_addr(MINOR_TO_UNIT(mynor));
1336 (*linesw[tp->t_line].l_close)(tp, flag);
1337 disc_optim(tp, &tp->t_termios, com);
1338 siostop(tp, FREAD | FWRITE);
1344 printf("sio%d: gone\n", com->unit);
1346 if (com->ibuf != NULL)
1347 free(com->ibuf, M_DEVBUF);
1348 bzero(tp, sizeof *tp);
1349 free(com, M_DEVBUF);
1365 iobase = com->iobase;
1368 com->poll_output = FALSE;
1369 com->do_timestamp = FALSE;
1370 com->do_dcd_timestamp = FALSE;
1371 com->pps.ppsparam.mode = 0;
1372 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1374 outb(iobase + com_ier, 0);
1376 if (tp->t_cflag & HUPCL
1378 * XXX we will miss any carrier drop between here and the
1379 * next open. Perhaps we should watch DCD even when the
1380 * port is closed; it is not sufficient to check it at
1381 * the next open because it might go up and down while
1382 * we're not watching.
1384 || (!com->active_out
1385 && !(com->prev_modem_status & MSR_DCD)
1386 && !(com->it_in.c_cflag & CLOCAL))
1387 || !(tp->t_state & TS_ISOPEN)) {
1388 (void)commctl(com, TIOCM_DTR, DMBIC);
1389 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
1390 timeout(siodtrwakeup, com, com->dtr_wait);
1391 com->state |= CS_DTR_OFF;
1397 * Disable fifos so that they are off after controlled
1398 * reboots. Some BIOSes fail to detect 16550s when the
1399 * fifos are enabled.
1401 outb(iobase + com_fifo, 0);
1403 com->active_out = FALSE;
1404 wakeup(&com->active_out);
1405 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1410 sioread(dev, uio, flag)
1419 if (mynor & CONTROL_MASK)
1421 com = com_addr(MINOR_TO_UNIT(mynor));
1424 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
1428 siowrite(dev, uio, flag)
1438 if (mynor & CONTROL_MASK)
1441 unit = MINOR_TO_UNIT(mynor);
1442 com = com_addr(unit);
1446 * (XXX) We disallow virtual consoles if the physical console is
1447 * a serial port. This is in case there is a display attached that
1448 * is not the console. In that situation we don't need/want the X
1449 * server taking over the console.
1451 if (constty != NULL && unit == comconsole)
1453 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
1463 com = (struct com_s *)chan;
1466 * Clear TS_BUSY if low-level output is complete.
1467 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1468 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1469 * called again. Reading the line status port outside of siointr1()
1470 * is safe because CS_BUSY is clear so there are no output interrupts
1474 if (com->state & CS_BUSY)
1475 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1476 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
1477 == (LSR_TSRE | LSR_TXRDY)) {
1478 com->tp->t_state &= ~TS_BUSY;
1480 com->extra_state &= ~CSE_BUSYCHECK;
1482 timeout(siobusycheck, com, hz / 100);
1492 com = (struct com_s *)chan;
1493 com->state &= ~CS_DTR_OFF;
1494 wakeup(&com->dtr_wait);
1509 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
1510 com_events -= (com->iptr - com->ibuf);
1511 com->iptr = com->ibuf;
1514 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
1516 * Avoid the grotesquely inefficient lineswitch routine
1517 * (ttyinput) in "raw" mode. It usually takes about 450
1518 * instructions (that's without canonical processing or echo!).
1519 * slinput is reasonably fast (usually 40 instructions plus
1524 incc = com->iptr - buf;
1525 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
1526 && (com->state & CS_RTS_IFLOW
1527 || tp->t_iflag & IXOFF)
1528 && !(tp->t_state & TS_TBLOCK))
1530 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
1531 += b_to_q((char *)buf, incc, &tp->t_rawq);
1535 tp->t_rawcc += incc;
1537 if (tp->t_state & TS_TTSTOP
1538 && (tp->t_iflag & IXANY
1539 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
1540 tp->t_state &= ~TS_TTSTOP;
1541 tp->t_lflag &= ~FLUSHO;
1545 } while (buf < com->iptr);
1549 line_status = buf[com->ierroff];
1552 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
1553 if (line_status & LSR_BI)
1554 recv_data |= TTY_BI;
1555 if (line_status & LSR_FE)
1556 recv_data |= TTY_FE;
1557 if (line_status & LSR_OE)
1558 recv_data |= TTY_OE;
1559 if (line_status & LSR_PE)
1560 recv_data |= TTY_PE;
1562 (*linesw[tp->t_line].l_rint)(recv_data, tp);
1564 } while (buf < com->iptr);
1566 com_events -= (com->iptr - com->ibuf);
1567 com->iptr = com->ibuf;
1570 * There is now room for another low-level buffer full of input,
1571 * so enable RTS if it is now disabled and there is room in the
1572 * high-level buffer.
1574 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
1575 !(tp->t_state & TS_TBLOCK))
1576 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
1583 #ifndef COM_MULTIPORT
1585 siointr1((struct com_s *) arg);
1587 #else /* COM_MULTIPORT */
1588 bool_t possibly_more_intrs;
1593 * Loop until there is no activity on any port. This is necessary
1594 * to get an interrupt edge more than to avoid another interrupt.
1595 * If the IRQ signal is just an OR of the IRQ signals from several
1596 * devices, then the edge from one may be lost because another is
1601 possibly_more_intrs = FALSE;
1602 for (unit = 0; unit < NSIOTOT; ++unit) {
1603 com = com_addr(unit);
1606 * would it work here, or be counter-productive?
1610 && (inb(com->int_id_port) & IIR_IMASK)
1613 possibly_more_intrs = TRUE;
1615 /* XXX COM_UNLOCK(); */
1617 } while (possibly_more_intrs);
1619 #endif /* COM_MULTIPORT */
1627 u_char modem_status;
1632 struct timecounter *tc;
1635 int_ctl = inb(com->intr_ctl_port);
1636 int_ctl_new = int_ctl;
1638 while (!com->gone) {
1639 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
1640 modem_status = inb(com->modem_status_port);
1641 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
1643 count = tc->tc_get_timecount(tc);
1644 pps_event(&com->pps, tc, count,
1645 (modem_status & MSR_DCD) ?
1646 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
1649 line_status = inb(com->line_status_port);
1651 /* input event? (check first to help avoid overruns) */
1652 while (line_status & LSR_RCV_MASK) {
1653 /* break/unnattached error bits or real input? */
1654 if (!(line_status & LSR_RXRDY))
1657 recv_data = inb(com->data_port);
1658 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
1660 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
1661 * Otherwise, push the work to a higher level
1662 * (to handle PARMRK) if we're bypassing.
1663 * Otherwise, convert BI/FE and PE+INPCK to 0.
1665 * This makes bypassing work right in the
1666 * usual "raw" case (IGNBRK set, and IGNPAR
1669 * Note: BI together with FE/PE means just BI.
1671 if (line_status & LSR_BI) {
1672 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
1673 if (com->unit == comconsole) {
1679 || com->tp->t_iflag & IGNBRK)
1683 || com->tp->t_iflag & IGNPAR)
1686 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
1687 && (line_status & (LSR_BI | LSR_FE)
1688 || com->tp->t_iflag & INPCK))
1692 if (com->hotchar != 0 && recv_data == com->hotchar)
1695 if (ioptr >= com->ibufend)
1696 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
1698 if (com->do_timestamp)
1699 microtime(&com->timestamp);
1702 #if 0 /* for testing input latency vs efficiency */
1703 if (com->iptr - com->ibuf == 8)
1706 ioptr[0] = recv_data;
1707 ioptr[com->ierroff] = line_status;
1708 com->iptr = ++ioptr;
1709 if (ioptr == com->ihighwater
1710 && com->state & CS_RTS_IFLOW)
1711 outb(com->modem_ctl_port,
1712 com->mcr_image &= ~MCR_RTS);
1713 if (line_status & LSR_OE)
1714 CE_RECORD(com, CE_OVERRUN);
1718 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
1719 * jump from the top of the loop to here
1721 line_status = inb(com->line_status_port) & 0x7F;
1724 /* modem status change? (always check before doing output) */
1725 modem_status = inb(com->modem_status_port);
1726 if (modem_status != com->last_modem_status) {
1727 if (com->do_dcd_timestamp
1728 && !(com->last_modem_status & MSR_DCD)
1729 && modem_status & MSR_DCD)
1730 microtime(&com->dcd_timestamp);
1733 * Schedule high level to handle DCD changes. Note
1734 * that we don't use the delta bits anywhere. Some
1735 * UARTs mess them up, and it's easy to remember the
1736 * previous bits and calculate the delta.
1738 com->last_modem_status = modem_status;
1739 if (!(com->state & CS_CHECKMSR)) {
1740 com_events += LOTS_OF_EVENTS;
1741 com->state |= CS_CHECKMSR;
1745 /* handle CTS change immediately for crisp flow ctl */
1746 if (com->state & CS_CTS_OFLOW) {
1747 if (modem_status & MSR_CTS)
1748 com->state |= CS_ODEVREADY;
1750 com->state &= ~CS_ODEVREADY;
1754 /* output queued and everything ready? */
1755 if (line_status & LSR_TXRDY
1756 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
1757 ioptr = com->obufq.l_head;
1758 if (com->tx_fifo_size > 1) {
1761 ocount = com->obufq.l_tail - ioptr;
1762 if (ocount > com->tx_fifo_size)
1763 ocount = com->tx_fifo_size;
1764 com->bytes_out += ocount;
1766 outb(com->data_port, *ioptr++);
1767 while (--ocount != 0);
1769 outb(com->data_port, *ioptr++);
1772 com->obufq.l_head = ioptr;
1773 if (COM_IIR_TXRDYBUG(com->flags)) {
1774 int_ctl_new = int_ctl | IER_ETXRDY;
1776 if (ioptr >= com->obufq.l_tail) {
1779 qp = com->obufq.l_next;
1780 qp->l_queued = FALSE;
1783 com->obufq.l_head = qp->l_head;
1784 com->obufq.l_tail = qp->l_tail;
1785 com->obufq.l_next = qp;
1787 /* output just completed */
1788 if ( COM_IIR_TXRDYBUG(com->flags) ) {
1789 int_ctl_new = int_ctl & ~IER_ETXRDY;
1791 com->state &= ~CS_BUSY;
1793 if (!(com->state & CS_ODONE)) {
1794 com_events += LOTS_OF_EVENTS;
1795 com->state |= CS_ODONE;
1796 setsofttty(); /* handle at high level ASAP */
1799 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
1800 outb(com->intr_ctl_port, int_ctl_new);
1805 #ifndef COM_MULTIPORT
1806 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
1807 #endif /* COM_MULTIPORT */
1813 sioioctl(dev, cmd, data, flag, p)
1826 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1828 struct termios term;
1832 com = com_addr(MINOR_TO_UNIT(mynor));
1835 iobase = com->iobase;
1836 if (mynor & CONTROL_MASK) {
1839 switch (mynor & CONTROL_MASK) {
1840 case CONTROL_INIT_STATE:
1841 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
1843 case CONTROL_LOCK_STATE:
1844 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
1847 return (ENODEV); /* /dev/nodev */
1854 *ct = *(struct termios *)data;
1857 *(struct termios *)data = *ct;
1860 *(int *)data = TTYDISC;
1863 bzero(data, sizeof(struct winsize));
1870 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
1871 term = tp->t_termios;
1873 error = ttsetcompat(tp, &cmd, data, &term);
1877 data = (caddr_t)&term;
1879 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
1881 struct termios *dt = (struct termios *)data;
1882 struct termios *lt = mynor & CALLOUT_MASK
1883 ? &com->lt_out : &com->lt_in;
1885 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
1886 | (dt->c_iflag & ~lt->c_iflag);
1887 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
1888 | (dt->c_oflag & ~lt->c_oflag);
1889 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
1890 | (dt->c_cflag & ~lt->c_cflag);
1891 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
1892 | (dt->c_lflag & ~lt->c_lflag);
1893 for (cc = 0; cc < NCCS; ++cc)
1894 if (lt->c_cc[cc] != 0)
1895 dt->c_cc[cc] = tp->t_cc[cc];
1896 if (lt->c_ispeed != 0)
1897 dt->c_ispeed = tp->t_ispeed;
1898 if (lt->c_ospeed != 0)
1899 dt->c_ospeed = tp->t_ospeed;
1901 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1902 if (error != ENOIOCTL)
1905 error = ttioctl(tp, cmd, data, flag);
1906 disc_optim(tp, &tp->t_termios, com);
1907 if (error != ENOIOCTL) {
1913 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
1916 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1919 (void)commctl(com, TIOCM_DTR, DMBIS);
1922 (void)commctl(com, TIOCM_DTR, DMBIC);
1925 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
1926 * changes get undone on the next call to comparam().
1929 (void)commctl(com, *(int *)data, DMSET);
1932 (void)commctl(com, *(int *)data, DMBIS);
1935 (void)commctl(com, *(int *)data, DMBIC);
1938 *(int *)data = commctl(com, 0, DMGET);
1941 /* must be root since the wait applies to following logins */
1947 com->dtr_wait = *(int *)data * hz / 100;
1950 *(int *)data = com->dtr_wait * 100 / hz;
1953 com->do_timestamp = TRUE;
1954 *(struct timeval *)data = com->timestamp;
1956 case TIOCDCDTIMESTAMP:
1957 com->do_dcd_timestamp = TRUE;
1958 *(struct timeval *)data = com->dcd_timestamp;
1962 error = pps_ioctl(cmd, data, &com->pps);
1963 if (error == ENODEV)
1976 if (com_events == 0)
1979 for (unit = 0; unit < NSIOTOT; ++unit) {
1984 com = com_addr(unit);
1988 if (tp == NULL || com->gone) {
1990 * Discard any events related to never-opened or
1991 * going-away devices.
1994 incc = com->iptr - com->ibuf;
1995 com->iptr = com->ibuf;
1996 if (com->state & CS_CHECKMSR) {
1997 incc += LOTS_OF_EVENTS;
1998 com->state &= ~CS_CHECKMSR;
2004 if (com->iptr != com->ibuf) {
2009 if (com->state & CS_CHECKMSR) {
2010 u_char delta_modem_status;
2013 delta_modem_status = com->last_modem_status
2014 ^ com->prev_modem_status;
2015 com->prev_modem_status = com->last_modem_status;
2016 com_events -= LOTS_OF_EVENTS;
2017 com->state &= ~CS_CHECKMSR;
2019 if (delta_modem_status & MSR_DCD)
2020 (*linesw[tp->t_line].l_modem)
2021 (tp, com->prev_modem_status & MSR_DCD);
2023 if (com->state & CS_ODONE) {
2025 com_events -= LOTS_OF_EVENTS;
2026 com->state &= ~CS_ODONE;
2028 if (!(com->state & CS_BUSY)
2029 && !(com->extra_state & CSE_BUSYCHECK)) {
2030 timeout(siobusycheck, com, hz / 100);
2031 com->extra_state |= CSE_BUSYCHECK;
2033 (*linesw[tp->t_line].l_start)(tp);
2035 if (com_events == 0)
2038 if (com_events >= LOTS_OF_EVENTS)
2057 /* do historical conversions */
2058 if (t->c_ispeed == 0)
2059 t->c_ispeed = t->c_ospeed;
2061 /* check requested parameters */
2062 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
2063 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
2066 /* parameters are OK, convert them to the com struct and the device */
2067 unit = DEV_TO_UNIT(tp->t_dev);
2068 com = com_addr(unit);
2069 iobase = com->iobase;
2072 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2074 (void)commctl(com, TIOCM_DTR, DMBIS);
2076 switch (cflag & CSIZE) {
2090 if (cflag & PARENB) {
2092 if (!(cflag & PARODD))
2098 if (com->hasfifo && divisor != 0) {
2100 * Use a fifo trigger level low enough so that the input
2101 * latency from the fifo is less than about 16 msec and
2102 * the total latency is less than about 30 msec. These
2103 * latencies are reasonable for humans. Serial comms
2104 * protocols shouldn't expect anything better since modem
2105 * latencies are larger.
2107 com->fifo_image = t->c_ospeed <= 4800
2108 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
2111 * The Hayes ESP card needs the fifo DMA mode bit set
2112 * in compatibility mode. If not, it will interrupt
2113 * for each character received.
2116 com->fifo_image |= FIFO_DMA_MODE;
2118 outb(iobase + com_fifo, com->fifo_image);
2122 * This returns with interrupts disabled so that we can complete
2123 * the speed change atomically. Keeping interrupts disabled is
2124 * especially important while com_data is hidden.
2126 (void) siosetwater(com, t->c_ispeed);
2129 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
2131 * Only set the divisor registers if they would change,
2132 * since on some 16550 incompatibles (UMC8669F), setting
2133 * them while input is arriving them loses sync until
2134 * data stops arriving.
2136 dlbl = divisor & 0xFF;
2137 if (inb(iobase + com_dlbl) != dlbl)
2138 outb(iobase + com_dlbl, dlbl);
2139 dlbh = (u_int) divisor >> 8;
2140 if (inb(iobase + com_dlbh) != dlbh)
2141 outb(iobase + com_dlbh, dlbh);
2145 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
2147 if (!(tp->t_state & TS_TTSTOP))
2148 com->state |= CS_TTGO;
2150 if (cflag & CRTS_IFLOW) {
2151 if (com->st16650a) {
2152 outb(iobase + com_cfcr, 0xbf);
2153 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
2155 com->state |= CS_RTS_IFLOW;
2157 * If CS_RTS_IFLOW just changed from off to on, the change
2158 * needs to be propagated to MCR_RTS. This isn't urgent,
2159 * so do it later by calling comstart() instead of repeating
2160 * a lot of code from comstart() here.
2162 } else if (com->state & CS_RTS_IFLOW) {
2163 com->state &= ~CS_RTS_IFLOW;
2165 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2166 * on here, since comstart() won't do it later.
2168 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2169 if (com->st16650a) {
2170 outb(iobase + com_cfcr, 0xbf);
2171 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
2177 * Set up state to handle output flow control.
2178 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2179 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2181 com->state |= CS_ODEVREADY;
2182 com->state &= ~CS_CTS_OFLOW;
2183 if (cflag & CCTS_OFLOW) {
2184 com->state |= CS_CTS_OFLOW;
2185 if (!(com->last_modem_status & MSR_CTS))
2186 com->state &= ~CS_ODEVREADY;
2187 if (com->st16650a) {
2188 outb(iobase + com_cfcr, 0xbf);
2189 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
2192 if (com->st16650a) {
2193 outb(iobase + com_cfcr, 0xbf);
2194 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
2199 outb(iobase + com_cfcr, com->cfcr_image);
2202 /* XXX shouldn't call functions while intrs are disabled. */
2203 disc_optim(tp, t, com);
2205 * Recover from fiddling with CS_TTGO. We used to call siointr1()
2206 * unconditionally, but that defeated the careful discarding of
2207 * stale input in sioopen().
2209 if (com->state >= (CS_BUSY | CS_TTGO))
2215 if (com->ibufold != NULL) {
2216 free(com->ibufold, M_DEVBUF);
2217 com->ibufold = NULL;
2223 siosetwater(com, speed)
2233 * Make the buffer size large enough to handle a softtty interrupt
2234 * latency of about 2 ticks without loss of throughput or data
2235 * (about 3 ticks if input flow control is not used or not honoured,
2236 * but a bit less for CS5-CS7 modes).
2238 cp4ticks = speed / 10 / hz * 4;
2239 for (ibufsize = 128; ibufsize < cp4ticks;)
2241 if (ibufsize == com->ibufsize) {
2247 * Allocate input buffer. The extra factor of 2 in the size is
2248 * to allow for an error byte for each input byte.
2250 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
2256 /* Initialize non-critical variables. */
2257 com->ibufold = com->ibuf;
2258 com->ibufsize = ibufsize;
2261 tp->t_ififosize = 2 * ibufsize;
2262 tp->t_ispeedwat = (speed_t)-1;
2263 tp->t_ospeedwat = (speed_t)-1;
2267 * Read current input buffer, if any. Continue with interrupts
2271 if (com->iptr != com->ibuf)
2275 * Initialize critical variables, including input buffer watermarks.
2276 * The external device is asked to stop sending when the buffer
2277 * exactly reaches high water, or when the high level requests it.
2278 * The high level is notified immediately (rather than at a later
2279 * clock tick) when this watermark is reached.
2280 * The buffer size is chosen so the watermark should almost never
2282 * The low watermark is invisibly 0 since the buffer is always
2283 * emptied all at once.
2285 com->iptr = com->ibuf = ibuf;
2286 com->ibufend = ibuf + ibufsize;
2287 com->ierroff = ibufsize;
2288 com->ihighwater = ibuf + 3 * ibufsize / 4;
2300 unit = DEV_TO_UNIT(tp->t_dev);
2301 com = com_addr(unit);
2304 if (tp->t_state & TS_TTSTOP)
2305 com->state &= ~CS_TTGO;
2307 com->state |= CS_TTGO;
2308 if (tp->t_state & TS_TBLOCK) {
2309 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
2310 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
2312 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
2313 && com->state & CS_RTS_IFLOW)
2314 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2317 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
2322 if (tp->t_outq.c_cc != 0) {
2326 if (!com->obufs[0].l_queued) {
2327 com->obufs[0].l_tail
2328 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
2330 com->obufs[0].l_next = NULL;
2331 com->obufs[0].l_queued = TRUE;
2333 if (com->state & CS_BUSY) {
2334 qp = com->obufq.l_next;
2335 while ((next = qp->l_next) != NULL)
2337 qp->l_next = &com->obufs[0];
2339 com->obufq.l_head = com->obufs[0].l_head;
2340 com->obufq.l_tail = com->obufs[0].l_tail;
2341 com->obufq.l_next = &com->obufs[0];
2342 com->state |= CS_BUSY;
2346 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
2347 com->obufs[1].l_tail
2348 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
2350 com->obufs[1].l_next = NULL;
2351 com->obufs[1].l_queued = TRUE;
2353 if (com->state & CS_BUSY) {
2354 qp = com->obufq.l_next;
2355 while ((next = qp->l_next) != NULL)
2357 qp->l_next = &com->obufs[1];
2359 com->obufq.l_head = com->obufs[1].l_head;
2360 com->obufq.l_tail = com->obufs[1].l_tail;
2361 com->obufq.l_next = &com->obufs[1];
2362 com->state |= CS_BUSY;
2366 tp->t_state |= TS_BUSY;
2369 if (com->state >= (CS_BUSY | CS_TTGO))
2370 siointr1(com); /* fake interrupt to start output */
2383 com = com_addr(DEV_TO_UNIT(tp->t_dev));
2390 /* XXX avoid h/w bug. */
2393 outb(com->iobase + com_fifo,
2394 FIFO_XMT_RST | com->fifo_image);
2395 com->obufs[0].l_queued = FALSE;
2396 com->obufs[1].l_queued = FALSE;
2397 if (com->state & CS_ODONE)
2398 com_events -= LOTS_OF_EVENTS;
2399 com->state &= ~(CS_ODONE | CS_BUSY);
2400 com->tp->t_state &= ~TS_BUSY;
2405 /* XXX avoid h/w bug. */
2408 outb(com->iobase + com_fifo,
2409 FIFO_RCV_RST | com->fifo_image);
2410 com_events -= (com->iptr - com->ibuf);
2411 com->iptr = com->ibuf;
2425 if (mynor & CONTROL_MASK)
2427 unit = MINOR_TO_UNIT(mynor);
2428 if ((u_int) unit >= NSIOTOT)
2430 return (dev->si_tty);
2434 commctl(com, bits, how)
2443 bits = TIOCM_LE; /* XXX - always enabled while open */
2444 mcr = com->mcr_image;
2449 msr = com->prev_modem_status;
2457 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
2458 * more volatile by reading the modem status a lot. Perhaps
2459 * we should latch both bits until the status is read here.
2461 if (msr & (MSR_RI | MSR_TERI))
2466 if (bits & TIOCM_DTR)
2468 if (bits & TIOCM_RTS)
2475 outb(com->modem_ctl_port,
2476 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
2479 outb(com->modem_ctl_port, com->mcr_image |= mcr);
2482 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
2497 * Set our timeout period to 1 second if no polled devices are open.
2498 * Otherwise set it to max(1/200, 1/hz).
2499 * Enable timeouts iff some device is open.
2501 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2504 for (unit = 0; unit < NSIOTOT; ++unit) {
2505 com = com_addr(unit);
2506 if (com != NULL && com->tp != NULL
2507 && com->tp->t_state & TS_ISOPEN && !com->gone) {
2509 if (com->poll || com->poll_output) {
2510 sio_timeout = hz > 200 ? hz / 200 : 1;
2516 sio_timeouts_until_log = hz / sio_timeout;
2517 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
2520 /* Flush error messages, if any. */
2521 sio_timeouts_until_log = 1;
2522 comwakeup((void *)NULL);
2523 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
2534 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
2537 * Recover from lost output interrupts.
2538 * Poll any lines that don't use interrupts.
2540 for (unit = 0; unit < NSIOTOT; ++unit) {
2541 com = com_addr(unit);
2542 if (com != NULL && !com->gone
2543 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
2551 * Check for and log errors, but not too often.
2553 if (--sio_timeouts_until_log > 0)
2555 sio_timeouts_until_log = hz / sio_timeout;
2556 for (unit = 0; unit < NSIOTOT; ++unit) {
2559 com = com_addr(unit);
2564 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
2569 delta = com->delta_error_counts[errnum];
2570 com->delta_error_counts[errnum] = 0;
2574 total = com->error_counts[errnum] += delta;
2575 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
2576 unit, delta, error_desc[errnum],
2577 delta == 1 ? "" : "s", total);
2583 disc_optim(tp, t, com)
2588 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
2589 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
2590 && (!(t->c_iflag & PARMRK)
2591 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
2592 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
2593 && linesw[tp->t_line].l_rint == ttyinput)
2594 tp->t_state |= TS_CAN_BYPASS_L_RINT;
2596 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
2597 com->hotchar = linesw[tp->t_line].l_hotchar;
2601 * Following are all routines needed for SIO to act as console
2603 #include <sys/cons.h>
2613 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
2614 static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
2615 static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
2616 static void siocntxwait __P((Port_t iobase));
2618 static cn_probe_t siocnprobe;
2619 static cn_init_t siocninit;
2620 static cn_checkc_t siocncheckc;
2621 static cn_getc_t siocngetc;
2622 static cn_putc_t siocnputc;
2625 CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc);
2629 /* To get the GDB related variables */
2631 #include <ddb/ddb.h>
2641 * Wait for any pending transmission to finish. Required to avoid
2642 * the UART lockup bug when the speed is changed, and for normal
2646 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
2647 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
2652 * Read the serial port specified and try to figure out what speed
2653 * it's currently running at. We're assuming the serial port has
2654 * been initialized and is basicly idle. This routine is only intended
2655 * to be run at system startup.
2657 * If the value read from the serial port doesn't make sense, return 0.
2661 siocngetspeed(iobase, table)
2663 struct speedtab *table;
2670 cfcr = inb(iobase + com_cfcr);
2671 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2673 dlbl = inb(iobase + com_dlbl);
2674 dlbh = inb(iobase + com_dlbh);
2676 outb(iobase + com_cfcr, cfcr);
2678 code = dlbh << 8 | dlbl;
2680 for ( ; table->sp_speed != -1; table++)
2681 if (table->sp_code == code)
2682 return (table->sp_speed);
2684 return 0; /* didn't match anything sane */
2688 siocnopen(sp, iobase, speed)
2689 struct siocnstate *sp;
2698 * Save all the device control registers except the fifo register
2699 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2700 * We can't save the fifo register since it is read-only.
2702 sp->ier = inb(iobase + com_ier);
2703 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
2704 siocntxwait(iobase);
2705 sp->cfcr = inb(iobase + com_cfcr);
2706 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2707 sp->dlbl = inb(iobase + com_dlbl);
2708 sp->dlbh = inb(iobase + com_dlbh);
2710 * Only set the divisor registers if they would change, since on
2711 * some 16550 incompatibles (Startech), setting them clears the
2712 * data input register. This also reduces the effects of the
2715 divisor = ttspeedtab(speed, comspeedtab);
2716 dlbl = divisor & 0xFF;
2717 if (sp->dlbl != dlbl)
2718 outb(iobase + com_dlbl, dlbl);
2719 dlbh = (u_int) divisor >> 8;
2720 if (sp->dlbh != dlbh)
2721 outb(iobase + com_dlbh, dlbh);
2722 outb(iobase + com_cfcr, CFCR_8BITS);
2723 sp->mcr = inb(iobase + com_mcr);
2725 * We don't want interrupts, but must be careful not to "disable"
2726 * them by clearing the MCR_IENABLE bit, since that might cause
2727 * an interrupt by floating the IRQ line.
2729 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
2733 siocnclose(sp, iobase)
2734 struct siocnstate *sp;
2738 * Restore the device control registers.
2740 siocntxwait(iobase);
2741 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
2742 if (sp->dlbl != inb(iobase + com_dlbl))
2743 outb(iobase + com_dlbl, sp->dlbl);
2744 if (sp->dlbh != inb(iobase + com_dlbh))
2745 outb(iobase + com_dlbh, sp->dlbh);
2746 outb(iobase + com_cfcr, sp->cfcr);
2748 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
2750 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
2751 outb(iobase + com_ier, sp->ier);
2761 struct siocnstate sp;
2764 * Find our first enabled console, if any. If it is a high-level
2765 * console device, then initialize it and return successfully.
2766 * If it is a low-level console device, then initialize it and
2767 * return unsuccessfully. It must be initialized in both cases
2768 * for early use by console drivers and debuggers. Initializing
2769 * the hardware is not necessary in all cases, since the i/o
2770 * routines initialize it on the fly, but it is necessary if
2771 * input might arrive while the hardware is switched back to an
2772 * uninitialized state. We can't handle multiple console devices
2773 * yet because our low-level routines don't take a device arg.
2774 * We trust the user to set the console flags properly so that we
2775 * don't need to probe.
2777 cp->cn_pri = CN_DEAD;
2779 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
2782 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
2786 if (resource_int_value("sio", unit, "flags", &flags))
2788 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
2792 if (resource_int_value("sio", unit, "port", &port))
2796 if (boothowto & RB_SERIAL) {
2797 boot_speed = siocngetspeed(iobase, comspeedtab);
2799 comdefaultrate = boot_speed;
2803 * Initialize the divisor latch. We can't rely on
2804 * siocnopen() to do this the first time, since it
2805 * avoids writing to the latch if the latch appears
2806 * to have the correct value. Also, if we didn't
2807 * just read the speed from the hardware, then we
2808 * need to set the speed in hardware so that
2809 * switching it later is null.
2811 cfcr = inb(iobase + com_cfcr);
2812 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2813 outb(iobase + com_dlbl,
2814 COMBRD(comdefaultrate) & 0xff);
2815 outb(iobase + com_dlbh,
2816 (u_int) COMBRD(comdefaultrate) >> 8);
2817 outb(iobase + com_cfcr, cfcr);
2819 siocnopen(&sp, iobase, comdefaultrate);
2822 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2823 cp->cn_dev = makedev(CDEV_MAJOR, unit);
2824 cp->cn_pri = COM_FORCECONSOLE(flags)
2825 || boothowto & RB_SERIAL
2826 ? CN_REMOTE : CN_NORMAL;
2827 siocniobase = iobase;
2830 if (COM_DEBUGGER(flags)) {
2831 printf("sio%d: gdb debugging port\n", unit);
2832 siogdbiobase = iobase;
2835 gdbdev = makedev(CDEV_MAJOR, unit);
2836 gdb_getc = siocngetc;
2837 gdb_putc = siocnputc;
2845 * XXX Ugly Compatability.
2846 * If no gdb port has been specified, set it to be the console
2847 * as some configuration files don't specify the gdb port.
2849 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
2850 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
2852 printf("Set flag 0x80 on desired GDB port in your\n");
2853 printf("configuration file (currently sio only).\n");
2854 siogdbiobase = siocniobase;
2855 siogdbunit = siocnunit;
2856 gdbdev = makedev(CDEV_MAJOR, siocnunit);
2857 gdb_getc = siocngetc;
2858 gdb_putc = siocnputc;
2866 CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc);
2869 siocnattach(port, speed)
2875 struct siocnstate sp;
2878 comdefaultrate = speed;
2879 sio_consdev.cn_pri = CN_NORMAL;
2880 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
2885 * Initialize the divisor latch. We can't rely on
2886 * siocnopen() to do this the first time, since it
2887 * avoids writing to the latch if the latch appears
2888 * to have the correct value. Also, if we didn't
2889 * just read the speed from the hardware, then we
2890 * need to set the speed in hardware so that
2891 * switching it later is null.
2893 cfcr = inb(siocniobase + com_cfcr);
2894 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
2895 outb(siocniobase + com_dlbl,
2896 COMBRD(comdefaultrate) & 0xff);
2897 outb(siocniobase + com_dlbh,
2898 (u_int) COMBRD(comdefaultrate) >> 8);
2899 outb(siocniobase + com_cfcr, cfcr);
2901 siocnopen(&sp, siocniobase, comdefaultrate);
2904 cn_tab = &sio_consdev;
2909 siogdbattach(port, speed)
2915 struct siocnstate sp;
2917 siogdbiobase = port;
2918 gdbdefaultrate = speed;
2923 * Initialize the divisor latch. We can't rely on
2924 * siocnopen() to do this the first time, since it
2925 * avoids writing to the latch if the latch appears
2926 * to have the correct value. Also, if we didn't
2927 * just read the speed from the hardware, then we
2928 * need to set the speed in hardware so that
2929 * switching it later is null.
2931 cfcr = inb(siogdbiobase + com_cfcr);
2932 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
2933 outb(siogdbiobase + com_dlbl,
2934 COMBRD(gdbdefaultrate) & 0xff);
2935 outb(siogdbiobase + com_dlbh,
2936 (u_int) COMBRD(gdbdefaultrate) >> 8);
2937 outb(siogdbiobase + com_cfcr, cfcr);
2939 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
2951 comconsole = DEV_TO_UNIT(cp->cn_dev);
2961 struct siocnstate sp;
2963 if (minor(dev) == siogdbunit)
2964 iobase = siogdbiobase;
2966 iobase = siocniobase;
2968 siocnopen(&sp, iobase, comdefaultrate);
2969 if (inb(iobase + com_lsr) & LSR_RXRDY)
2970 c = inb(iobase + com_data);
2973 siocnclose(&sp, iobase);
2986 struct siocnstate sp;
2988 if (minor(dev) == siogdbunit)
2989 iobase = siogdbiobase;
2991 iobase = siocniobase;
2993 siocnopen(&sp, iobase, comdefaultrate);
2994 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
2996 c = inb(iobase + com_data);
2997 siocnclose(&sp, iobase);
3008 struct siocnstate sp;
3011 if (minor(dev) == siogdbunit)
3012 iobase = siogdbiobase;
3014 iobase = siocniobase;
3016 siocnopen(&sp, iobase, comdefaultrate);
3017 siocntxwait(iobase);
3018 outb(iobase + com_data, c);
3019 siocnclose(&sp, iobase);
3030 struct siocnstate sp;
3032 iobase = siogdbiobase;
3034 siocnopen(&sp, iobase, gdbdefaultrate);
3035 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
3037 c = inb(iobase + com_data);
3038 siocnclose(&sp, iobase);
3048 struct siocnstate sp;
3051 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3052 siocntxwait(siogdbiobase);
3053 outb(siogdbiobase + com_data, c);
3054 siocnclose(&sp, siogdbiobase);
3059 DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass, sio_cdevsw, 0, 0);