sys/legacy/dev/usb/if_urtwreg.h

   1 /*      $FreeBSD$       */
   2
   3 /*-
   4  * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  */
  18
  19 #define URTW_CONFIG_NO                  1
  20 #define URTW_IFACE_INDEX                0
  21
  22 /* for 8187  */
  23 #define URTW_MAC0                       0x0000          /* 1 byte  */
  24 #define URTW_MAC1                       0x0001          /* 1 byte  */
  25 #define URTW_MAC2                       0x0002          /* 1 byte  */
  26 #define URTW_MAC3                       0x0003          /* 1 byte  */
  27 #define URTW_MAC4                       0x0004          /* 1 byte  */
  28 #define URTW_MAC5                       0x0005          /* 1 byte  */
  29 #define URTW_BRSR                       0x002c          /* 2 byte  */
  30 #define URTW_BRSR_MBR_8185              (0x0fff)
  31 #define URTW_BSSID                      0x002e          /* 6 byte  */
  32 #define URTW_RESP_RATE                  0x0034          /* 1 byte  */
  33 #define URTW_RESP_MAX_RATE_SHIFT        (4)
  34 #define URTW_RESP_MIN_RATE_SHIFT        (0)
  35 #define URTW_EIFS                       0x0035          /* 1 byte  */
  36 #define URTW_INTR_MASK                  0x003c          /* 2 byte  */
  37 #define URTW_CMD                        0x0037          /* 1 byte  */
  38 #define URTW_CMD_TX_ENABLE              (0x4)
  39 #define URTW_CMD_RX_ENABLE              (0x8)
  40 #define URTW_CMD_RST                    (0x10)
  41 #define URTW_TX_CONF                    0x0040          /* 4 byte  */
  42 #define URTW_TX_LOOPBACK_SHIFT          (17)
  43 #define URTW_TX_LOOPBACK_NONE           (0 << URTW_TX_LOOPBACK_SHIFT)
  44 #define URTW_TX_LOOPBACK_MAC            (1 << URTW_TX_LOOPBACK_SHIFT)
  45 #define URTW_TX_LOOPBACK_BASEBAND       (2 << URTW_TX_LOOPBACK_SHIFT)
  46 #define URTW_TX_LOOPBACK_CONTINUE       (3 << URTW_TX_LOOPBACK_SHIFT)
  47 #define URTW_TX_LOOPBACK_MASK           (0x60000)
  48 #define URTW_TX_DPRETRY_MASK            (0xff00)
  49 #define URTW_TX_RTSRETRY_MASK           (0xff)
  50 #define URTW_TX_DPRETRY_SHIFT           (0)
  51 #define URTW_TX_RTSRETRY_SHIFT          (8)
  52 #define URTW_TX_NOCRC                   (0x10000)
  53 #define URTW_TX_MXDMA_MASK              (0xe00000)
  54 #define URTW_TX_MXDMA_1024              (6 << URTW_TX_MXDMA_SHIFT)
  55 #define URTW_TX_MXDMA_2048              (7 << URTW_TX_MXDMA_SHIFT)
  56 #define URTW_TX_MXDMA_SHIFT             (21)
  57 #define URTW_TX_CWMIN                   (1 << 31)
  58 #define URTW_TX_DISCW                   (1 << 20)
  59 #define URTW_TX_SWPLCPLEN               (1 << 24)
  60 #define URTW_TX_NOICV                   (0x80000)
  61 #define URTW_RX                         0x0044          /* 4 byte  */
  62 #define URTW_RX_9356SEL                 (1 << 6)
  63 #define URTW_RX_FILTER_MASK                     \
  64         (URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \
  65         URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \
  66         URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG | \
  67         (1 << 21) |                                                     \
  68         URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID)
  69 #define URTW_RX_FILTER_ALLMAC           (0x00000001)
  70 #define URTW_RX_FILTER_NICMAC           (0x00000002)
  71 #define URTW_RX_FILTER_MCAST            (0x00000004)
  72 #define URTW_RX_FILTER_BCAST            (0x00000008)
  73 #define URTW_RX_FILTER_CRCERR           (0x00000020)
  74 #define URTW_RX_FILTER_ICVERR           (0x00001000)
  75 #define URTW_RX_FILTER_DATA             (0x00040000)
  76 #define URTW_RX_FILTER_CTL              (0x00080000)
  77 #define URTW_RX_FILTER_MNG              (0x00100000)
  78 #define URTW_RX_FILTER_PWR              (0x00400000)
  79 #define URTW_RX_CHECK_BSSID             (0x00800000)
  80 #define URTW_RX_FIFO_THRESHOLD_MASK     ((1 << 13) | (1 << 14) | (1 << 15))
  81 #define URTW_RX_FIFO_THRESHOLD_SHIFT    (13)
  82 #define URTW_RX_FIFO_THRESHOLD_128      (3)
  83 #define URTW_RX_FIFO_THRESHOLD_256      (4)
  84 #define URTW_RX_FIFO_THRESHOLD_512      (5)
  85 #define URTW_RX_FIFO_THRESHOLD_1024     (6)
  86 #define URTW_RX_FIFO_THRESHOLD_NONE     (7 << URTW_RX_FIFO_THRESHOLD_SHIFT)
  87 #define URTW_RX_AUTORESETPHY            (1 << URTW_RX_AUTORESETPHY_SHIFT)
  88 #define URTW_RX_AUTORESETPHY_SHIFT      (28)
  89 #define URTW_MAX_RX_DMA_MASK            ((1<<8) | (1<<9) | (1<<10))
  90 #define URTW_MAX_RX_DMA_2048            (7 << URTW_MAX_RX_DMA_SHIFT)
  91 #define URTW_MAX_RX_DMA_1024            (6)
  92 #define URTW_MAX_RX_DMA_SHIFT           (10)
  93 #define URTW_RCR_ONLYERLPKT             (1 << 31)
  94 #define URTW_INT_TIMEOUT                0x0048          /* 4 byte  */
  95 #define URTW_EPROM_CMD                  0x0050          /* 1 byte  */
  96 #define URTW_EPROM_CMD_NORMAL           (0x0)
  97 #define URTW_EPROM_CMD_NORMAL_MODE                              \
  98         (URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT)
  99 #define URTW_EPROM_CMD_LOAD             (0x1)
 100 #define URTW_EPROM_CMD_PROGRAM          (0x2)
 101 #define URTW_EPROM_CMD_PROGRAM_MODE                             \
 102         (URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT)
 103 #define URTW_EPROM_CMD_CONFIG           (0x3)
 104 #define URTW_EPROM_CMD_SHIFT            (6)
 105 #define URTW_EPROM_CMD_MASK             ((1 << 7) | (1 << 6))
 106 #define URTW_EPROM_READBIT              (0x1)
 107 #define URTW_EPROM_WRITEBIT             (0x2)
 108 #define URTW_EPROM_CK                   (0x4)
 109 #define URTW_EPROM_CS                   (0x8)
 110 #define URTW_CONFIG2                    0x0053
 111 #define URTW_ANAPARAM                   0x0054          /* 4 byte  */
 112 #define URTW_8225_ANAPARAM_ON           (0xa0000a59)
 113 #define URTW_MSR                        0x0058          /* 1 byte  */
 114 #define URTW_MSR_LINK_MASK              ((1 << 2) | (1 << 3))
 115 #define URTW_MSR_LINK_SHIFT             (2)
 116 #define URTW_MSR_LINK_NONE              (0 << URTW_MSR_LINK_SHIFT)
 117 #define URTW_MSR_LINK_ADHOC             (1 << URTW_MSR_LINK_SHIFT)
 118 #define URTW_MSR_LINK_STA               (2 << URTW_MSR_LINK_SHIFT)
 119 #define URTW_MSR_LINK_HOSTAP            (3 << URTW_MSR_LINK_SHIFT)
 120 #define URTW_CONFIG3                    0x0059          /* 1 byte  */
 121 #define URTW_CONFIG3_ANAPARAM_WRITE     (0x40)
 122 #define URTW_CONFIG3_ANAPARAM_W_SHIFT   (6)
 123 #define URTW_ADDR_MAGIC4                0x005b          /* 1 byte  */
 124 #define URTW_PSR                        0x005e          /* 1 byte  */
 125 #define URTW_ANAPARAM2                  0x0060          /* 4 byte  */
 126 #define URTW_8225_ANAPARAM2_ON          (0x860c7312)
 127 #define URTW_BEACON_INTERVAL            0x0070          /* 2 byte  */
 128 #define URTW_ATIM_WND                   0x0072          /* 2 byte  */
 129 #define URTW_BEACON_INTERVAL_TIME       0x0074          /* 2 byte  */
 130 #define URTW_ATIM_TR_ITV                0x0076          /* 2 byte  */
 131 #define URTW_PHY_MAGIC1                 0x007c          /* 1 byte  */
 132 #define URTW_PHY_MAGIC2                 0x007d          /* 1 byte  */
 133 #define URTW_PHY_MAGIC3                 0x007e          /* 1 byte  */
 134 #define URTW_PHY_MAGIC4                 0x007f          /* 1 byte  */
 135 #define URTW_RF_PINS_OUTPUT             0x0080          /* 2 byte  */
 136 #define URTW_RF_PINS_OUTPUT_MAGIC1      (0x3a0)
 137 #define URTW_BB_HOST_BANG_CLK           (1 << 1)
 138 #define URTW_BB_HOST_BANG_EN            (1 << 2)
 139 #define URTW_BB_HOST_BANG_RW            (1 << 3)
 140 #define URTW_RF_PINS_ENABLE             0x0082          /* 2 byte  */
 141 #define URTW_RF_PINS_SELECT             0x0084          /* 2 byte  */
 142 #define URTW_ADDR_MAGIC1                0x0085          /* broken?  */
 143 #define URTW_RF_PINS_INPUT              0x0086          /* 2 byte  */
 144 #define URTW_RF_PINS_MAGIC1             (0xfff3)
 145 #define URTW_RF_PINS_MAGIC2             (0xfff0)
 146 #define URTW_RF_PINS_MAGIC3             (0x0007)
 147 #define URTW_RF_PINS_MAGIC4             (0xf)
 148 #define URTW_RF_PINS_MAGIC5             (0x0080)
 149 #define URTW_RF_PARA                    0x0088          /* 4 byte  */
 150 #define URTW_RF_TIMING                  0x008c          /* 4 byte  */
 151 #define URTW_GP_ENABLE                  0x0090          /* 1 byte  */
 152 #define URTW_GP_ENABLE_DATA_MAGIC1      (0x1)
 153 #define URTW_GPIO                       0x0091          /* 1 byte  */
 154 #define URTW_GPIO_DATA_MAGIC1           (0x1)
 155 #define URTW_ADDR_MAGIC5                0x0094          /* 4 byte  */
 156 #define URTW_TX_AGC_CTL                 0x009c          /* 1 byte  */
 157 #define URTW_TX_AGC_CTL_PERPACKET_GAIN  (0x1)
 158 #define URTW_TX_AGC_CTL_PERPACKET_ANTSEL        (0x2)
 159 #define URTW_TX_AGC_CTL_FEEDBACK_ANT    (0x4)
 160 #define URTW_TX_GAIN_CCK                0x009d          /* 1 byte  */
 161 #define URTW_TX_GAIN_OFDM               0x009e          /* 1 byte  */
 162 #define URTW_TX_ANTENNA                 0x009f          /* 1 byte  */
 163 #define URTW_WPA_CONFIG                 0x00b0          /* 1 byte  */
 164 #define URTW_SIFS                       0x00b4          /* 1 byte  */
 165 #define URTW_DIFS                       0x00b5          /* 1 byte  */
 166 #define URTW_SLOT                       0x00b6          /* 1 byte  */
 167 #define URTW_CW_CONF                    0x00bc          /* 1 byte  */
 168 #define URTW_CW_CONF_PERPACKET_RETRY    (0x2)
 169 #define URTW_CW_CONF_PERPACKET_CW       (0x1)
 170 #define URTW_CW_VAL                     0x00bd          /* 1 byte  */
 171 #define URTW_RATE_FALLBACK              0x00be          /* 1 byte  */
 172 #define URTW_TALLY_SEL                  0x00fc          /* 1 byte  */
 173 #define URTW_ADDR_MAGIC2                0x00fe          /* 2 byte  */
 174 #define URTW_ADDR_MAGIC3                0x00ff          /* 1 byte  */
 175
 176 /* for 8225  */
 177 #define URTW_8225_ADDR_0_MAGIC          0x0
 178 #define URTW_8225_ADDR_0_DATA_MAGIC1    (0x1b7)
 179 #define URTW_8225_ADDR_0_DATA_MAGIC2    (0x0b7)
 180 #define URTW_8225_ADDR_0_DATA_MAGIC3    (0x127)
 181 #define URTW_8225_ADDR_0_DATA_MAGIC4    (0x027)
 182 #define URTW_8225_ADDR_0_DATA_MAGIC5    (0x22f)
 183 #define URTW_8225_ADDR_0_DATA_MAGIC6    (0x2bf)
 184 #define URTW_8225_ADDR_1_MAGIC          0x1
 185 #define URTW_8225_ADDR_2_MAGIC          0x2
 186 #define URTW_8225_ADDR_2_DATA_MAGIC1    (0xc4d)
 187 #define URTW_8225_ADDR_2_DATA_MAGIC2    (0x44d)
 188 #define URTW_8225_ADDR_3_MAGIC          0x3
 189 #define URTW_8225_ADDR_3_DATA_MAGIC1    (0x2)
 190 #define URTW_8225_ADDR_5_MAGIC          0x5
 191 #define URTW_8225_ADDR_5_DATA_MAGIC1    (0x4)
 192 #define URTW_8225_ADDR_6_MAGIC          0x6
 193 #define URTW_8225_ADDR_6_DATA_MAGIC1    (0xe6)
 194 #define URTW_8225_ADDR_6_DATA_MAGIC2    (0x80)
 195 #define URTW_8225_ADDR_7_MAGIC          0x7
 196 #define URTW_8225_ADDR_8_MAGIC          0x8
 197 #define URTW_8225_ADDR_8_DATA_MAGIC1    (0x588)
 198 #define URTW_8225_ADDR_9_MAGIC          0x9
 199 #define URTW_8225_ADDR_9_DATA_MAGIC1    (0x700)
 200 #define URTW_8225_ADDR_C_MAGIC          0xc
 201 #define URTW_8225_ADDR_C_DATA_MAGIC1    (0x850)
 202 #define URTW_8225_ADDR_C_DATA_MAGIC2    (0x050)
 203
 204 /* for EEPROM  */
 205 #define URTW_EPROM_TXPW_BASE            0x05
 206 #define URTW_EPROM_RFCHIPID             0x06
 207 #define URTW_EPROM_RFCHIPID_RTL8225U    (5)
 208 #define URTW_EPROM_MACADDR              0x07
 209 #define URTW_EPROM_TXPW0                0x16
 210 #define URTW_EPROM_TXPW2                0x1b
 211 #define URTW_EPROM_TXPW1                0x3d
 212 #define URTW_EPROM_SWREV                0x3f
 213 #define URTW_EPROM_CID_MASK             (0xff)
 214 #define URTW_EPROM_CID_RSVD0            (0x00)
 215 #define URTW_EPROM_CID_RSVD1            (0xff)
 216 #define URTW_EPROM_CID_ALPHA0           (0x01)
 217 #define URTW_EPROM_CID_SERCOMM_PS       (0x02)
 218 #define URTW_EPROM_CID_HW_LED           (0x03)
 219
 220 /* LED  */
 221 #define URTW_CID_DEFAULT                0
 222 #define URTW_CID_8187_ALPHA0            1
 223 #define URTW_CID_8187_SERCOMM_PS        2
 224 #define URTW_CID_8187_HW_LED            3
 225 #define URTW_SW_LED_MODE0               0
 226 #define URTW_SW_LED_MODE1               1
 227 #define URTW_SW_LED_MODE2               2
 228 #define URTW_SW_LED_MODE3               3
 229 #define URTW_HW_LED                     4
 230 #define URTW_LED_CTL_POWER_ON           0
 231 #define URTW_LED_CTL_LINK               2
 232 #define URTW_LED_CTL_TX                 4
 233 #define URTW_LED_PIN_GPIO0              0
 234 #define URTW_LED_PIN_LED0               1
 235 #define URTW_LED_PIN_LED1               2
 236 #define URTW_LED_UNKNOWN                0
 237 #define URTW_LED_ON                     1
 238 #define URTW_LED_OFF                    2
 239 #define URTW_LED_BLINK_NORMAL           3
 240 #define URTW_LED_BLINK_SLOWLY           4
 241 #define URTW_LED_POWER_ON_BLINK         5
 242 #define URTW_LED_SCAN_BLINK             6
 243 #define URTW_LED_NO_LINK_BLINK          7
 244 #define URTW_LED_BLINK_CM3              8
 245
 246 /* for extra area  */
 247 #define URTW_EPROM_DISABLE              0
 248 #define URTW_EPROM_ENABLE               1
 249 #define URTW_EPROM_DELAY                10
 250 #define URTW_8187_GETREGS_REQ           5
 251 #define URTW_8187_SETREGS_REQ           5
 252 #define URTW_8225_RF_MAX_SENS           6
 253 #define URTW_8225_RF_DEF_SENS           4
 254 #define URTW_DEFAULT_RTS_RETRY          7
 255 #define URTW_DEFAULT_TX_RETRY           7
 256 #define URTW_DEFAULT_RTS_THRESHOLD      2342U