1 /* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
5 * Copyright (c) 2007 Oleksandr Tymoshenko.
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 * 3. The names of the authors may not be used to endorse or promote
18 * products derived from this software without specific prior
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
23 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
24 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
28 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
30 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
42 #include <machine/bus.h>
44 #include <dev/uart/uart.h>
45 #include <dev/uart/uart_cpu.h>
46 #include <dev/uart/uart_bus.h>
48 #include <mips/adm5120/uart_dev_adm5120.h>
53 * Low-level UART interface.
55 static int adm5120_uart_probe(struct uart_bas *bas);
56 static void adm5120_uart_init(struct uart_bas *bas, int, int, int, int);
57 static void adm5120_uart_term(struct uart_bas *bas);
58 static void adm5120_uart_putc(struct uart_bas *bas, int);
59 static int adm5120_uart_rxready(struct uart_bas *bas);
60 static int adm5120_uart_getc(struct uart_bas *bas, struct mtx *);
62 static struct uart_ops uart_adm5120_uart_ops = {
63 .probe = adm5120_uart_probe,
64 .init = adm5120_uart_init,
65 .term = adm5120_uart_term,
66 .putc = adm5120_uart_putc,
67 .rxready = adm5120_uart_rxready,
68 .getc = adm5120_uart_getc,
72 adm5120_uart_probe(struct uart_bas *bas)
79 adm5120_uart_init(struct uart_bas *bas, int baudrate, int databits,
80 int stopbits, int parity)
83 /* TODO: Set parameters for uart, meanwhile stick with 115200N1 */
87 adm5120_uart_term(struct uart_bas *bas)
93 adm5120_uart_putc(struct uart_bas *bas, int c)
97 while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)
99 uart_setreg(bas, UART_DR_REG, c);
100 while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY)
106 adm5120_uart_rxready(struct uart_bas *bas)
108 if (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY)
115 adm5120_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
121 while (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) {
127 c = uart_getreg(bas, UART_DR_REG);
135 * High-level UART interface.
137 struct adm5120_uart_softc {
138 struct uart_softc base;
141 static int adm5120_uart_bus_attach(struct uart_softc *);
142 static int adm5120_uart_bus_detach(struct uart_softc *);
143 static int adm5120_uart_bus_flush(struct uart_softc *, int);
144 static int adm5120_uart_bus_getsig(struct uart_softc *);
145 static int adm5120_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
146 static int adm5120_uart_bus_ipend(struct uart_softc *);
147 static int adm5120_uart_bus_param(struct uart_softc *, int, int, int, int);
148 static int adm5120_uart_bus_probe(struct uart_softc *);
149 static int adm5120_uart_bus_receive(struct uart_softc *);
150 static int adm5120_uart_bus_setsig(struct uart_softc *, int);
151 static int adm5120_uart_bus_transmit(struct uart_softc *);
153 static kobj_method_t adm5120_uart_methods[] = {
154 KOBJMETHOD(uart_attach, adm5120_uart_bus_attach),
155 KOBJMETHOD(uart_detach, adm5120_uart_bus_detach),
156 KOBJMETHOD(uart_flush, adm5120_uart_bus_flush),
157 KOBJMETHOD(uart_getsig, adm5120_uart_bus_getsig),
158 KOBJMETHOD(uart_ioctl, adm5120_uart_bus_ioctl),
159 KOBJMETHOD(uart_ipend, adm5120_uart_bus_ipend),
160 KOBJMETHOD(uart_param, adm5120_uart_bus_param),
161 KOBJMETHOD(uart_probe, adm5120_uart_bus_probe),
162 KOBJMETHOD(uart_receive, adm5120_uart_bus_receive),
163 KOBJMETHOD(uart_setsig, adm5120_uart_bus_setsig),
164 KOBJMETHOD(uart_transmit, adm5120_uart_bus_transmit),
168 struct uart_class uart_adm5120_uart_class = {
170 adm5120_uart_methods,
171 sizeof(struct adm5120_uart_softc),
172 .uc_ops = &uart_adm5120_uart_ops,
173 .uc_range = 1, /* use hinted range */
177 #define SIGCHG(c, i, s, d) \
179 i |= (i & s) ? s : s | d; \
181 i = (i & s) ? (i & ~s) | d : i; \
185 * Disable TX interrupt. uart should be locked
188 adm5120_uart_disable_txintr(struct uart_softc *sc)
192 cr = uart_getreg(&sc->sc_bas, UART_CR_REG);
193 cr &= ~UART_CR_TX_INT_EN;
194 uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
198 * Enable TX interrupt. uart should be locked
201 adm5120_uart_enable_txintr(struct uart_softc *sc)
205 cr = uart_getreg(&sc->sc_bas, UART_CR_REG);
206 cr |= UART_CR_TX_INT_EN;
207 uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
211 adm5120_uart_bus_attach(struct uart_softc *sc)
213 struct uart_bas *bas;
214 struct uart_devinfo *di;
217 if (sc->sc_sysdev != NULL) {
219 /* TODO: set parameters from di */
221 /* TODO: set parameters 115200, 8N1 */
224 sc->sc_rxfifosz = 16;
225 sc->sc_txfifosz = 16;
227 (void)adm5120_uart_bus_getsig(sc);
231 uart_setreg(bas, UART_LCR_H_REG,
232 uart_getreg(bas, UART_LCR_H_REG) | UART_LCR_H_FEN);
234 /* Enable interrupts */
235 uart_setreg(bas, UART_CR_REG,
236 UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN|
237 UART_CR_MODEM_STATUS_INT_EN);
243 adm5120_uart_bus_detach(struct uart_softc *sc)
250 adm5120_uart_bus_flush(struct uart_softc *sc, int what)
257 adm5120_uart_bus_getsig(struct uart_softc *sc)
259 uint32_t new, old, sig;
265 uart_lock(sc->sc_hwmtx);
266 bes = uart_getreg(&sc->sc_bas, UART_FR_REG);
267 uart_unlock(sc->sc_hwmtx);
268 SIGCHG(bes & UART_FR_CTS, sig, SER_CTS, SER_DCTS);
269 SIGCHG(bes & UART_FR_DCD, sig, SER_DCD, SER_DDCD);
270 SIGCHG(bes & UART_FR_DSR, sig, SER_DSR, SER_DDSR);
271 new = sig & ~SER_MASK_DELTA;
272 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
278 adm5120_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
280 struct uart_bas *bas;
281 int baudrate, divisor, error;
285 uart_lock(sc->sc_hwmtx);
287 case UART_IOCTL_BREAK:
288 /* TODO: Send BREAK */
290 case UART_IOCTL_BAUD:
291 divisor = uart_getreg(bas, UART_LCR_M_REG);
292 divisor = (divisor << 8) |
293 uart_getreg(bas, UART_LCR_L_REG);
294 baudrate = bas->rclk / 2 / (divisor + 2);
295 *(int*)data = baudrate;
301 uart_unlock(sc->sc_hwmtx);
306 adm5120_uart_bus_ipend(struct uart_softc *sc)
308 struct uart_bas *bas;
315 uart_lock(sc->sc_hwmtx);
316 ir = uart_getreg(&sc->sc_bas, UART_IR_REG);
317 fr = uart_getreg(&sc->sc_bas, UART_FR_REG);
318 rsr = uart_getreg(&sc->sc_bas, UART_RSR_REG);
320 if (ir & UART_IR_RX_INT)
321 ipend |= SER_INT_RXREADY;
323 if (ir & UART_IR_RX_TIMEOUT_INT)
324 ipend |= SER_INT_RXREADY;
326 if (ir & UART_IR_MODEM_STATUS_INT)
327 ipend |= SER_INT_SIGCHG;
329 if (rsr & UART_RSR_BE)
330 ipend |= SER_INT_BREAK;
332 if (rsr & UART_RSR_OE)
333 ipend |= SER_INT_OVERRUN;
335 if (fr & UART_FR_TX_FIFO_EMPTY) {
336 if (ir & UART_IR_TX_INT) {
337 adm5120_uart_disable_txintr(sc);
338 ipend |= SER_INT_TXIDLE;
343 uart_setreg(bas, UART_IR_REG, ir | UART_IR_UICR);
345 uart_unlock(sc->sc_hwmtx);
351 adm5120_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
352 int stopbits, int parity)
355 /* TODO: Set parameters for uart, meanwhile stick with 115200 8N1 */
360 adm5120_uart_bus_probe(struct uart_softc *sc)
366 error = adm5120_uart_probe(&sc->sc_bas);
370 ch = sc->sc_bas.chan + 'A';
372 snprintf(buf, sizeof(buf), "adm5120_uart, channel %c", ch);
373 device_set_desc_copy(sc->sc_dev, buf);
379 adm5120_uart_bus_receive(struct uart_softc *sc)
381 struct uart_bas *bas;
386 uart_lock(sc->sc_hwmtx);
387 fr = uart_getreg(bas, UART_FR_REG);
388 while (!(fr & UART_FR_RX_FIFO_EMPTY)) {
389 if (uart_rx_full(sc)) {
390 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
394 rsr = uart_getreg(bas, UART_RSR_REG);
395 if (rsr & UART_RSR_FE)
396 xc |= UART_STAT_FRAMERR;
397 if (rsr & UART_RSR_PE)
398 xc |= UART_STAT_PARERR;
399 if (rsr & UART_RSR_OE)
400 xc |= UART_STAT_OVERRUN;
401 xc |= uart_getreg(bas, UART_DR_REG);
404 if (rsr & (UART_RSR_FE | UART_RSR_PE | UART_RSR_OE)) {
405 uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
408 fr = uart_getreg(bas, UART_FR_REG);
411 /* Discard everything left in the Rx FIFO. */
412 while (!(fr & UART_FR_RX_FIFO_EMPTY)) {
413 ( void)uart_getreg(bas, UART_DR_REG);
415 rsr = uart_getreg(bas, UART_RSR_REG);
416 if (rsr & (UART_RSR_FE | UART_RSR_PE | UART_RSR_OE)) {
417 uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
420 fr = uart_getreg(bas, UART_FR_REG);
422 uart_unlock(sc->sc_hwmtx);
427 adm5120_uart_bus_setsig(struct uart_softc *sc, int sig)
430 /* TODO: implement (?) */
435 adm5120_uart_bus_transmit(struct uart_softc *sc)
437 struct uart_bas *bas;
440 uart_lock(sc->sc_hwmtx);
442 for (int i = 0; i < sc->sc_txdatasz; i++) {
443 if (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)
445 uart_setreg(bas, UART_DR_REG, sc->sc_txbuf[i]);
448 /* Enable TX interrupt */
449 adm5120_uart_enable_txintr(sc);
450 uart_unlock(sc->sc_hwmtx);