2 * Copyright (c) 2016 Hiroki Mori
3 * Copyright (c) 2010 Adrian Chadd
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/socket.h>
37 #include <sys/systm.h>
41 #include <sys/reboot.h>
44 #include <vm/vm_page.h>
46 #include <net/ethernet.h>
48 #include <machine/clock.h>
49 #include <machine/cpu.h>
50 #include <machine/cpuregs.h>
51 #include <machine/hwfunc.h>
52 #include <machine/md_var.h>
53 #include <machine/trap.h>
54 #include <machine/vmparam.h>
56 #include <mips/atheros/ar531x/ar5312reg.h>
57 #include <mips/atheros/ar531x/ar5315reg.h>
58 #include <mips/atheros/ar531x/ar5315_cpudef.h>
59 #include <mips/atheros/ar531x/ar5315_setup.h>
62 ar5312_chip_detect_mem_size(void)
65 uint32_t memcfg, bank0, bank1;
68 * Determine the memory size as established by system
71 * NB: we allow compile time override
73 memcfg = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
74 bank0 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK0);
75 bank1 = __SHIFTOUT(memcfg, AR5312_MEM_CFG1_BANK1);
77 memsize = (bank0 ? (1 << (bank0 + 1)) : 0) +
78 (bank1 ? (1 << (bank1 + 1)) : 0);
85 ar5312_chip_detect_sys_frequency(void)
91 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL);
92 if(ar531x_soc == AR531X_SOC_AR5313) {
93 predivisor = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_PREDIVIDE);
94 multiplier = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_MULTIPLIER);
96 predivisor = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_PREDIVIDE);
97 multiplier = __SHIFTOUT(clockctl, AR5312_CLOCKCTL_MULTIPLIER);
100 const uint32_t divisor = (0x5421 >> (predivisor * 4)) & 15;
102 const uint32_t cpufreq = (40000000 / divisor) * multiplier;
104 u_ar531x_cpu_freq = cpufreq;
105 u_ar531x_ahb_freq = cpufreq / 4;
106 u_ar531x_ddr_freq = 0;
110 * This does not lock the CPU whilst doing the work!
113 ar5312_chip_device_reset(void)
115 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL,
116 AR5312_RESET_SYSTEM);
120 ar5312_chip_device_start(void)
123 uint32_t bank0, bank1;
124 uint32_t size0, size1;
126 cfg0 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG0);
127 cfg1 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1);
129 bank0 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK0);
130 bank1 = __SHIFTOUT(cfg1, AR5312_MEM_CFG1_BANK1);
132 size0 = bank0 ? (1 << (bank0 + 1)) : 0;
133 size1 = bank1 ? (1 << (bank1 + 1)) : 0;
138 printf("SDRMCTL %x %x %x %x\n", cfg0, cfg1, size0, size1);
140 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR);
141 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE);
142 // ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_WDOG_CTL, 0);
143 ATH_WRITE_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_ENABLE, 0);
145 ATH_WRITE_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE,
146 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) |
147 AR5312_ENABLE_ENET0 | AR5312_ENABLE_ENET1);
152 ar5312_chip_device_stopped(uint32_t mask)
156 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL);
157 return ((reg & mask) == mask);
161 ar5312_chip_set_mii_speed(uint32_t unit, uint32_t speed)
165 /* Speed is either 10, 100 or 1000 */
167 ar5312_chip_set_pll_ge(int unit, int speed)
172 ar5312_chip_ddr_flush_ge(int unit)
177 ar5312_chip_soc_init(void)
180 u_ar531x_uart_addr = MIPS_PHYS_TO_KSEG1(AR5312_UART0_BASE);
182 u_ar531x_gpio_di = AR5312_GPIO_DI;
183 u_ar531x_gpio_do = AR5312_GPIO_DO;
184 u_ar531x_gpio_cr = AR5312_GPIO_CR;
185 u_ar531x_gpio_pins = AR5312_GPIO_PINS;
187 u_ar531x_wdog_ctl = AR5312_SYSREG_WDOG_CTL;
188 u_ar531x_wdog_timer = AR5312_SYSREG_WDOG_TIMER;
193 ar5312_chip_get_eth_pll(unsigned int mac, int speed)
198 struct ar5315_cpu_def ar5312_chip_def = {
199 &ar5312_chip_detect_mem_size,
200 &ar5312_chip_detect_sys_frequency,
201 &ar5312_chip_device_reset,
202 &ar5312_chip_device_start,
203 &ar5312_chip_device_stopped,
204 &ar5312_chip_set_pll_ge,
205 &ar5312_chip_set_mii_speed,
206 &ar5312_chip_ddr_flush_ge,
207 &ar5312_chip_get_eth_pll,
208 &ar5312_chip_soc_init,