1 /* $Id: ar5315reg.h,v 1.3 2011/07/07 05:06:44 matt Exp $ */
3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center.
4 * Copyright (c) 2006 Garrett D'Amore.
7 * This code was written by Garrett D'Amore for the Champaign-Urbana
8 * Community Wireless Network Project.
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer in the documentation and/or other materials provided
18 * with the distribution.
19 * 3. All advertising materials mentioning features or use of this
20 * software must display the following acknowledgements:
21 * This product includes software developed by the Urbana-Champaign
22 * Independent Media Center.
23 * This product includes software developed by Garrett D'Amore.
24 * 4. Urbana-Champaign Independent Media Center's name and Garrett
25 * D'Amore's name may not be used to endorse or promote products
26 * derived from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #ifndef _MIPS_ATHEROS_AR5315REG_H_
46 #define _MIPS_ATHEROS_AR5315REG_H_
48 #define AR5315_MEM0_BASE 0x00000000 /* sdram */
49 #define AR5315_MEM1_BASE 0x08000000 /* spi flash */
50 #define AR5315_WLAN_BASE 0x10000000
51 #define AR5315_PCI_BASE 0x10100000
52 #define AR5315_SDRAMCTL_BASE 0x10300000
53 #define AR5315_LOCAL_BASE 0x10400000 /* local bus */
54 #define AR5315_ENET_BASE 0x10500000
55 #define AR5315_SYSREG_BASE 0x11000000
56 #define AR5315_UART_BASE 0x11100000
57 #define AR5315_SPI_BASE 0x11300000 /* spi flash */
58 #define AR5315_BOOTROM_BASE 0x1FC00000 /* boot rom */
59 #define AR5315_CONFIG_BASE 0x087D0000 /* flash start */
60 #define AR5315_CONFIG_END 0x087FF000 /* flash end */
61 #define AR5315_RADIO_END 0x1FFFF000 /* radio end */
64 #define AR5315_PCIEXT_BASE 0x80000000 /* pci external */
65 #define AR5315_RAM2_BASE 0xc0000000
66 #define AR5315_RAM3_BASE 0xe0000000
70 * SYSREG registers -- offset relative to AR531X_SYSREG_BASE
72 #define AR5315_SYSREG_COLDRESET 0x0000
73 #define AR5315_SYSREG_RESETCTL 0x0004
74 #define AR5315_SYSREG_AHB_ARB_CTL 0x0008
75 #define AR5315_SYSREG_ENDIAN 0x000c
76 #define AR5315_SYSREG_NMI_CTL 0x0010
77 #define AR5315_SYSREG_SREV 0x0014
78 #define AR5315_SYSREG_IF_CTL 0x0018
79 #define AR5315_SYSREG_MISC_INTSTAT 0x0020
80 #define AR5315_SYSREG_MISC_INTMASK 0x0024
81 #define AR5315_SYSREG_GISR 0x0028
82 #define AR5315_SYSREG_TIMER 0x0030
83 #define AR5315_SYSREG_RELOAD 0x0034
84 #define AR5315_SYSREG_WDOG_TIMER 0x0038
85 #define AR5315_SYSREG_WDOG_CTL 0x003c
86 #define AR5315_SYSREG_PERFCNT0 0x0048
87 #define AR5315_SYSREG_PERFCNT1 0x004c
88 #define AR5315_SYSREG_AHB_ERR0 0x0050
89 #define AR5315_SYSREG_AHB_ERR1 0x0054
90 #define AR5315_SYSREG_AHB_ERR2 0x0058
91 #define AR5315_SYSREG_AHB_ERR3 0x005c
92 #define AR5315_SYSREG_AHB_ERR4 0x0060
93 #define AR5315_SYSREG_PLLC_CTL 0x0064
94 #define AR5315_SYSREG_PLLV_CTL 0x0068
95 #define AR5315_SYSREG_CPUCLK 0x006c
96 #define AR5315_SYSREG_AMBACLK 0x0070
97 #define AR5315_SYSREG_SYNCCLK 0x0074
98 #define AR5315_SYSREG_DSL_SLEEP_CTL 0x0080
99 #define AR5315_SYSREG_DSL_SLEEP_DUR 0x0084
100 #define AR5315_SYSREG_GPIO_DI 0x0088
101 #define AR5315_SYSREG_GPIO_DO 0x0090
102 #define AR5315_SYSREG_GPIO_CR 0x0098
103 #define AR5315_SYSREG_GPIO_INT 0x00a0
105 #define AR5315_GPIO_PINS 23
107 /* Cold resets (AR5315_SYSREG_COLDRESET) */
108 #define AR5315_COLD_AHB 0x00000001
109 #define AR5315_COLD_APB 0x00000002
110 #define AR5315_COLD_CPU 0x00000004
111 #define AR5315_COLD_CPU_WARM 0x00000008
113 /* Resets (AR5315_SYSREG_RESETCTL) */
114 #define AR5315_RESET_WARM_WLAN0_MAC 0x00000001
115 #define AR5315_RESET_WARM_WLAN0_BB 0x00000002
116 #define AR5315_RESET_MPEGTS 0x00000004 /* MPEG-TS */
117 #define AR5315_RESET_PCIDMA 0x00000008 /* PCI dma */
118 #define AR5315_RESET_MEMCTL 0x00000010
119 #define AR5315_RESET_LOCAL 0x00000020 /* local bus */
120 #define AR5315_RESET_I2C 0x00000040 /* i2c */
121 #define AR5315_RESET_SPI 0x00000080 /* SPI */
122 #define AR5315_RESET_UART 0x00000100
123 #define AR5315_RESET_IR 0x00000200 /* infrared */
124 #define AR5315_RESET_PHY0 0x00000400 /* enet phy */
125 #define AR5315_RESET_ENET0 0x00000800
127 /* Watchdog control (AR5315_SYSREG_WDOG_CTL) */
128 #define AR5315_WDOG_CTL_IGNORE 0x0000
129 #define AR5315_WDOG_CTL_NMI 0x0001
130 #define AR5315_WDOG_CTL_RESET 0x0002
132 /* AR5315 AHB arbitration control (AR5315_SYSREG_AHB_ARB_CTL) */
133 #define AR5315_ARB_CPU 0x00001
134 #define AR5315_ARB_WLAN 0x00002
135 #define AR5315_ARB_MPEGTS 0x00004
136 #define AR5315_ARB_LOCAL 0x00008
137 #define AR5315_ARB_PCI 0x00010
138 #define AR5315_ARB_ENET 0x00020
139 #define AR5315_ARB_RETRY 0x00100
141 /* AR5315 endianness control (AR5315_SYSREG_ENDIAN) */
142 #define AR5315_ENDIAN_AHB 0x00001
143 #define AR5315_ENDIAN_WLAN 0x00002
144 #define AR5315_ENDIAN_MPEGTS 0x00004
145 #define AR5315_ENDIAN_PCI 0x00008
146 #define AR5315_ENDIAN_MEMCTL 0x00010
147 #define AR5315_ENDIAN_LOCAL 0x00020
148 #define AR5315_ENDIAN_ENET 0x00040
149 #define AR5315_ENDIAN_MERGE 0x00200
150 #define AR5315_ENDIAN_CPU 0x00400
151 #define AR5315_ENDIAN_PCIAHB 0x00800
152 #define AR5315_ENDIAN_PCIAHB_BRIDGE 0x01000
153 #define AR5315_ENDIAN_SPI 0x08000
154 #define AR5315_ENDIAN_CPU_DRAM 0x10000
155 #define AR5315_ENDIAN_CPU_PCI 0x20000
156 #define AR5315_ENDIAN_CPU_MMR 0x40000
158 /* AR5315 AHB error bits */
159 #define AR5315_AHB_ERROR_DET 1 /* error detected */
160 #define AR5315_AHB_ERROR_OVR 2 /* AHB overflow */
161 #define AR5315_AHB_ERROR_WDT 4 /* wdt (not hresp) */
164 #define AR5315_PLLC_REF_DIV(reg) ((reg) & 0x3)
165 #define AR5315_PLLC_FB_DIV(reg) (((reg) & 0x7c) >> 2)
166 #define AR5315_PLLC_DIV_2(reg) (((reg) & 0x80) >> 7)
167 #define AR5315_PLLC_CLKC(reg) (((reg) & 0x1c000) >> 14)
168 #define AR5315_PLLC_CLKM(reg) (((reg) & 0x700000) >> 20)
170 #define AR5315_CLOCKCTL_SELECT(reg) ((reg) & 0x3)
171 #define AR5315_CLOCKCTL_DIV(reg) (((reg) & 0xc) >> 2)
174 * SDRAMCTL registers -- offset relative to SDRAMCTL
176 #define AR5315_SDRAMCTL_MEM_CFG 0x0000
177 #define AR5315_MEM_CFG_DATA_WIDTH __BITS(13,14)
178 #define AR5315_MEM_CFG_COL_WIDTH __BITS(9,12)
179 #define AR5315_MEM_CFG_ROW_WIDTH __BITS(5,8)
181 /* memory config 1 bits */
182 #define AR531X_MEM_CFG1_BANK0 __BITS(8,10)
183 #define AR531X_MEM_CFG1_BANK1 __BITS(12,14)
186 * PCI configuration stuff. I don't pretend to fully understand these
187 * registers, they seem to be magic numbers in the Linux code.
189 #define AR5315_PCI_MAC_RC 0x4000
190 #define AR5315_PCI_MAC_SCR 0x4004
191 #define AR5315_PCI_MAC_INTPEND 0x4008
192 #define AR5315_PCI_MAC_SFR 0x400c
193 #define AR5315_PCI_MAC_PCICFG 0x4010
194 #define AR5315_PCI_MAC_SREV 0x4020
196 #define PCI_MAC_RC_MAC 0x1
197 #define PCI_MAC_RC_BB 0x2
199 #define PCI_MAC_SCR_SLM_MASK 0x00030000
200 #define PCI_MAC_SCR_SLM_FWAKE 0x00000000
201 #define PCI_MAC_SCR_SLM_FSLEEP 0x00010000
202 #define PCI_MAC_SCR_SLM_NORMAL 0x00020000
204 #define PCI_MAC_PCICFG_SPWR_DN 0x00010000
207 #define AR5315_CPU_IRQ_MISC 0
208 #define AR5315_CPU_IRQ_WLAN 1
209 #define AR5315_CPU_IRQ_ENET 2
211 #define AR5315_MISC_IRQ_UART 0
212 #define AR5315_MISC_IRQ_I2C 1
213 #define AR5315_MISC_IRQ_SPI 2
214 #define AR5315_MISC_IRQ_AHBE 3
215 #define AR5315_MISC_IRQ_AHPE 4
216 #define AR5315_MISC_IRQ_TIMER 5
217 #define AR5315_MISC_IRQ_GPIO 6
218 #define AR5315_MISC_IRQ_WDOG 7
219 #define AR5315_MISC_IRQ_IR 8
221 #define AR5315_APB_BASE AR5315_SYSREG_BASE
222 #define AR5315_APB_SIZE 0x06000000
224 #define ATH_READ_REG(reg) \
225 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
227 #define ATH_WRITE_REG(reg, val) \
228 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
230 /* Helpers from NetBSD cdefs.h */
231 /* __BIT(n): nth bit, where __BIT(0) == 0x1. */
233 (((__n) >= NBBY * sizeof(uintmax_t)) ? 0 : ((uintmax_t)1 << (__n)))
235 /* __BITS(m, n): bits m through n, m < n. */
236 #define __BITS(__m, __n) \
237 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
239 /* find least significant bit that is set */
240 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
242 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
243 #define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask))
244 #endif /* _MIPS_ATHEROS_AR531XREG_H_ */