2 * Copyright (c) 2010 Adrian Chadd
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar71xx_chip.h>
56 #include <mips/atheros/ar71xx_cpudef.h>
58 /* XXX these should replace the current definitions in ar71xxreg.h */
59 /* XXX perhaps an ar71xx_chip.h header file? */
60 #define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
61 #define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04
62 #define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10
63 #define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
65 #define AR71XX_PLL_DIV_SHIFT 3
66 #define AR71XX_PLL_DIV_MASK 0x1f
67 #define AR71XX_CPU_DIV_SHIFT 16
68 #define AR71XX_CPU_DIV_MASK 0x3
69 #define AR71XX_DDR_DIV_SHIFT 18
70 #define AR71XX_DDR_DIV_MASK 0x3
71 #define AR71XX_AHB_DIV_SHIFT 20
72 #define AR71XX_AHB_DIV_MASK 0x7
74 /* XXX these shouldn't be in here - this file is a per-chip file */
75 /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
76 uint32_t u_ar71xx_cpu_freq;
77 uint32_t u_ar71xx_ahb_freq;
78 uint32_t u_ar71xx_ddr_freq;
79 uint32_t u_ar71xx_uart_freq;
80 uint32_t u_ar71xx_wdt_freq;
81 uint32_t u_ar71xx_refclk;
82 uint32_t u_ar71xx_mdio_freq;
85 ar71xx_chip_detect_mem_size(void)
90 ar71xx_chip_detect_sys_frequency(void)
96 u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ;
98 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
100 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
101 freq = div * AR71XX_BASE_FREQ;
103 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
104 u_ar71xx_cpu_freq = freq / div;
106 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
107 u_ar71xx_ddr_freq = freq / div;
109 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
110 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
111 u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
112 u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
116 * This does not lock the CPU whilst doing the work!
119 ar71xx_chip_device_stop(uint32_t mask)
123 reg = ATH_READ_REG(AR71XX_RST_RESET);
124 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
128 ar71xx_chip_device_start(uint32_t mask)
132 reg = ATH_READ_REG(AR71XX_RST_RESET);
133 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
137 ar71xx_chip_device_stopped(uint32_t mask)
141 reg = ATH_READ_REG(AR71XX_RST_RESET);
142 return ((reg & mask) == mask);
146 ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
148 uint32_t val, reg, ctrl;
152 reg = AR71XX_MII0_CTRL;
155 reg = AR71XX_MII1_CTRL;
158 printf("%s: invalid MII unit set for arge unit: %d\n",
165 ctrl = MII_CTRL_SPEED_10;
168 ctrl = MII_CTRL_SPEED_100;
171 ctrl = MII_CTRL_SPEED_1000;
174 printf("%s: invalid MII speed (%d) set for arge unit: %d\n",
175 __func__, speed, unit);
179 val = ATH_READ_REG(reg);
180 val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
181 val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
182 ATH_WRITE_REG(reg, val);
186 ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
188 uint32_t val, reg, mii_if;
192 reg = AR71XX_MII0_CTRL;
193 if (mii_mode == AR71XX_MII_MODE_GMII)
194 mii_if = MII0_CTRL_IF_GMII;
195 else if (mii_mode == AR71XX_MII_MODE_MII)
196 mii_if = MII0_CTRL_IF_MII;
197 else if (mii_mode == AR71XX_MII_MODE_RGMII)
198 mii_if = MII0_CTRL_IF_RGMII;
199 else if (mii_mode == AR71XX_MII_MODE_RMII)
200 mii_if = MII0_CTRL_IF_RMII;
202 printf("%s: invalid MII mode (%d) for unit %d\n",
203 __func__, mii_mode, unit);
208 reg = AR71XX_MII1_CTRL;
209 if (mii_mode == AR71XX_MII_MODE_RGMII)
210 mii_if = MII1_CTRL_IF_RGMII;
211 else if (mii_mode == AR71XX_MII_MODE_RMII)
212 mii_if = MII1_CTRL_IF_RMII;
214 printf("%s: invalid MII mode (%d) for unit %d\n",
215 __func__, mii_mode, unit);
220 printf("%s: invalid MII unit set for arge unit: %d\n",
225 val = ATH_READ_REG(reg);
226 val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT);
227 val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT;
228 ATH_WRITE_REG(reg, val);
231 /* Speed is either 10, 100 or 1000 */
233 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
238 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
239 AR71XX_PLL_ETH_INT0_CLK, pll,
240 AR71XX_PLL_ETH0_SHIFT);
243 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
244 AR71XX_PLL_ETH_INT1_CLK, pll,
245 AR71XX_PLL_ETH1_SHIFT);
248 printf("%s: invalid PLL set for arge unit: %d\n",
255 ar71xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
259 case AR71XX_CPU_DDR_FLUSH_GE0:
260 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
262 case AR71XX_CPU_DDR_FLUSH_GE1:
263 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
265 case AR71XX_CPU_DDR_FLUSH_USB:
266 ar71xx_ddr_flush(AR71XX_WB_FLUSH_USB);
268 case AR71XX_CPU_DDR_FLUSH_PCIE:
269 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
272 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
278 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
284 pll = PLL_ETH_INT_CLK_10;
287 pll = PLL_ETH_INT_CLK_100;
290 pll = PLL_ETH_INT_CLK_1000;
293 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
301 ar71xx_chip_init_usb_peripheral(void)
304 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
305 RST_RESET_USB_HOST | RST_RESET_USB_PHY);
308 ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
309 RST_RESET_USB_HOST | RST_RESET_USB_PHY);
312 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
313 USB_CTRL_CONFIG_OHCI_DES_SWAP |
314 USB_CTRL_CONFIG_OHCI_BUF_SWAP |
315 USB_CTRL_CONFIG_EHCI_DES_SWAP |
316 USB_CTRL_CONFIG_EHCI_BUF_SWAP);
318 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
319 (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
320 (3 << USB_CTRL_FLADJ_A5_SHIFT));
325 struct ar71xx_cpu_def ar71xx_chip_def = {
326 &ar71xx_chip_detect_mem_size,
327 &ar71xx_chip_detect_sys_frequency,
328 &ar71xx_chip_device_stop,
329 &ar71xx_chip_device_start,
330 &ar71xx_chip_device_stopped,
331 &ar71xx_chip_set_pll_ge,
332 &ar71xx_chip_set_mii_speed,
333 &ar71xx_chip_set_mii_if,
334 &ar71xx_chip_get_eth_pll,
335 &ar71xx_chip_ddr_flush,
336 &ar71xx_chip_init_usb_peripheral,