2 * Copyright (c) 2010 Adrian Chadd
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar71xx_chip.h>
56 #include <mips/atheros/ar71xx_cpudef.h>
58 #include <mips/sentry5/s5reg.h>
60 /* XXX these should replace the current definitions in ar71xxreg.h */
61 /* XXX perhaps an ar71xx_chip.h header file? */
62 #define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
63 #define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04
64 #define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10
65 #define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
67 #define AR71XX_PLL_DIV_SHIFT 3
68 #define AR71XX_PLL_DIV_MASK 0x1f
69 #define AR71XX_CPU_DIV_SHIFT 16
70 #define AR71XX_CPU_DIV_MASK 0x3
71 #define AR71XX_DDR_DIV_SHIFT 18
72 #define AR71XX_DDR_DIV_MASK 0x3
73 #define AR71XX_AHB_DIV_SHIFT 20
74 #define AR71XX_AHB_DIV_MASK 0x7
76 /* XXX these shouldn't be in here - this file is a per-chip file */
77 /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
78 uint32_t u_ar71xx_cpu_freq;
79 uint32_t u_ar71xx_ahb_freq;
80 uint32_t u_ar71xx_ddr_freq;
81 uint32_t u_ar71xx_uart_freq;
82 uint32_t u_ar71xx_wdt_freq;
83 uint32_t u_ar71xx_refclk;
84 uint32_t u_ar71xx_mdio_freq;
87 ar71xx_chip_detect_mem_size(void)
92 ar71xx_chip_detect_sys_frequency(void)
98 u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ;
100 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
102 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
103 freq = div * AR71XX_BASE_FREQ;
105 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
106 u_ar71xx_cpu_freq = freq / div;
108 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
109 u_ar71xx_ddr_freq = freq / div;
111 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
112 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
113 u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
114 u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
118 * This does not lock the CPU whilst doing the work!
121 ar71xx_chip_device_stop(uint32_t mask)
125 reg = ATH_READ_REG(AR71XX_RST_RESET);
126 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
130 ar71xx_chip_device_start(uint32_t mask)
134 reg = ATH_READ_REG(AR71XX_RST_RESET);
135 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
139 ar71xx_chip_device_stopped(uint32_t mask)
143 reg = ATH_READ_REG(AR71XX_RST_RESET);
144 return ((reg & mask) == mask);
148 ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
150 uint32_t val, reg, ctrl;
154 reg = AR71XX_MII0_CTRL;
157 reg = AR71XX_MII1_CTRL;
160 printf("%s: invalid MII unit set for arge unit: %d\n",
167 ctrl = MII_CTRL_SPEED_10;
170 ctrl = MII_CTRL_SPEED_100;
173 ctrl = MII_CTRL_SPEED_1000;
176 printf("%s: invalid MII speed (%d) set for arge unit: %d\n",
177 __func__, speed, unit);
181 val = ATH_READ_REG(reg);
182 val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
183 val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
184 ATH_WRITE_REG(reg, val);
188 ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
190 uint32_t val, reg, mii_if;
194 reg = AR71XX_MII0_CTRL;
195 if (mii_mode == AR71XX_MII_MODE_GMII)
196 mii_if = MII0_CTRL_IF_GMII;
197 else if (mii_mode == AR71XX_MII_MODE_MII)
198 mii_if = MII0_CTRL_IF_MII;
199 else if (mii_mode == AR71XX_MII_MODE_RGMII)
200 mii_if = MII0_CTRL_IF_RGMII;
201 else if (mii_mode == AR71XX_MII_MODE_RMII)
202 mii_if = MII0_CTRL_IF_RMII;
204 printf("%s: invalid MII mode (%d) for unit %d\n",
205 __func__, mii_mode, unit);
210 reg = AR71XX_MII1_CTRL;
211 if (mii_mode == AR71XX_MII_MODE_RGMII)
212 mii_if = MII1_CTRL_IF_RGMII;
213 else if (mii_mode == AR71XX_MII_MODE_RMII)
214 mii_if = MII1_CTRL_IF_RMII;
216 printf("%s: invalid MII mode (%d) for unit %d\n",
217 __func__, mii_mode, unit);
222 printf("%s: invalid MII unit set for arge unit: %d\n",
227 val = ATH_READ_REG(reg);
228 val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT);
229 val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT;
230 ATH_WRITE_REG(reg, val);
233 /* Speed is either 10, 100 or 1000 */
235 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
240 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
241 AR71XX_PLL_ETH_INT0_CLK, pll,
242 AR71XX_PLL_ETH0_SHIFT);
245 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
246 AR71XX_PLL_ETH_INT1_CLK, pll,
247 AR71XX_PLL_ETH1_SHIFT);
250 printf("%s: invalid PLL set for arge unit: %d\n",
257 ar71xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
261 case AR71XX_CPU_DDR_FLUSH_GE0:
262 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
264 case AR71XX_CPU_DDR_FLUSH_GE1:
265 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
267 case AR71XX_CPU_DDR_FLUSH_USB:
268 ar71xx_ddr_flush(AR71XX_WB_FLUSH_USB);
270 case AR71XX_CPU_DDR_FLUSH_PCIE:
271 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
274 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
280 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
286 pll = PLL_ETH_INT_CLK_10;
289 pll = PLL_ETH_INT_CLK_100;
292 pll = PLL_ETH_INT_CLK_1000;
295 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
303 ar71xx_chip_init_usb_peripheral(void)
306 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
307 RST_RESET_USB_HOST | RST_RESET_USB_PHY);
310 ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
311 RST_RESET_USB_HOST | RST_RESET_USB_PHY);
314 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
315 USB_CTRL_CONFIG_OHCI_DES_SWAP |
316 USB_CTRL_CONFIG_OHCI_BUF_SWAP |
317 USB_CTRL_CONFIG_EHCI_DES_SWAP |
318 USB_CTRL_CONFIG_EHCI_BUF_SWAP);
320 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
321 (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
322 (3 << USB_CTRL_FLADJ_A5_SHIFT));
327 struct ar71xx_cpu_def ar71xx_chip_def = {
328 &ar71xx_chip_detect_mem_size,
329 &ar71xx_chip_detect_sys_frequency,
330 &ar71xx_chip_device_stop,
331 &ar71xx_chip_device_start,
332 &ar71xx_chip_device_stopped,
333 &ar71xx_chip_set_pll_ge,
334 &ar71xx_chip_set_mii_speed,
335 &ar71xx_chip_set_mii_if,
336 &ar71xx_chip_get_eth_pll,
337 &ar71xx_chip_ddr_flush,
338 &ar71xx_chip_init_usb_peripheral,