2 * Copyright (c) 2010 Adrian Chadd
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __AR71XX_CPUDEF_H__
30 #define __AR71XX_CPUDEF_H__
32 struct ar71xx_cpu_def {
33 void (* detect_mem_size) (void);
34 void (* detect_sys_frequency) (void);
35 void (* ar71xx_chip_device_stop) (uint32_t);
36 void (* ar71xx_chip_device_start) (uint32_t);
37 int (* ar71xx_chip_device_stopped) (uint32_t);
38 void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
39 void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
40 void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
41 void (* ar71xx_chip_ddr_flush_ge) (int);
42 uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
45 * From Linux - Handling this IRQ is a bit special.
46 * AR71xx - AR71XX_DDR_REG_FLUSH_PCI
47 * AR724x - AR724X_DDR_REG_FLUSH_PCIE
48 * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC
50 * These are set when STATUSF_IP2 is set in regiser c0.
51 * This flush is done before the IRQ is handled to make
52 * sure the driver correctly sees any memory updates.
54 void (* ar71xx_chip_ddr_flush_ip2) (void);
56 * The USB peripheral init code is subtly different for
59 void (* ar71xx_chip_init_usb_peripheral) (void);
61 void (* ar71xx_chip_reset_ethernet_switch) (void);
63 void (* ar71xx_chip_reset_wmac) (void);
65 void (* ar71xx_chip_init_gmac) (void);
67 void (* ar71xx_chip_reset_nfc) (int);
70 extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
72 static inline void ar71xx_detect_sys_frequency(void)
74 ar71xx_cpu_ops->detect_sys_frequency();
77 static inline void ar71xx_device_stop(uint32_t mask)
79 ar71xx_cpu_ops->ar71xx_chip_device_stop(mask);
82 static inline void ar71xx_device_start(uint32_t mask)
84 ar71xx_cpu_ops->ar71xx_chip_device_start(mask);
87 static inline int ar71xx_device_stopped(uint32_t mask)
89 return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
92 static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll)
94 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
97 static inline void ar71xx_device_set_mii_speed(int unit, int speed)
99 ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed);
102 static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg)
104 ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg);
107 static inline void ar71xx_device_flush_ddr_ge(int unit)
109 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit);
112 static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
114 return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed));
117 static inline void ar71xx_init_usb_peripheral(void)
119 ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
122 static inline void ar71xx_reset_ethernet_switch(void)
124 if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch)
125 ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch();
128 static inline void ar71xx_reset_wmac(void)
130 if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac)
131 ar71xx_cpu_ops->ar71xx_chip_reset_wmac();
134 static inline void ar71xx_init_gmac(void)
136 if (ar71xx_cpu_ops->ar71xx_chip_init_gmac)
137 ar71xx_cpu_ops->ar71xx_chip_init_gmac();
140 static inline void ar71xx_device_ddr_flush_ip2(void)
142 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2();
145 static inline void ar71xx_reset_nfc(int active)
148 if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc)
149 ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active);
152 /* XXX shouldn't be here! */
153 extern uint32_t u_ar71xx_refclk;
154 extern uint32_t u_ar71xx_cpu_freq;
155 extern uint32_t u_ar71xx_ahb_freq;
156 extern uint32_t u_ar71xx_ddr_freq;
157 extern uint32_t u_ar71xx_uart_freq;
158 extern uint32_t u_ar71xx_wdt_freq;
159 extern uint32_t u_ar71xx_mdio_freq;
161 static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
162 static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
163 static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
164 static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
165 static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
166 static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
167 static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; }