2 * Copyright (c) 2008 Sam Leffler. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * AR71XX attachment driver for the USB Enhanced Host Controller.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/condvar.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
42 #include <machine/bus.h>
44 #include <dev/usb/usb.h>
45 #include <dev/usb/usbdi.h>
47 #include <dev/usb/usb_core.h>
48 #include <dev/usb/usb_busdma.h>
49 #include <dev/usb/usb_process.h>
50 #include <dev/usb/usb_util.h>
52 #include <dev/usb/usb_controller.h>
53 #include <dev/usb/usb_bus.h>
54 #include <dev/usb/controller/ehci.h>
55 #include <dev/usb/controller/ehcireg.h>
57 #include <mips/atheros/ar71xx_setup.h>
58 #include <mips/atheros/ar71xxreg.h> /* for stuff in ar71xx_cpudef.h */
59 #include <mips/atheros/ar71xx_cpudef.h>
60 #include <mips/atheros/ar71xx_bus_space_reversed.h>
62 #define EHCI_HC_DEVSTR "AR71XX Integrated USB 2.0 controller"
64 struct ar71xx_ehci_softc {
65 ehci_softc_t base; /* storage for EHCI code */
68 static device_attach_t ar71xx_ehci_attach;
69 static device_detach_t ar71xx_ehci_detach;
71 bs_r_1_proto(reversed);
72 bs_w_1_proto(reversed);
75 ar71xx_ehci_probe(device_t self)
78 device_set_desc(self, EHCI_HC_DEVSTR);
80 return (BUS_PROBE_NOWILDCARD);
84 ar71xx_ehci_intr(void *arg)
87 /* XXX TODO: should really see if this was our interrupt.. */
88 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_USB);
93 ar71xx_ehci_attach(device_t self)
95 struct ar71xx_ehci_softc *isc = device_get_softc(self);
96 ehci_softc_t *sc = &isc->base;
100 /* initialise some bus fields */
101 sc->sc_bus.parent = self;
102 sc->sc_bus.devices = sc->sc_devices;
103 sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
104 sc->sc_bus.dma_bits = 32;
106 /* get all DMA memory */
107 if (usb_bus_mem_alloc_all(&sc->sc_bus,
108 USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
112 sc->sc_bus.usbrev = USB_REV_2_0;
114 /* NB: hints fix the memory location and irq */
117 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
118 if (!sc->sc_io_res) {
119 device_printf(self, "Could not map memory\n");
124 * Craft special resource for bus space ops that handle
125 * byte-alignment of non-word addresses.
127 sc->sc_io_tag = ar71xx_bus_space_reversed;
128 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
129 sc->sc_io_size = rman_get_size(sc->sc_io_res);
132 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
133 RF_ACTIVE | RF_SHAREABLE);
134 if (sc->sc_irq_res == NULL) {
135 device_printf(self, "Could not allocate irq\n");
138 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
139 if (!sc->sc_bus.bdev) {
140 device_printf(self, "Could not add USB device\n");
143 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
144 device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
146 sprintf(sc->sc_vendor, "Atheros");
148 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
149 NULL, ar71xx_ehci_intr, sc, &sc->sc_intr_hdl);
151 device_printf(self, "Could not setup irq, %d\n", err);
152 sc->sc_intr_hdl = NULL;
157 * Arrange to force Host mode, select big-endian byte alignment,
158 * and arrange to not terminate reset operations (the adapter
159 * will ignore it if we do but might as well save a reg write).
160 * Also, the controller has an embedded Transaction Translator
161 * which means port speed must be read from the Port Status
162 * register following a port enable.
164 sc->sc_flags = EHCI_SCFLG_SETMODE;
166 switch (ar71xx_soc) {
167 case AR71XX_SOC_AR7241:
168 case AR71XX_SOC_AR7242:
169 case AR71XX_SOC_AR9130:
170 case AR71XX_SOC_AR9132:
171 case AR71XX_SOC_AR9330:
172 case AR71XX_SOC_AR9331:
173 case AR71XX_SOC_AR9341:
174 case AR71XX_SOC_AR9342:
175 case AR71XX_SOC_AR9344:
176 case AR71XX_SOC_QCA9533:
177 case AR71XX_SOC_QCA9533_V2:
178 case AR71XX_SOC_QCA9556:
179 case AR71XX_SOC_QCA9558:
180 sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
188 * ehci_reset() needs the correct offset to access the host controller
189 * registers. The AR724x/AR913x offsets aren't 0.
191 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
193 (void) ehci_reset(sc);
197 err = device_probe_and_attach(sc->sc_bus.bdev);
200 device_printf(self, "USB init failed err=%d\n", err);
206 ar71xx_ehci_detach(self);
211 ar71xx_ehci_detach(device_t self)
213 struct ar71xx_ehci_softc *isc = device_get_softc(self);
214 ehci_softc_t *sc = &isc->base;
218 if (sc->sc_bus.bdev) {
219 bdev = sc->sc_bus.bdev;
221 device_delete_child(self, bdev);
223 /* during module unload there are lots of children leftover */
224 device_delete_children(self);
226 if (sc->sc_irq_res && sc->sc_intr_hdl) {
228 * only call ehci_detach() after ehci_init()
232 err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
235 /* XXX or should we panic? */
236 device_printf(self, "Could not tear down irq, %d\n",
238 sc->sc_intr_hdl = NULL;
241 if (sc->sc_irq_res) {
242 bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
243 sc->sc_irq_res = NULL;
246 bus_release_resource(self, SYS_RES_MEMORY, 0,
248 sc->sc_io_res = NULL;
250 usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
255 static device_method_t ehci_methods[] = {
256 /* Device interface */
257 DEVMETHOD(device_probe, ar71xx_ehci_probe),
258 DEVMETHOD(device_attach, ar71xx_ehci_attach),
259 DEVMETHOD(device_detach, ar71xx_ehci_detach),
260 DEVMETHOD(device_suspend, bus_generic_suspend),
261 DEVMETHOD(device_resume, bus_generic_resume),
262 DEVMETHOD(device_shutdown, bus_generic_shutdown),
267 static driver_t ehci_driver = {
269 .methods = ehci_methods,
270 .size = sizeof(struct ar71xx_ehci_softc),
273 static devclass_t ehci_devclass;
275 DRIVER_MODULE(ehci, nexus, ehci_driver, ehci_devclass, 0, 0);
276 DRIVER_MODULE(ehci, apb, ehci_driver, ehci_devclass, 0, 0);
278 MODULE_DEPEND(ehci, usb, 1, 1, 1);