2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * GPIO driver for AR71xx
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <mips/atheros/ar71xxreg.h>
51 #include <mips/atheros/ar71xx_setup.h>
52 #include <mips/atheros/ar71xx_cpudef.h>
53 #include <mips/atheros/ar71xx_gpiovar.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <mips/atheros/ar933xreg.h>
56 #include <mips/atheros/ar934xreg.h>
57 #include <mips/atheros/qca955xreg.h>
61 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
66 static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
68 static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
70 static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
71 struct gpio_pin *pin, uint32_t flags);
76 static int ar71xx_gpio_probe(device_t dev);
77 static int ar71xx_gpio_attach(device_t dev);
78 static int ar71xx_gpio_detach(device_t dev);
79 static int ar71xx_gpio_filter(void *arg);
80 static void ar71xx_gpio_intr(void *arg);
85 static device_t ar71xx_gpio_get_bus(device_t);
86 static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
87 static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
88 static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
90 static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
91 static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
92 static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
93 static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
94 static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
97 * Enable/disable the GPIO function control space.
99 * This is primarily for the AR71xx, which has SPI CS1/CS2, UART, SLIC, I2S
100 * as GPIO pin options.
103 ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
105 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
106 ar71xx_soc == AR71XX_SOC_AR9342 ||
107 ar71xx_soc == AR71XX_SOC_AR9344 ||
108 ar71xx_soc == AR71XX_SOC_QCA9556 ||
109 ar71xx_soc == AR71XX_SOC_QCA9558)
110 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
112 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
116 ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
118 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
119 ar71xx_soc == AR71XX_SOC_AR9342 ||
120 ar71xx_soc == AR71XX_SOC_AR9344 ||
121 ar71xx_soc == AR71XX_SOC_QCA9556 ||
122 ar71xx_soc == AR71XX_SOC_QCA9558)
123 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
125 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
129 ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
134 mask = 1 << pin->gp_pin;
137 * Manage input/output
139 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
140 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
141 if (flags & GPIO_PIN_OUTPUT) {
142 pin->gp_flags |= GPIO_PIN_OUTPUT;
143 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
146 pin->gp_flags |= GPIO_PIN_INPUT;
147 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
153 ar71xx_gpio_get_bus(device_t dev)
155 struct ar71xx_gpio_softc *sc;
157 sc = device_get_softc(dev);
163 ar71xx_gpio_pin_max(device_t dev, int *maxpin)
166 switch (ar71xx_soc) {
167 case AR71XX_SOC_AR9130:
168 case AR71XX_SOC_AR9132:
169 *maxpin = AR91XX_GPIO_PINS - 1;
171 case AR71XX_SOC_AR7240:
172 case AR71XX_SOC_AR7241:
173 case AR71XX_SOC_AR7242:
174 *maxpin = AR724X_GPIO_PINS - 1;
176 case AR71XX_SOC_AR9330:
177 case AR71XX_SOC_AR9331:
178 *maxpin = AR933X_GPIO_COUNT - 1;
180 case AR71XX_SOC_AR9341:
181 case AR71XX_SOC_AR9342:
182 case AR71XX_SOC_AR9344:
183 *maxpin = AR934X_GPIO_COUNT - 1;
185 case AR71XX_SOC_QCA9556:
186 case AR71XX_SOC_QCA9558:
187 *maxpin = QCA955X_GPIO_COUNT - 1;
190 *maxpin = AR71XX_GPIO_PINS - 1;
196 ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
198 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
201 for (i = 0; i < sc->gpio_npins; i++) {
202 if (sc->gpio_pins[i].gp_pin == pin)
206 if (i >= sc->gpio_npins)
210 *caps = sc->gpio_pins[i].gp_caps;
217 ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
219 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
222 for (i = 0; i < sc->gpio_npins; i++) {
223 if (sc->gpio_pins[i].gp_pin == pin)
227 if (i >= sc->gpio_npins)
231 *flags = sc->gpio_pins[i].gp_flags;
238 ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
240 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
243 for (i = 0; i < sc->gpio_npins; i++) {
244 if (sc->gpio_pins[i].gp_pin == pin)
248 if (i >= sc->gpio_npins)
252 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
259 ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
262 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
264 for (i = 0; i < sc->gpio_npins; i++) {
265 if (sc->gpio_pins[i].gp_pin == pin)
269 if (i >= sc->gpio_npins)
272 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
278 ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
280 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
283 for (i = 0; i < sc->gpio_npins; i++) {
284 if (sc->gpio_pins[i].gp_pin == pin)
288 if (i >= sc->gpio_npins)
292 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
294 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
300 ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
302 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
305 for (i = 0; i < sc->gpio_npins; i++) {
306 if (sc->gpio_pins[i].gp_pin == pin)
310 if (i >= sc->gpio_npins)
313 *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
319 ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
322 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
324 for (i = 0; i < sc->gpio_npins; i++) {
325 if (sc->gpio_pins[i].gp_pin == pin)
329 if (i >= sc->gpio_npins)
332 res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
334 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
336 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
342 ar71xx_gpio_filter(void *arg)
345 /* TODO: something useful */
346 return (FILTER_STRAY);
352 ar71xx_gpio_intr(void *arg)
354 struct ar71xx_gpio_softc *sc = arg;
356 /* TODO: something useful */
361 ar71xx_gpio_probe(device_t dev)
364 device_set_desc(dev, "Atheros AR71XX GPIO driver");
369 ar71xx_gpio_attach(device_t dev)
371 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
376 KASSERT((device_get_unit(dev) == 0),
377 ("ar71xx_gpio: Only one gpio module supported"));
379 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
381 /* Map control/status registers. */
382 sc->gpio_mem_rid = 0;
383 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
384 &sc->gpio_mem_rid, RF_ACTIVE);
386 if (sc->gpio_mem_res == NULL) {
387 device_printf(dev, "couldn't map memory\n");
388 ar71xx_gpio_detach(dev);
392 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
393 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
394 device_printf(dev, "unable to allocate IRQ resource\n");
395 ar71xx_gpio_detach(dev);
399 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
400 ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
402 "WARNING: unable to register interrupt handler\n");
403 ar71xx_gpio_detach(dev);
409 /* Enable function bits that are required */
410 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
411 "function_set", &mask) == 0) {
412 device_printf(dev, "function_set: 0x%x\n", mask);
413 ar71xx_gpio_function_enable(sc, mask);
415 /* Disable function bits that are required */
416 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
417 "function_clear", &mask) == 0) {
418 device_printf(dev, "function_clear: 0x%x\n", mask);
419 ar71xx_gpio_function_disable(sc, mask);
422 /* Disable interrupts for all pins. */
423 GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
425 /* Initialise all pins specified in the mask, up to the pin count */
426 (void) ar71xx_gpio_pin_max(dev, &maxpin);
427 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
428 "pinmask", &mask) != 0)
430 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
431 "pinon", &pinon) != 0)
433 device_printf(dev, "gpio pinmask=0x%x\n", mask);
434 for (j = 0; j <= maxpin; j++) {
435 if ((mask & (1 << j)) == 0)
439 /* Iniatilize the GPIO pins, keep the loader settings. */
440 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
441 sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
442 M_DEVBUF, M_WAITOK | M_ZERO);
443 for (i = 0, j = 0; j <= maxpin; j++) {
444 if ((mask & (1 << j)) == 0)
446 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
448 sc->gpio_pins[i].gp_pin = j;
449 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
451 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
453 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
457 /* Turn on the hinted pins. */
458 for (i = 0; i < sc->gpio_npins; i++) {
459 j = sc->gpio_pins[i].gp_pin;
460 if ((pinon & (1 << j)) != 0) {
461 ar71xx_gpio_pin_setflags(dev, j, GPIO_PIN_OUTPUT);
462 ar71xx_gpio_pin_set(dev, j, 1);
467 * Search through the function hints, in case there's some
468 * overrides such as LNA control.
470 * hint.gpio.X.func.<pin>.gpiofunc=<func value>
471 * hint.gpio.X.func.<pin>.gpiomode=1 (for output, default low)
473 for (i = 0; i <= maxpin; i++) {
475 int gpiofunc, gpiomode;
477 snprintf(buf, 32, "func.%d.gpiofunc", i);
478 if (resource_int_value(device_get_name(dev),
479 device_get_unit(dev),
483 /* Get the mode too */
484 snprintf(buf, 32, "func.%d.gpiomode", i);
485 if (resource_int_value(device_get_name(dev),
486 device_get_unit(dev),
491 /* We only handle mode=1 for now */
495 device_printf(dev, "%s: GPIO %d: func=%d, mode=%d\n",
501 /* Set output (bit == 0) */
502 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
504 GPIO_WRITE(sc, AR71XX_GPIO_OE, oe);
506 /* Set pin value = 0, so it stays low by default */
507 oe = GPIO_READ(sc, AR71XX_GPIO_OUT);
509 GPIO_WRITE(sc, AR71XX_GPIO_OUT, oe);
511 /* Finally: Set the output config */
512 ar71xx_gpio_ouput_configure(i, gpiofunc);
515 sc->busdev = gpiobus_attach_bus(dev);
516 if (sc->busdev == NULL) {
517 ar71xx_gpio_detach(dev);
525 ar71xx_gpio_detach(device_t dev)
527 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
529 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
531 gpiobus_detach_bus(dev);
533 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
534 if (sc->gpio_irq_res)
535 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
537 if (sc->gpio_mem_res)
538 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
541 free(sc->gpio_pins, M_DEVBUF);
542 mtx_destroy(&sc->gpio_mtx);
547 static device_method_t ar71xx_gpio_methods[] = {
548 DEVMETHOD(device_probe, ar71xx_gpio_probe),
549 DEVMETHOD(device_attach, ar71xx_gpio_attach),
550 DEVMETHOD(device_detach, ar71xx_gpio_detach),
553 DEVMETHOD(gpio_get_bus, ar71xx_gpio_get_bus),
554 DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
555 DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
556 DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
557 DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
558 DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
559 DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
560 DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
561 DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
565 static driver_t ar71xx_gpio_driver = {
568 sizeof(struct ar71xx_gpio_softc),
570 static devclass_t ar71xx_gpio_devclass;
572 DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);