2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * GPIO driver for AR71xx
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <mips/atheros/ar71xxreg.h>
51 #include <mips/atheros/ar71xx_setup.h>
52 #include <mips/atheros/ar71xx_cpudef.h>
53 #include <mips/atheros/ar71xx_gpiovar.h>
54 #include <dev/gpio/gpiobusvar.h>
55 #include <mips/atheros/ar933xreg.h>
56 #include <mips/atheros/ar934xreg.h>
57 #include <mips/atheros/qca953xreg.h>
58 #include <mips/atheros/qca955xreg.h>
62 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
67 static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
69 static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
71 static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
72 struct gpio_pin *pin, uint32_t flags);
77 static int ar71xx_gpio_probe(device_t dev);
78 static int ar71xx_gpio_attach(device_t dev);
79 static int ar71xx_gpio_detach(device_t dev);
80 static int ar71xx_gpio_filter(void *arg);
81 static void ar71xx_gpio_intr(void *arg);
86 static device_t ar71xx_gpio_get_bus(device_t);
87 static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
88 static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
89 static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
91 static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
92 static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
93 static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
94 static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
95 static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
98 * Enable/disable the GPIO function control space.
100 * This is primarily for the AR71xx, which has SPI CS1/CS2, UART, SLIC, I2S
101 * as GPIO pin options.
104 ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
108 * XXX TODO: refactor this out into a per-chipset method.
110 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
111 ar71xx_soc == AR71XX_SOC_AR9342 ||
112 ar71xx_soc == AR71XX_SOC_AR9344 ||
113 ar71xx_soc == AR71XX_SOC_QCA9533 ||
114 ar71xx_soc == AR71XX_SOC_QCA9533_V2 ||
115 ar71xx_soc == AR71XX_SOC_QCA9556 ||
116 ar71xx_soc == AR71XX_SOC_QCA9558)
117 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
119 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
123 ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
127 * XXX TODO: refactor this out into a per-chipset method.
129 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
130 ar71xx_soc == AR71XX_SOC_AR9342 ||
131 ar71xx_soc == AR71XX_SOC_AR9344 ||
132 ar71xx_soc == AR71XX_SOC_QCA9533 ||
133 ar71xx_soc == AR71XX_SOC_QCA9533_V2 ||
134 ar71xx_soc == AR71XX_SOC_QCA9556 ||
135 ar71xx_soc == AR71XX_SOC_QCA9558)
136 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
138 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
142 * On most platforms, GPIO_OE is a bitmap where the bit set
143 * means "enable output."
145 * On AR934x and QCA953x, it's the opposite - the bit set means
149 ar71xx_gpio_oe_is_high(void)
151 switch (ar71xx_soc) {
152 case AR71XX_SOC_AR9344:
153 case AR71XX_SOC_QCA9533:
154 case AR71XX_SOC_QCA9533_V2:
162 ar71xx_gpio_oe_set_output(struct ar71xx_gpio_softc *sc, int b)
168 if (ar71xx_gpio_oe_is_high())
169 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
171 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
175 ar71xx_gpio_oe_set_input(struct ar71xx_gpio_softc *sc, int b)
181 if (ar71xx_gpio_oe_is_high())
182 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
184 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
188 ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
193 * Manage input/output
195 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
196 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
197 if (flags & GPIO_PIN_OUTPUT) {
198 pin->gp_flags |= GPIO_PIN_OUTPUT;
199 ar71xx_gpio_oe_set_output(sc, pin->gp_pin);
201 pin->gp_flags |= GPIO_PIN_INPUT;
202 ar71xx_gpio_oe_set_input(sc, pin->gp_pin);
208 ar71xx_gpio_get_bus(device_t dev)
210 struct ar71xx_gpio_softc *sc;
212 sc = device_get_softc(dev);
218 ar71xx_gpio_pin_max(device_t dev, int *maxpin)
221 switch (ar71xx_soc) {
222 case AR71XX_SOC_AR9130:
223 case AR71XX_SOC_AR9132:
224 *maxpin = AR91XX_GPIO_PINS - 1;
226 case AR71XX_SOC_AR7240:
227 case AR71XX_SOC_AR7241:
228 case AR71XX_SOC_AR7242:
229 *maxpin = AR724X_GPIO_PINS - 1;
231 case AR71XX_SOC_AR9330:
232 case AR71XX_SOC_AR9331:
233 *maxpin = AR933X_GPIO_COUNT - 1;
235 case AR71XX_SOC_AR9341:
236 case AR71XX_SOC_AR9342:
237 case AR71XX_SOC_AR9344:
238 *maxpin = AR934X_GPIO_COUNT - 1;
240 case AR71XX_SOC_QCA9533:
241 case AR71XX_SOC_QCA9533_V2:
242 *maxpin = QCA953X_GPIO_COUNT - 1;
244 case AR71XX_SOC_QCA9556:
245 case AR71XX_SOC_QCA9558:
246 *maxpin = QCA955X_GPIO_COUNT - 1;
249 *maxpin = AR71XX_GPIO_PINS - 1;
255 ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
257 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
260 for (i = 0; i < sc->gpio_npins; i++) {
261 if (sc->gpio_pins[i].gp_pin == pin)
265 if (i >= sc->gpio_npins)
269 *caps = sc->gpio_pins[i].gp_caps;
276 ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
278 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
281 for (i = 0; i < sc->gpio_npins; i++) {
282 if (sc->gpio_pins[i].gp_pin == pin)
286 if (i >= sc->gpio_npins)
290 *flags = sc->gpio_pins[i].gp_flags;
297 ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
299 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
302 for (i = 0; i < sc->gpio_npins; i++) {
303 if (sc->gpio_pins[i].gp_pin == pin)
307 if (i >= sc->gpio_npins)
311 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
318 ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
321 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
323 for (i = 0; i < sc->gpio_npins; i++) {
324 if (sc->gpio_pins[i].gp_pin == pin)
328 if (i >= sc->gpio_npins)
331 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
337 ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
339 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
342 for (i = 0; i < sc->gpio_npins; i++) {
343 if (sc->gpio_pins[i].gp_pin == pin)
347 if (i >= sc->gpio_npins)
351 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
353 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
359 ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
361 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
364 for (i = 0; i < sc->gpio_npins; i++) {
365 if (sc->gpio_pins[i].gp_pin == pin)
369 if (i >= sc->gpio_npins)
372 *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
378 ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
381 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
383 for (i = 0; i < sc->gpio_npins; i++) {
384 if (sc->gpio_pins[i].gp_pin == pin)
388 if (i >= sc->gpio_npins)
391 res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
393 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
395 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
401 ar71xx_gpio_filter(void *arg)
404 /* TODO: something useful */
405 return (FILTER_STRAY);
411 ar71xx_gpio_intr(void *arg)
413 struct ar71xx_gpio_softc *sc = arg;
415 /* TODO: something useful */
420 ar71xx_gpio_probe(device_t dev)
423 device_set_desc(dev, "Atheros AR71XX GPIO driver");
428 ar71xx_gpio_attach(device_t dev)
430 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
435 KASSERT((device_get_unit(dev) == 0),
436 ("ar71xx_gpio: Only one gpio module supported"));
438 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
440 /* Map control/status registers. */
441 sc->gpio_mem_rid = 0;
442 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
443 &sc->gpio_mem_rid, RF_ACTIVE);
445 if (sc->gpio_mem_res == NULL) {
446 device_printf(dev, "couldn't map memory\n");
447 ar71xx_gpio_detach(dev);
451 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
452 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
453 device_printf(dev, "unable to allocate IRQ resource\n");
454 ar71xx_gpio_detach(dev);
458 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
459 ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
461 "WARNING: unable to register interrupt handler\n");
462 ar71xx_gpio_detach(dev);
468 /* Enable function bits that are required */
469 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
470 "function_set", &mask) == 0) {
471 device_printf(dev, "function_set: 0x%x\n", mask);
472 ar71xx_gpio_function_enable(sc, mask);
474 /* Disable function bits that are required */
475 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
476 "function_clear", &mask) == 0) {
477 device_printf(dev, "function_clear: 0x%x\n", mask);
478 ar71xx_gpio_function_disable(sc, mask);
481 /* Disable interrupts for all pins. */
482 GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
484 /* Initialise all pins specified in the mask, up to the pin count */
485 (void) ar71xx_gpio_pin_max(dev, &maxpin);
486 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
487 "pinmask", &mask) != 0)
489 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
490 "pinon", &pinon) != 0)
492 device_printf(dev, "gpio pinmask=0x%x\n", mask);
493 for (j = 0; j <= maxpin; j++) {
494 if ((mask & (1 << j)) == 0)
498 /* Iniatilize the GPIO pins, keep the loader settings. */
499 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
501 * For AR934x and QCA953x, the meaning of oe is inverted;
502 * so flip it the right way around so we can parse the GPIO
505 if (!ar71xx_gpio_oe_is_high())
508 sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
509 M_DEVBUF, M_WAITOK | M_ZERO);
510 for (i = 0, j = 0; j <= maxpin; j++) {
511 if ((mask & (1 << j)) == 0)
513 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
515 sc->gpio_pins[i].gp_pin = j;
516 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
518 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
520 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
524 /* Turn on the hinted pins. */
525 for (i = 0; i < sc->gpio_npins; i++) {
526 j = sc->gpio_pins[i].gp_pin;
527 if ((pinon & (1 << j)) != 0) {
528 ar71xx_gpio_pin_setflags(dev, j, GPIO_PIN_OUTPUT);
529 ar71xx_gpio_pin_set(dev, j, 1);
534 * Search through the function hints, in case there's some
535 * overrides such as LNA control.
537 * hint.gpio.X.func.<pin>.gpiofunc=<func value>
538 * hint.gpio.X.func.<pin>.gpiomode=1 (for output, default low)
540 for (i = 0; i <= maxpin; i++) {
542 int gpiofunc, gpiomode;
544 snprintf(buf, 32, "func.%d.gpiofunc", i);
545 if (resource_int_value(device_get_name(dev),
546 device_get_unit(dev),
550 /* Get the mode too */
551 snprintf(buf, 32, "func.%d.gpiomode", i);
552 if (resource_int_value(device_get_name(dev),
553 device_get_unit(dev),
558 /* We only handle mode=1 for now */
562 device_printf(dev, "%s: GPIO %d: func=%d, mode=%d\n",
568 /* Set pin value = 0, so it stays low by default */
569 oe = GPIO_READ(sc, AR71XX_GPIO_OUT);
571 GPIO_WRITE(sc, AR71XX_GPIO_OUT, oe);
574 ar71xx_gpio_oe_set_output(sc, i);
576 /* Finally: Set the output config */
577 ar71xx_gpio_ouput_configure(i, gpiofunc);
580 sc->busdev = gpiobus_attach_bus(dev);
581 if (sc->busdev == NULL) {
582 ar71xx_gpio_detach(dev);
590 ar71xx_gpio_detach(device_t dev)
592 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
594 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
596 gpiobus_detach_bus(dev);
598 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
599 if (sc->gpio_irq_res)
600 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
602 if (sc->gpio_mem_res)
603 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
606 free(sc->gpio_pins, M_DEVBUF);
607 mtx_destroy(&sc->gpio_mtx);
612 static device_method_t ar71xx_gpio_methods[] = {
613 DEVMETHOD(device_probe, ar71xx_gpio_probe),
614 DEVMETHOD(device_attach, ar71xx_gpio_attach),
615 DEVMETHOD(device_detach, ar71xx_gpio_detach),
618 DEVMETHOD(gpio_get_bus, ar71xx_gpio_get_bus),
619 DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
620 DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
621 DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
622 DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
623 DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
624 DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
625 DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
626 DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
630 static driver_t ar71xx_gpio_driver = {
633 sizeof(struct ar71xx_gpio_softc),
635 static devclass_t ar71xx_gpio_devclass;
637 DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);