2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/interrupt.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
43 #include <vm/vm_extern.h>
45 #include <machine/bus.h>
46 #include <machine/cpu.h>
47 #include <machine/pmap.h>
49 #include <dev/spibus/spi.h>
50 #include <dev/spibus/spibusvar.h>
51 #include "spibus_if.h"
53 #include <mips/atheros/ar71xxreg.h>
55 #undef AR71XX_SPI_DEBUG
56 #ifdef AR71XX_SPI_DEBUG
57 #define dprintf printf
59 #define dprintf(x, arg...)
63 * register space access macros
66 #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
67 BUS_SPACE_BARRIER_WRITE)
68 #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
69 BUS_SPACE_BARRIER_READ)
70 #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
71 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
73 #define SPI_WRITE(sc, reg, val) do { \
74 bus_write_4(sc->sc_mem_res, (reg), (val)); \
77 #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))
79 #define SPI_SET_BITS(sc, reg, bits) \
80 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))
82 #define SPI_CLEAR_BITS(sc, reg, bits) \
83 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))
85 struct ar71xx_spi_softc {
87 struct resource *sc_mem_res;
92 ar71xx_spi_probe(device_t dev)
94 device_set_desc(dev, "AR71XX SPI");
95 return (BUS_PROBE_NOWILDCARD);
99 ar71xx_spi_attach(device_t dev)
101 struct ar71xx_spi_softc *sc = device_get_softc(dev);
106 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
108 if (!sc->sc_mem_res) {
109 device_printf(dev, "Could not map memory\n");
113 SPI_WRITE(sc, AR71XX_SPI_FS, 1);
115 /* Flush out read before reading the control register */
116 SPI_BARRIER_WRITE(sc);
118 sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL);
121 * XXX TODO: document what the SPI control register does.
123 SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43);
126 * Ensure the config register write has gone out before configuring
127 * the chip select mask.
129 SPI_BARRIER_WRITE(sc);
130 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
133 * .. and ensure the write has gone out before continuing.
135 SPI_BARRIER_WRITE(sc);
137 device_add_child(dev, "spibus", -1);
138 return (bus_generic_attach(dev));
142 ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs)
144 uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
146 * Put respective CSx to low
148 ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
151 * Make sure any other writes have gone out to the
152 * device before changing the chip select line;
153 * then ensure that it has made it out to the device
156 SPI_BARRIER_WRITE(sc);
157 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl);
158 SPI_BARRIER_WRITE(sc);
162 ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs)
165 * Put all CSx to high
167 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
171 ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data)
175 uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
177 * low-level for selected CS
179 ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
182 for (bit = 7; bit >=0; bit--) {
183 if (data & (1 << bit))
184 iod = ioctrl | SPI_IO_CTRL_DO;
186 iod = ioctrl & ~SPI_IO_CTRL_DO;
187 SPI_BARRIER_WRITE(sc);
188 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
189 SPI_BARRIER_WRITE(sc);
190 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK);
194 * Provide falling edge for connected device by clear clock bit.
196 SPI_BARRIER_WRITE(sc);
197 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
198 SPI_BARRIER_WRITE(sc);
199 rds = SPI_READ(sc, AR71XX_SPI_RDS);
205 ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
207 struct ar71xx_spi_softc *sc;
208 uint8_t *buf_in, *buf_out;
209 struct spibus_ivar *devi = SPIBUS_IVAR(child);
212 sc = device_get_softc(dev);
214 ar71xx_spi_chip_activate(sc, devi->cs);
216 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
217 ("TX/RX command sizes should be equal"));
218 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
219 ("TX/RX data sizes should be equal"));
224 buf_out = (uint8_t *)cmd->tx_cmd;
225 buf_in = (uint8_t *)cmd->rx_cmd;
226 for (i = 0; i < cmd->tx_cmd_sz; i++)
227 buf_in[i] = ar71xx_spi_txrx(sc, devi->cs, buf_out[i]);
230 * Receive/transmit data (depends on command)
232 buf_out = (uint8_t *)cmd->tx_data;
233 buf_in = (uint8_t *)cmd->rx_data;
234 for (i = 0; i < cmd->tx_data_sz; i++)
235 buf_in[i] = ar71xx_spi_txrx(sc, devi->cs, buf_out[i]);
237 ar71xx_spi_chip_deactivate(sc, devi->cs);
243 ar71xx_spi_detach(device_t dev)
245 struct ar71xx_spi_softc *sc = device_get_softc(dev);
248 * Ensure any other writes to the device are finished
249 * before we tear down the SPI device.
251 SPI_BARRIER_WRITE(sc);
254 * Restore the control register; ensure it has hit the
255 * hardware before continuing.
257 SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
258 SPI_BARRIER_WRITE(sc);
261 * And now, put the flash back into mapped IO mode and
262 * ensure _that_ has completed before we finish up.
264 SPI_WRITE(sc, AR71XX_SPI_FS, 0);
265 SPI_BARRIER_WRITE(sc);
268 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
273 static device_method_t ar71xx_spi_methods[] = {
274 /* Device interface */
275 DEVMETHOD(device_probe, ar71xx_spi_probe),
276 DEVMETHOD(device_attach, ar71xx_spi_attach),
277 DEVMETHOD(device_detach, ar71xx_spi_detach),
279 DEVMETHOD(spibus_transfer, ar71xx_spi_transfer),
284 static driver_t ar71xx_spi_driver = {
287 sizeof(struct ar71xx_spi_softc),
290 static devclass_t ar71xx_spi_devclass;
292 DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0);