2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/interrupt.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
43 #include <vm/vm_extern.h>
45 #include <machine/bus.h>
46 #include <machine/cpu.h>
48 #include <dev/spibus/spi.h>
49 #include <dev/spibus/spibusvar.h>
50 #include "spibus_if.h"
52 #include <mips/atheros/ar71xxreg.h>
54 #undef AR71XX_SPI_DEBUG
55 #ifdef AR71XX_SPI_DEBUG
56 #define dprintf printf
58 #define dprintf(x, arg...)
62 * register space access macros
65 #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
66 BUS_SPACE_BARRIER_WRITE)
67 #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
68 BUS_SPACE_BARRIER_READ)
69 #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
70 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
72 #define SPI_WRITE(sc, reg, val) do { \
73 bus_write_4(sc->sc_mem_res, (reg), (val)); \
76 #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))
78 #define SPI_SET_BITS(sc, reg, bits) \
79 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))
81 #define SPI_CLEAR_BITS(sc, reg, bits) \
82 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))
84 struct ar71xx_spi_softc {
86 struct resource *sc_mem_res;
91 ar71xx_spi_probe(device_t dev)
93 device_set_desc(dev, "AR71XX SPI");
94 return (BUS_PROBE_NOWILDCARD);
98 ar71xx_spi_attach(device_t dev)
100 struct ar71xx_spi_softc *sc = device_get_softc(dev);
105 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
107 if (!sc->sc_mem_res) {
108 device_printf(dev, "Could not map memory\n");
112 SPI_WRITE(sc, AR71XX_SPI_FS, 1);
114 /* Flush out read before reading the control register */
115 SPI_BARRIER_WRITE(sc);
117 sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL);
120 * XXX TODO: document what the SPI control register does.
122 SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43);
125 * Ensure the config register write has gone out before configuring
126 * the chip select mask.
128 SPI_BARRIER_WRITE(sc);
129 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
132 * .. and ensure the write has gone out before continuing.
134 SPI_BARRIER_WRITE(sc);
136 device_add_child(dev, "spibus", -1);
137 return (bus_generic_attach(dev));
141 ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs)
143 uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
145 * Put respective CSx to low
147 ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
150 * Make sure any other writes have gone out to the
151 * device before changing the chip select line;
152 * then ensure that it has made it out to the device
155 SPI_BARRIER_WRITE(sc);
156 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl);
157 SPI_BARRIER_WRITE(sc);
161 ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs)
164 * Put all CSx to high
166 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
170 ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data)
174 uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
176 * low-level for selected CS
178 ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
181 for (bit = 7; bit >=0; bit--) {
182 if (data & (1 << bit))
183 iod = ioctrl | SPI_IO_CTRL_DO;
185 iod = ioctrl & ~SPI_IO_CTRL_DO;
186 SPI_BARRIER_WRITE(sc);
187 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
188 SPI_BARRIER_WRITE(sc);
189 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK);
193 * Provide falling edge for connected device by clear clock bit.
195 SPI_BARRIER_WRITE(sc);
196 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
197 SPI_BARRIER_WRITE(sc);
198 rds = SPI_READ(sc, AR71XX_SPI_RDS);
204 ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
206 struct ar71xx_spi_softc *sc;
208 uint8_t *buf_in, *buf_out;
211 sc = device_get_softc(dev);
213 spibus_get_cs(child, &cs);
215 cs &= ~SPIBUS_CS_HIGH;
217 ar71xx_spi_chip_activate(sc, cs);
219 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
220 ("TX/RX command sizes should be equal"));
221 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
222 ("TX/RX data sizes should be equal"));
227 buf_out = (uint8_t *)cmd->tx_cmd;
228 buf_in = (uint8_t *)cmd->rx_cmd;
229 for (i = 0; i < cmd->tx_cmd_sz; i++)
230 buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]);
233 * Receive/transmit data (depends on command)
235 buf_out = (uint8_t *)cmd->tx_data;
236 buf_in = (uint8_t *)cmd->rx_data;
237 for (i = 0; i < cmd->tx_data_sz; i++)
238 buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]);
240 ar71xx_spi_chip_deactivate(sc, cs);
246 ar71xx_spi_detach(device_t dev)
248 struct ar71xx_spi_softc *sc = device_get_softc(dev);
251 * Ensure any other writes to the device are finished
252 * before we tear down the SPI device.
254 SPI_BARRIER_WRITE(sc);
257 * Restore the control register; ensure it has hit the
258 * hardware before continuing.
260 SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
261 SPI_BARRIER_WRITE(sc);
264 * And now, put the flash back into mapped IO mode and
265 * ensure _that_ has completed before we finish up.
267 SPI_WRITE(sc, AR71XX_SPI_FS, 0);
268 SPI_BARRIER_WRITE(sc);
271 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
276 static device_method_t ar71xx_spi_methods[] = {
277 /* Device interface */
278 DEVMETHOD(device_probe, ar71xx_spi_probe),
279 DEVMETHOD(device_attach, ar71xx_spi_attach),
280 DEVMETHOD(device_detach, ar71xx_spi_detach),
282 DEVMETHOD(spibus_transfer, ar71xx_spi_transfer),
287 static driver_t ar71xx_spi_driver = {
290 sizeof(struct ar71xx_spi_softc),
293 static devclass_t ar71xx_spi_devclass;
295 DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0);