2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
45 #include <vm/vm_extern.h>
47 #include <machine/bus.h>
48 #include <machine/cpu.h>
50 #include <dev/spibus/spi.h>
51 #include <dev/spibus/spibusvar.h>
52 #include "spibus_if.h"
54 #include <mips/atheros/ar71xxreg.h>
56 #undef AR71XX_SPI_DEBUG
57 #ifdef AR71XX_SPI_DEBUG
58 #define dprintf printf
60 #define dprintf(x, arg...)
64 * register space access macros
67 #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
68 BUS_SPACE_BARRIER_WRITE)
69 #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
70 BUS_SPACE_BARRIER_READ)
71 #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \
72 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
74 #define SPI_WRITE(sc, reg, val) do { \
75 bus_write_4(sc->sc_mem_res, (reg), (val)); \
78 #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))
80 #define SPI_SET_BITS(sc, reg, bits) \
81 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))
83 #define SPI_CLEAR_BITS(sc, reg, bits) \
84 SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))
86 struct ar71xx_spi_softc {
88 struct resource *sc_mem_res;
93 ar71xx_spi_probe(device_t dev)
95 device_set_desc(dev, "AR71XX SPI");
96 return (BUS_PROBE_NOWILDCARD);
100 ar71xx_spi_attach(device_t dev)
102 struct ar71xx_spi_softc *sc = device_get_softc(dev);
107 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
109 if (!sc->sc_mem_res) {
110 device_printf(dev, "Could not map memory\n");
114 SPI_WRITE(sc, AR71XX_SPI_FS, 1);
116 /* Flush out read before reading the control register */
117 SPI_BARRIER_WRITE(sc);
119 sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL);
122 * XXX TODO: document what the SPI control register does.
124 SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43);
127 * Ensure the config register write has gone out before configuring
128 * the chip select mask.
130 SPI_BARRIER_WRITE(sc);
131 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
134 * .. and ensure the write has gone out before continuing.
136 SPI_BARRIER_WRITE(sc);
138 device_add_child(dev, "spibus", -1);
139 return (bus_generic_attach(dev));
143 ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs)
145 uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
147 * Put respective CSx to low
149 ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
152 * Make sure any other writes have gone out to the
153 * device before changing the chip select line;
154 * then ensure that it has made it out to the device
157 SPI_BARRIER_WRITE(sc);
158 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl);
159 SPI_BARRIER_WRITE(sc);
163 ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs)
166 * Put all CSx to high
168 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
172 ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data)
176 uint32_t ioctrl = SPI_IO_CTRL_CSMASK;
178 * low-level for selected CS
180 ioctrl &= ~(SPI_IO_CTRL_CS0 << cs);
183 for (bit = 7; bit >=0; bit--) {
184 if (data & (1 << bit))
185 iod = ioctrl | SPI_IO_CTRL_DO;
187 iod = ioctrl & ~SPI_IO_CTRL_DO;
188 SPI_BARRIER_WRITE(sc);
189 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
190 SPI_BARRIER_WRITE(sc);
191 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK);
195 * Provide falling edge for connected device by clear clock bit.
197 SPI_BARRIER_WRITE(sc);
198 SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
199 SPI_BARRIER_WRITE(sc);
200 rds = SPI_READ(sc, AR71XX_SPI_RDS);
206 ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
208 struct ar71xx_spi_softc *sc;
210 uint8_t *buf_in, *buf_out;
213 sc = device_get_softc(dev);
215 spibus_get_cs(child, &cs);
217 cs &= ~SPIBUS_CS_HIGH;
219 ar71xx_spi_chip_activate(sc, cs);
221 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
222 ("TX/RX command sizes should be equal"));
223 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
224 ("TX/RX data sizes should be equal"));
229 buf_out = (uint8_t *)cmd->tx_cmd;
230 buf_in = (uint8_t *)cmd->rx_cmd;
231 for (i = 0; i < cmd->tx_cmd_sz; i++)
232 buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]);
235 * Receive/transmit data (depends on command)
237 buf_out = (uint8_t *)cmd->tx_data;
238 buf_in = (uint8_t *)cmd->rx_data;
239 for (i = 0; i < cmd->tx_data_sz; i++)
240 buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]);
242 ar71xx_spi_chip_deactivate(sc, cs);
248 ar71xx_spi_detach(device_t dev)
250 struct ar71xx_spi_softc *sc = device_get_softc(dev);
253 * Ensure any other writes to the device are finished
254 * before we tear down the SPI device.
256 SPI_BARRIER_WRITE(sc);
259 * Restore the control register; ensure it has hit the
260 * hardware before continuing.
262 SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
263 SPI_BARRIER_WRITE(sc);
266 * And now, put the flash back into mapped IO mode and
267 * ensure _that_ has completed before we finish up.
269 SPI_WRITE(sc, AR71XX_SPI_FS, 0);
270 SPI_BARRIER_WRITE(sc);
273 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
278 static device_method_t ar71xx_spi_methods[] = {
279 /* Device interface */
280 DEVMETHOD(device_probe, ar71xx_spi_probe),
281 DEVMETHOD(device_attach, ar71xx_spi_attach),
282 DEVMETHOD(device_detach, ar71xx_spi_detach),
284 DEVMETHOD(spibus_transfer, ar71xx_spi_transfer),
289 static driver_t ar71xx_spi_driver = {
292 sizeof(struct ar71xx_spi_softc),
295 static devclass_t ar71xx_spi_devclass;
297 DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0);