sys/mips/atheros/ar91xx_chip.c

   1 /*-
   2  * Copyright (c) 2010 Adrian Chadd
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_ddb.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/cons.h>
  38 #include <sys/kdb.h>
  39 #include <sys/reboot.h>
  40
  41 #include <vm/vm.h>
  42 #include <vm/vm_page.h>
  43
  44 #include <net/ethernet.h>
  45
  46 #include <machine/clock.h>
  47 #include <machine/cpu.h>
  48 #include <machine/cpuregs.h>
  49 #include <machine/hwfunc.h>
  50 #include <machine/md_var.h>
  51 #include <machine/trap.h>
  52 #include <machine/vmparam.h>
  53
  54 #include <mips/atheros/ar71xxreg.h>
  55 #include <mips/atheros/ar71xx_cpudef.h>
  56 #include <mips/atheros/ar71xx_chip.h>
  57 #include <mips/atheros/ar91xxreg.h>
  58 #include <mips/atheros/ar91xx_chip.h>
  59
  60 static void
  61 ar91xx_chip_detect_mem_size(void)
  62 {
  63 }
  64
  65 static void
  66 ar91xx_chip_detect_sys_frequency(void)
  67 {
  68         uint32_t pll;
  69         uint32_t freq;
  70         uint32_t div;
  71
  72         u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ;
  73
  74         pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
  75
  76         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
  77         freq = div * AR91XX_BASE_FREQ;
  78         u_ar71xx_cpu_freq = freq;
  79
  80         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
  81         u_ar71xx_ddr_freq = freq / div;
  82
  83         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
  84         u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
  85         u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
  86         u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
  87 }
  88
  89 static void
  90 ar91xx_chip_device_stop(uint32_t mask)
  91 {
  92         uint32_t reg;
  93
  94         reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
  95         ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
  96 }
  97
  98 static void
  99 ar91xx_chip_device_start(uint32_t mask)
 100 {
 101         uint32_t reg;
 102
 103         reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
 104         ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
 105 }
 106
 107 static int
 108 ar91xx_chip_device_stopped(uint32_t mask)
 109 {
 110         uint32_t reg;
 111
 112         reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
 113         return ((reg & mask) == mask);
 114 }
 115
 116 static void
 117 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
 118 {
 119
 120         switch (unit) {
 121         case 0:
 122                 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
 123                     AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
 124                     AR91XX_ETH0_PLL_SHIFT);
 125                 break;
 126         case 1:
 127                 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
 128                     AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
 129                     AR91XX_ETH1_PLL_SHIFT);
 130                 break;
 131         default:
 132                 printf("%s: invalid PLL set for arge unit: %d\n",
 133                     __func__, unit);
 134                 return;
 135         }
 136 }
 137
 138 static void
 139 ar91xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
 140 {
 141
 142         switch (id) {
 143         case AR71XX_CPU_DDR_FLUSH_GE0:
 144                 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
 145                 break;
 146         case AR71XX_CPU_DDR_FLUSH_GE1:
 147                 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
 148                 break;
 149         case AR71XX_CPU_DDR_FLUSH_USB:
 150                 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
 151                 break;
 152         case AR71XX_CPU_DDR_FLUSH_WMAC:
 153                 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
 154                 break;
 155         default:
 156                 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
 157                 break;
 158         }
 159 }
 160
 161 static uint32_t
 162 ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
 163 {
 164         uint32_t pll;
 165
 166         switch(speed) {
 167         case 10:
 168                 pll = AR91XX_PLL_VAL_10;
 169                 break;
 170         case 100:
 171                 pll = AR91XX_PLL_VAL_100;
 172                 break;
 173         case 1000:
 174                 pll = AR91XX_PLL_VAL_1000;
 175                 break;
 176         default:
 177                 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
 178                 pll = 0;
 179         }
 180
 181         return (pll);
 182 }
 183
 184 static void
 185 ar91xx_chip_init_usb_peripheral(void)
 186 {
 187
 188         ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
 189         DELAY(100);
 190
 191         ar71xx_device_start(RST_RESET_USB_HOST);
 192         DELAY(100);
 193
 194         ar71xx_device_start(RST_RESET_USB_PHY);
 195         DELAY(100);
 196
 197         /* Wireless */
 198         ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
 199         DELAY(1000);
 200
 201         ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
 202         DELAY(1000);
 203 }
 204
 205 struct ar71xx_cpu_def ar91xx_chip_def = {
 206         &ar91xx_chip_detect_mem_size,
 207         &ar91xx_chip_detect_sys_frequency,
 208         &ar91xx_chip_device_stop,
 209         &ar91xx_chip_device_start,
 210         &ar91xx_chip_device_stopped,
 211         &ar91xx_chip_set_pll_ge,
 212         &ar71xx_chip_set_mii_speed,
 213         &ar71xx_chip_set_mii_if,
 214         &ar91xx_chip_get_eth_pll,
 215         &ar91xx_chip_ddr_flush,
 216         &ar91xx_chip_init_usb_peripheral,
 217 };