2 * Copyright (c) 2010 Adrian Chadd
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar71xx_cpudef.h>
56 #include <mips/atheros/ar71xx_chip.h>
57 #include <mips/atheros/ar91xxreg.h>
58 #include <mips/atheros/ar91xx_chip.h>
61 ar91xx_chip_detect_mem_size(void)
66 ar91xx_chip_detect_sys_frequency(void)
72 u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ;
74 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
76 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
77 freq = div * AR91XX_BASE_FREQ;
78 u_ar71xx_cpu_freq = freq;
80 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
81 u_ar71xx_ddr_freq = freq / div;
83 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
84 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
85 u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
86 u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
90 ar91xx_chip_device_stop(uint32_t mask)
94 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
95 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
99 ar91xx_chip_device_start(uint32_t mask)
103 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
104 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
108 ar91xx_chip_device_stopped(uint32_t mask)
112 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
113 return ((reg & mask) == mask);
117 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
122 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
123 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
124 AR91XX_ETH0_PLL_SHIFT);
127 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
128 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
129 AR91XX_ETH1_PLL_SHIFT);
132 printf("%s: invalid PLL set for arge unit: %d\n",
139 ar91xx_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
143 case AR71XX_CPU_DDR_FLUSH_GE0:
144 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
146 case AR71XX_CPU_DDR_FLUSH_GE1:
147 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
149 case AR71XX_CPU_DDR_FLUSH_USB:
150 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB);
152 case AR71XX_CPU_DDR_FLUSH_WMAC:
153 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
156 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
162 ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
168 pll = AR91XX_PLL_VAL_10;
171 pll = AR91XX_PLL_VAL_100;
174 pll = AR91XX_PLL_VAL_1000;
177 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
185 ar91xx_chip_init_usb_peripheral(void)
188 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
191 ar71xx_device_start(RST_RESET_USB_HOST);
194 ar71xx_device_start(RST_RESET_USB_PHY);
198 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
201 ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
205 struct ar71xx_cpu_def ar91xx_chip_def = {
206 &ar91xx_chip_detect_mem_size,
207 &ar91xx_chip_detect_sys_frequency,
208 &ar91xx_chip_device_stop,
209 &ar91xx_chip_device_start,
210 &ar91xx_chip_device_stopped,
211 &ar91xx_chip_set_pll_ge,
212 &ar71xx_chip_set_mii_speed,
213 &ar71xx_chip_set_mii_if,
214 &ar91xx_chip_get_eth_pll,
215 &ar91xx_chip_ddr_flush,
216 &ar91xx_chip_init_usb_peripheral,