2 * Copyright (c) 2010 Adrian Chadd
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __AR91XX_REG_H__
30 #define __AR91XX_REG_H__
32 #define AR91XX_BASE_FREQ 5000000
35 #define AR91XX_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c
37 #define AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE (1 << 10)
40 #define AR91XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
41 #define AR91XX_PLL_REG_ETH_CONFIG AR71XX_PLL_CPU_BASE + 0x04
42 #define AR91XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
43 #define AR91XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x18
45 #define AR91XX_PLL_DIV_SHIFT 0
46 #define AR91XX_PLL_DIV_MASK 0x3ff
47 #define AR91XX_DDR_DIV_SHIFT 22
48 #define AR91XX_DDR_DIV_MASK 0x3
49 #define AR91XX_AHB_DIV_SHIFT 19
50 #define AR91XX_AHB_DIV_MASK 0x1
52 #define AR91XX_ETH0_PLL_SHIFT 20
53 #define AR91XX_ETH1_PLL_SHIFT 22
55 #define AR91XX_PLL_VAL_1000 0x1a000000
56 #define AR91XX_PLL_VAL_100 0x13000a44
57 #define AR91XX_PLL_VAL_10 0x00441099
60 #define AR91XX_DDR_CTRLBASE (AR71XX_APB_BASE + 0)
61 #define AR91XX_DDR_CTRL_SIZE 0x10000
62 #define AR91XX_DDR_REG_FLUSH_GE0 AR91XX_DDR_CTRLBASE + 0x7c
63 #define AR91XX_DDR_REG_FLUSH_GE1 AR91XX_DDR_CTRLBASE + 0x80
64 #define AR91XX_DDR_REG_FLUSH_USB AR91XX_DDR_CTRLBASE + 0x84
65 #define AR91XX_DDR_REG_FLUSH_WMAC AR91XX_DDR_CTRLBASE + 0x88
68 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
69 #define AR91XX_WMAC_SIZE 0x30000
72 #define AR91XX_GPIO_FUNC_WMAC_LED_EN (1 << 22)
73 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN (1 << 21)
74 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN (1 << 20)
75 #define AR91XX_GPIO_FUNC_I2S_MCKEN (1 << 19)
76 #define AR91XX_GPIO_FUNC_I2S1_EN (1 << 18)
77 #define AR91XX_GPIO_FUNC_I2S0_EN (1 << 17)
78 #define AR91XX_GPIO_FUNC_SLIC_EN (1 << 16)
79 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN (1 << 9)
80 #define AR91XX_GPIO_FUNC_UART_EN (1 << 8)
81 #define AR91XX_GPIO_FUNC_USB_CLK_EN (1 << 4)
83 #define AR91XX_GPIO_COUNT 22