2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar933xreg.h>
57 #include <mips/atheros/ar71xx_cpudef.h>
58 #include <mips/atheros/ar71xx_setup.h>
60 #include <mips/atheros/ar71xx_chip.h>
61 #include <mips/atheros/ar933x_chip.h>
64 ar933x_chip_detect_mem_size(void)
69 ar933x_chip_detect_sys_frequency(void)
76 t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
77 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
78 u_ar71xx_refclk = (40 * 1000 * 1000);
80 u_ar71xx_refclk = (25 * 1000 * 1000);
82 clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
83 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
84 u_ar71xx_cpu_freq = u_ar71xx_refclk;
85 u_ar71xx_ahb_freq = u_ar71xx_refclk;
86 u_ar71xx_ddr_freq = u_ar71xx_refclk;
88 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
90 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
92 freq = u_ar71xx_refclk / t;
94 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
95 AR933X_PLL_CPU_CONFIG_NINT_MASK;
98 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
99 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
105 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
106 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
107 u_ar71xx_cpu_freq = freq / t;
109 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
110 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
111 u_ar71xx_ddr_freq = freq / t;
113 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
114 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
115 u_ar71xx_ahb_freq = freq / t;
119 * On the AR933x, the UART frequency is the reference clock,
120 * not the AHB bus clock.
122 u_ar71xx_uart_freq = u_ar71xx_refclk;
125 * XXX TODO: check whether the mdio frequency is always the
126 * refclock frequency, or whether it's variable like on the
129 u_ar71xx_mdio_freq = u_ar71xx_refclk;
132 * XXX check what the watchdog frequency should be?
134 u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
138 ar933x_chip_device_stop(uint32_t mask)
142 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
143 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
147 ar933x_chip_device_start(uint32_t mask)
151 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
152 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
156 ar933x_chip_device_stopped(uint32_t mask)
160 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
161 return ((reg & mask) == mask);
165 ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
176 ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
187 printf("%s: invalid PLL set for arge unit: %d\n",
194 ar933x_chip_ddr_flush_ge(int unit)
199 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
202 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
205 printf("%s: invalid DDR flush for arge unit: %d\n",
212 ar933x_chip_ddr_flush_ip2(void)
215 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
219 ar933x_chip_get_eth_pll(unsigned int mac, int speed)
225 pll = AR933X_PLL_VAL_10;
228 pll = AR933X_PLL_VAL_100;
231 pll = AR933X_PLL_VAL_1000;
234 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
241 ar933x_chip_init_usb_peripheral(void)
243 ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
246 ar71xx_device_start(AR933X_RESET_USB_HOST);
249 ar71xx_device_start(AR933X_RESET_USB_PHY);
254 ar933x_configure_gmac(uint32_t gmac_cfg)
258 reg = ATH_READ_REG(AR933X_GMAC_REG_ETH_CFG);
261 * The relevant bits here include:
263 * + AR933X_ETH_CFG_SW_PHY_SWAP
264 * + AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
266 * There are other things; look at what openwrt exposes so
267 * it can be correctly exposed.
269 * TODO: what about ethernet switch support? How's that work?
272 printf("%s: GMAC config was 0x%08x\n", __func__, reg);
273 reg &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
276 printf("%s: GMAC setting is 0x%08x; register is now 0x%08x\n",
280 ATH_WRITE_REG(AR933X_GMAC_REG_ETH_CFG, reg);
284 ar933x_chip_init_gmac(void)
287 uint32_t gmac_cfg = 0;
290 * These two bits need a bit better explanation.
292 * The default configuration in the hardware is to map both
293 * ports to the internal switch.
295 * Here, GE0 == arge0, GE1 == arge1.
297 * The internal switch has:
298 * + 5 MAC ports, MAC0->MAC4.
299 * + 5 PHY ports, PHY0->PHY4,
300 * + MAC0 connects to GE1;
301 * + GE0 connects to PHY4;
302 * + The other mappings are MAC1->PHY0, MAC2->PHY1 .. MAC4->PHY3.
304 * The GE1 port is linked in via 1000MBit/full, supplying what is
305 * normally the 'WAN' switch ports.
307 * The switch is connected the MDIO bus on GE1. It looks like
308 * a normal AR7240 on-board switch.
310 * The GE0 port is connected via MII to PHY4, and can operate in
311 * 10/100mbit, full/half duplex. Ie, you can speak to PHY4 on
312 * the MDIO bus and everything will simply 'work'.
314 * So far so good. This looks just like an AR7240 SoC.
316 * However, some configurations will just expose one or two
317 * physical ports. In this case, some configuration bits can
318 * be set to tweak this.
320 * + CFG_SW_PHY_ADDR_SWAP swaps PHY port 0 with PHY port 4.
321 * Ie, GE0's PHY shows up as PHY 0. So if there's only
322 * one physical port, there's no need to involve the
323 * switch framework - it can just show up as a default,
326 * + CFG_SW_PHY_SWAP swaps the internal switch connection
327 * between PHY0 and PHY4. Ie, PHY4 connects to MAc1,
328 * PHY0 connects to GE0.
330 if ((resource_int_value("ar933x_gmac", 0, "override_phy", &val) == 0)
333 if ((resource_int_value("ar933x_gmac", 0, "swap_phy", &val) == 0)
335 gmac_cfg |= AR933X_ETH_CFG_SW_PHY_SWAP;
336 if ((resource_int_value("ar933x_gmac", 0, "swap_phy_addr", &val) == 0)
338 gmac_cfg |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
339 ar933x_configure_gmac(gmac_cfg);
342 struct ar71xx_cpu_def ar933x_chip_def = {
343 &ar933x_chip_detect_mem_size,
344 &ar933x_chip_detect_sys_frequency,
345 &ar933x_chip_device_stop,
346 &ar933x_chip_device_start,
347 &ar933x_chip_device_stopped,
348 &ar933x_chip_set_pll_ge,
349 &ar933x_chip_set_mii_speed,
350 &ar71xx_chip_set_mii_if,
351 &ar933x_chip_ddr_flush_ge,
352 &ar933x_chip_get_eth_pll,
353 &ar933x_chip_ddr_flush_ip2,
354 &ar933x_chip_init_usb_peripheral,
357 &ar933x_chip_init_gmac,