2 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar934xreg.h>
57 #include <mips/atheros/ar71xx_cpudef.h>
58 #include <mips/atheros/ar71xx_setup.h>
60 #include <mips/atheros/ar71xx_chip.h>
61 #include <mips/atheros/ar934x_chip.h>
64 ar934x_chip_detect_mem_size(void)
69 ar934x_get_pll_freq(uint32_t ref, uint32_t ref_div, uint32_t nint,
70 uint32_t nfrac, uint32_t frac, uint32_t out_div)
82 t = t / (ref_div * frac);
85 ret /= (1 << out_div);
90 ar934x_chip_detect_sys_frequency(void)
92 uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
93 uint32_t cpu_pll, ddr_pll;
97 bootstrap = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
98 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
99 u_ar71xx_refclk = 40 * 1000 * 1000;
101 u_ar71xx_refclk = 25 * 1000 * 1000;
103 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
104 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
105 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
106 AR934X_SRIF_DPLL2_OUTDIV_MASK;
107 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
108 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
109 AR934X_SRIF_DPLL1_NINT_MASK;
110 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
111 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
112 AR934X_SRIF_DPLL1_REFDIV_MASK;
115 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
116 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
117 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
118 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
119 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
120 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
121 AR934X_PLL_CPU_CONFIG_NINT_MASK;
122 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
123 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
127 cpu_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
128 nfrac, frac, out_div);
130 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
131 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
132 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
133 AR934X_SRIF_DPLL2_OUTDIV_MASK;
134 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
135 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
136 AR934X_SRIF_DPLL1_NINT_MASK;
137 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
138 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
139 AR934X_SRIF_DPLL1_REFDIV_MASK;
142 pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
143 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
144 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
145 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
146 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
147 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
148 AR934X_PLL_DDR_CONFIG_NINT_MASK;
149 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
150 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
154 ddr_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
155 nfrac, frac, out_div);
157 clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
159 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
160 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
162 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
163 u_ar71xx_cpu_freq = u_ar71xx_refclk;
164 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
165 u_ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
167 u_ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
169 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
170 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
172 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
173 u_ar71xx_ddr_freq = u_ar71xx_refclk;
174 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
175 u_ar71xx_ddr_freq = ddr_pll / (postdiv + 1);
177 u_ar71xx_ddr_freq = cpu_pll / (postdiv + 1);
179 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
180 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
182 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
183 u_ar71xx_ahb_freq = u_ar71xx_refclk;
184 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
185 u_ar71xx_ahb_freq = ddr_pll / (postdiv + 1);
187 u_ar71xx_ahb_freq = cpu_pll / (postdiv + 1);
189 u_ar71xx_wdt_freq = u_ar71xx_refclk;
190 u_ar71xx_uart_freq = u_ar71xx_refclk;
193 * Next, fetch reference clock speed for MDIO bus.
195 reg = ATH_READ_REG(AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
196 if (reg & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
197 printf("%s: mdio=100MHz\n", __func__);
198 u_ar71xx_mdio_freq = (100 * 1000 * 1000);
200 printf("%s: mdio=%d Hz\n", __func__, u_ar71xx_refclk);
201 u_ar71xx_mdio_freq = u_ar71xx_refclk;
206 ar934x_chip_device_stop(uint32_t mask)
210 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
211 ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg | mask);
215 ar934x_chip_device_start(uint32_t mask)
219 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
220 ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg & ~mask);
224 ar934x_chip_device_stopped(uint32_t mask)
228 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
229 return ((reg & mask) == mask);
233 ar934x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
244 ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
249 ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll);
255 printf("%s: invalid PLL set for arge unit: %d\n",
262 ar934x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
266 case AR71XX_CPU_DDR_FLUSH_GE0:
267 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
269 case AR71XX_CPU_DDR_FLUSH_GE1:
270 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
272 case AR71XX_CPU_DDR_FLUSH_USB:
273 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_USB);
275 case AR71XX_CPU_DDR_FLUSH_PCIE:
276 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
278 case AR71XX_CPU_DDR_FLUSH_WMAC:
279 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
282 printf("%s: invalid DDR flush id (%d)\n", __func__, id);
289 ar934x_chip_get_eth_pll(unsigned int mac, int speed)
295 pll = AR934X_PLL_VAL_10;
298 pll = AR934X_PLL_VAL_100;
301 pll = AR934X_PLL_VAL_1000;
304 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
311 ar934x_chip_reset_ethernet_switch(void)
314 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH);
316 ar71xx_device_start(AR934X_RESET_ETH_SWITCH);
318 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
320 ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
325 ar934x_configure_gmac(uint32_t gmac_cfg)
329 reg = ATH_READ_REG(AR934X_GMAC_REG_ETH_CFG);
330 printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
332 reg &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
333 AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
334 AR934X_ETH_CFG_SW_PHY_SWAP);
338 ATH_WRITE_REG(AR934X_GMAC_REG_ETH_CFG, reg);
342 ar934x_chip_init_usb_peripheral(void)
346 reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
347 if (reg & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
350 ar71xx_device_stop(AR934X_RESET_USBSUS_OVERRIDE);
353 ar71xx_device_start(AR934X_RESET_USB_PHY);
356 ar71xx_device_start(AR934X_RESET_USB_PHY_ANALOG);
359 ar71xx_device_start(AR934X_RESET_USB_HOST);
364 ar934x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
370 * Nothing to see here; although gmac0 can have its
371 * MII configuration changed, the register values
372 * are slightly different.
377 * XXX TODO: fetch default MII divider configuration
381 ar934x_chip_reset_wmac(void)
388 ar934x_chip_init_gmac(void)
392 if (resource_long_value("ar934x_gmac", 0, "gmac_cfg",
394 printf("%s: gmac_cfg=0x%08lx\n",
397 ar934x_configure_gmac((uint32_t) gmac_cfg);
402 * Reset the NAND Flash Controller.
404 * + active=1 means "make it active".
405 * + active=0 means "make it inactive".
408 ar934x_chip_reset_nfc(int active)
412 ar71xx_device_start(AR934X_RESET_NANDF);
415 ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
418 ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
421 ar71xx_device_stop(AR934X_RESET_NANDF);
427 * Configure the GPIO output mux setup.
429 * The AR934x introduced an output mux which allowed
430 * certain functions to be configured on any pin.
431 * Specifically, the switch PHY link LEDs and
432 * WMAC external RX LNA switches are not limited to
433 * a specific GPIO pin.
436 ar934x_chip_gpio_output_configure(int gpio, uint8_t func)
441 if (gpio > AR934X_GPIO_COUNT)
444 reg = AR934X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
447 /* read-modify-write */
448 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
451 ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
454 ATH_READ_REG(AR71XX_GPIO_BASE + reg);
457 struct ar71xx_cpu_def ar934x_chip_def = {
458 &ar934x_chip_detect_mem_size,
459 &ar934x_chip_detect_sys_frequency,
460 &ar934x_chip_device_stop,
461 &ar934x_chip_device_start,
462 &ar934x_chip_device_stopped,
463 &ar934x_chip_set_pll_ge,
464 &ar934x_chip_set_mii_speed,
465 &ar934x_chip_set_mii_if,
466 &ar934x_chip_get_eth_pll,
467 &ar934x_chip_ddr_flush,
468 &ar934x_chip_init_usb_peripheral,
469 &ar934x_chip_reset_ethernet_switch,
470 &ar934x_chip_reset_wmac,
471 &ar934x_chip_init_gmac,
472 &ar934x_chip_reset_nfc,
473 &ar934x_chip_gpio_output_configure,