sys/mips/atheros/if_arge.c

   1 /*-
   2  * Copyright (c) 2009, Oleksandr Tymoshenko
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 /*
  32  * AR71XX gigabit ethernet driver
  33  */
  34 #ifdef HAVE_KERNEL_OPTION_HEADERS
  35 #include "opt_device_polling.h"
  36 #endif
  37
  38 #include "opt_arge.h"
  39
  40 #include <sys/param.h>
  41 #include <sys/endian.h>
  42 #include <sys/systm.h>
  43 #include <sys/sockio.h>
  44 #include <sys/lock.h>
  45 #include <sys/mbuf.h>
  46 #include <sys/malloc.h>
  47 #include <sys/mutex.h>
  48 #include <sys/kernel.h>
  49 #include <sys/module.h>
  50 #include <sys/socket.h>
  51 #include <sys/taskqueue.h>
  52 #include <sys/sysctl.h>
  53
  54 #include <net/if.h>
  55 #include <net/if_var.h>
  56 #include <net/if_media.h>
  57 #include <net/ethernet.h>
  58 #include <net/if_types.h>
  59
  60 #include <net/bpf.h>
  61
  62 #include <machine/bus.h>
  63 #include <machine/cache.h>
  64 #include <machine/resource.h>
  65 #include <vm/vm_param.h>
  66 #include <vm/vm.h>
  67 #include <vm/pmap.h>
  68 #include <machine/pmap.h>
  69 #include <sys/bus.h>
  70 #include <sys/rman.h>
  71
  72 #include <dev/mii/mii.h>
  73 #include <dev/mii/miivar.h>
  74
  75 #include <dev/pci/pcireg.h>
  76 #include <dev/pci/pcivar.h>
  77
  78 #include "opt_arge.h"
  79
  80 #if defined(ARGE_MDIO)
  81 #include <dev/etherswitch/mdio.h>
  82 #include <dev/etherswitch/miiproxy.h>
  83 #include "mdio_if.h"
  84 #endif
  85
  86
  87 MODULE_DEPEND(arge, ether, 1, 1, 1);
  88 MODULE_DEPEND(arge, miibus, 1, 1, 1);
  89 MODULE_VERSION(arge, 1);
  90
  91 #include "miibus_if.h"
  92
  93 #include <net/ethernet.h>
  94
  95 #include <mips/atheros/ar71xxreg.h>
  96 #include <mips/atheros/ar934xreg.h>     /* XXX tsk! */
  97 #include <mips/atheros/qca953xreg.h>    /* XXX tsk! */
  98 #include <mips/atheros/qca955xreg.h>    /* XXX tsk! */
  99 #include <mips/atheros/if_argevar.h>
 100 #include <mips/atheros/ar71xx_setup.h>
 101 #include <mips/atheros/ar71xx_cpudef.h>
 102 #include <mips/atheros/ar71xx_macaddr.h>
 103
 104 typedef enum {
 105         ARGE_DBG_MII    =       0x00000001,
 106         ARGE_DBG_INTR   =       0x00000002,
 107         ARGE_DBG_TX     =       0x00000004,
 108         ARGE_DBG_RX     =       0x00000008,
 109         ARGE_DBG_ERR    =       0x00000010,
 110         ARGE_DBG_RESET  =       0x00000020,
 111         ARGE_DBG_PLL    =       0x00000040,
 112 } arge_debug_flags;
 113
 114 static const char * arge_miicfg_str[] = {
 115         "NONE",
 116         "GMII",
 117         "MII",
 118         "RGMII",
 119         "RMII",
 120         "SGMII"
 121 };
 122
 123 #ifdef ARGE_DEBUG
 124 #define ARGEDEBUG(_sc, _m, ...)                                         \
 125         do {                                                            \
 126                 if ((_m) & (_sc)->arge_debug)                           \
 127                         device_printf((_sc)->arge_dev, __VA_ARGS__);    \
 128         } while (0)
 129 #else
 130 #define ARGEDEBUG(_sc, _m, ...)
 131 #endif
 132
 133 static int arge_attach(device_t);
 134 static int arge_detach(device_t);
 135 static void arge_flush_ddr(struct arge_softc *);
 136 static int arge_ifmedia_upd(struct ifnet *);
 137 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 138 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
 139 static void arge_init(void *);
 140 static void arge_init_locked(struct arge_softc *);
 141 static void arge_link_task(void *, int);
 142 static void arge_update_link_locked(struct arge_softc *sc);
 143 static void arge_set_pll(struct arge_softc *, int, int);
 144 static int arge_miibus_readreg(device_t, int, int);
 145 static void arge_miibus_statchg(device_t);
 146 static int arge_miibus_writereg(device_t, int, int, int);
 147 static int arge_probe(device_t);
 148 static void arge_reset_dma(struct arge_softc *);
 149 static int arge_resume(device_t);
 150 static int arge_rx_ring_init(struct arge_softc *);
 151 static void arge_rx_ring_free(struct arge_softc *sc);
 152 static int arge_tx_ring_init(struct arge_softc *);
 153 static void arge_tx_ring_free(struct arge_softc *);
 154 #ifdef DEVICE_POLLING
 155 static int arge_poll(struct ifnet *, enum poll_cmd, int);
 156 #endif
 157 static int arge_shutdown(device_t);
 158 static void arge_start(struct ifnet *);
 159 static void arge_start_locked(struct ifnet *);
 160 static void arge_stop(struct arge_softc *);
 161 static int arge_suspend(device_t);
 162
 163 static int arge_rx_locked(struct arge_softc *);
 164 static void arge_tx_locked(struct arge_softc *);
 165 static void arge_intr(void *);
 166 static int arge_intr_filter(void *);
 167 static void arge_tick(void *);
 168
 169 static void arge_hinted_child(device_t bus, const char *dname, int dunit);
 170
 171 /*
 172  * ifmedia callbacks for multiPHY MAC
 173  */
 174 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
 175 int arge_multiphy_mediachange(struct ifnet *);
 176
 177 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 178 static int arge_dma_alloc(struct arge_softc *);
 179 static void arge_dma_free(struct arge_softc *);
 180 static int arge_newbuf(struct arge_softc *, int);
 181 static __inline void arge_fixup_rx(struct mbuf *);
 182
 183 static device_method_t arge_methods[] = {
 184         /* Device interface */
 185         DEVMETHOD(device_probe,         arge_probe),
 186         DEVMETHOD(device_attach,        arge_attach),
 187         DEVMETHOD(device_detach,        arge_detach),
 188         DEVMETHOD(device_suspend,       arge_suspend),
 189         DEVMETHOD(device_resume,        arge_resume),
 190         DEVMETHOD(device_shutdown,      arge_shutdown),
 191
 192         /* MII interface */
 193         DEVMETHOD(miibus_readreg,       arge_miibus_readreg),
 194         DEVMETHOD(miibus_writereg,      arge_miibus_writereg),
 195         DEVMETHOD(miibus_statchg,       arge_miibus_statchg),
 196
 197         /* bus interface */
 198         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 199         DEVMETHOD(bus_hinted_child,     arge_hinted_child),
 200
 201         DEVMETHOD_END
 202 };
 203
 204 static driver_t arge_driver = {
 205         "arge",
 206         arge_methods,
 207         sizeof(struct arge_softc)
 208 };
 209
 210 static devclass_t arge_devclass;
 211
 212 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
 213 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
 214
 215 #if defined(ARGE_MDIO)
 216 static int argemdio_probe(device_t);
 217 static int argemdio_attach(device_t);
 218 static int argemdio_detach(device_t);
 219
 220 /*
 221  * Declare an additional, separate driver for accessing the MDIO bus.
 222  */
 223 static device_method_t argemdio_methods[] = {
 224         /* Device interface */
 225         DEVMETHOD(device_probe,         argemdio_probe),
 226         DEVMETHOD(device_attach,        argemdio_attach),
 227         DEVMETHOD(device_detach,        argemdio_detach),
 228
 229         /* bus interface */
 230         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 231
 232         /* MDIO access */
 233         DEVMETHOD(mdio_readreg,         arge_miibus_readreg),
 234         DEVMETHOD(mdio_writereg,        arge_miibus_writereg),
 235 };
 236
 237 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
 238     sizeof(struct arge_softc));
 239 static devclass_t argemdio_devclass;
 240
 241 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
 242 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
 243 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
 244 #endif
 245
 246 static struct mtx miibus_mtx;
 247
 248 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
 249
 250 /*
 251  * Flushes all
 252  *
 253  * XXX this needs to be done at interrupt time! Grr!
 254  */
 255 static void
 256 arge_flush_ddr(struct arge_softc *sc)
 257 {
 258         switch (sc->arge_mac_unit) {
 259         case 0:
 260                 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE0);
 261                 break;
 262         case 1:
 263                 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE1);
 264                 break;
 265         default:
 266                 device_printf(sc->arge_dev, "%s: unknown unit (%d)\n",
 267                     __func__,
 268                     sc->arge_mac_unit);
 269                 break;
 270         }
 271 }
 272
 273 static int
 274 arge_probe(device_t dev)
 275 {
 276
 277         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
 278         return (BUS_PROBE_NOWILDCARD);
 279 }
 280
 281 #ifdef  ARGE_DEBUG
 282 static void
 283 arge_attach_intr_sysctl(device_t dev, struct sysctl_oid_list *parent)
 284 {
 285         struct arge_softc *sc = device_get_softc(dev);
 286         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 287         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 288         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
 289         char sn[8];
 290         int i;
 291
 292         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "intr",
 293             CTLFLAG_RD, NULL, "Interrupt statistics");
 294         child = SYSCTL_CHILDREN(tree);
 295         for (i = 0; i < 32; i++) {
 296                 snprintf(sn, sizeof(sn), "%d", i);
 297                 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD,
 298                     &sc->intr_stats.count[i], 0, "");
 299         }
 300 }
 301 #endif
 302
 303 static void
 304 arge_attach_sysctl(device_t dev)
 305 {
 306         struct arge_softc *sc = device_get_softc(dev);
 307         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 308         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 309
 310 #ifdef  ARGE_DEBUG
 311         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 312                 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
 313                 "arge interface debugging flags");
 314         arge_attach_intr_sysctl(dev, SYSCTL_CHILDREN(tree));
 315 #endif
 316
 317         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 318                 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
 319                 "number of TX aligned packets");
 320
 321         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 322                 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
 323                 0, "number of TX unaligned packets");
 324
 325         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 326                 "tx_pkts_unaligned_start", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_start,
 327                 0, "number of TX unaligned packets (start)");
 328
 329         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 330                 "tx_pkts_unaligned_len", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_len,
 331                 0, "number of TX unaligned packets (len)");
 332
 333         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 334                 "tx_pkts_nosegs", CTLFLAG_RW, &sc->stats.tx_pkts_nosegs,
 335                 0, "number of TX packets fail with no ring slots avail");
 336
 337         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 338                 "intr_stray_filter", CTLFLAG_RW, &sc->stats.intr_stray,
 339                 0, "number of stray interrupts (filter)");
 340
 341         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 342                 "intr_stray_intr", CTLFLAG_RW, &sc->stats.intr_stray2,
 343                 0, "number of stray interrupts (intr)");
 344
 345         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 346                 "intr_ok", CTLFLAG_RW, &sc->stats.intr_ok,
 347                 0, "number of OK interrupts");
 348 #ifdef  ARGE_DEBUG
 349         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
 350             CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
 351         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
 352             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
 353         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
 354             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
 355 #endif
 356 }
 357
 358 static void
 359 arge_reset_mac(struct arge_softc *sc)
 360 {
 361         uint32_t reg;
 362         uint32_t reset_reg;
 363
 364         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s called\n", __func__);
 365
 366         /* Step 1. Soft-reset MAC */
 367         ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
 368         DELAY(20);
 369
 370         /* Step 2. Punt the MAC core from the central reset register */
 371         /*
 372          * XXX TODO: migrate this (and other) chip specific stuff into
 373          * a chipdef method.
 374          */
 375         if (sc->arge_mac_unit == 0) {
 376                 reset_reg = RST_RESET_GE0_MAC;
 377         } else {
 378                 reset_reg = RST_RESET_GE1_MAC;
 379         }
 380
 381         /*
 382          * AR934x (and later) also needs the MDIO block reset.
 383          * XXX should methodize this!
 384          */
 385         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
 386            ar71xx_soc == AR71XX_SOC_AR9342 ||
 387            ar71xx_soc == AR71XX_SOC_AR9344) {
 388                 if (sc->arge_mac_unit == 0) {
 389                         reset_reg |= AR934X_RESET_GE0_MDIO;
 390                 } else {
 391                         reset_reg |= AR934X_RESET_GE1_MDIO;
 392                 }
 393         }
 394
 395         if (ar71xx_soc == AR71XX_SOC_QCA9556 ||
 396            ar71xx_soc == AR71XX_SOC_QCA9558) {
 397                 if (sc->arge_mac_unit == 0) {
 398                         reset_reg |= QCA955X_RESET_GE0_MDIO;
 399                 } else {
 400                         reset_reg |= QCA955X_RESET_GE1_MDIO;
 401                 }
 402         }
 403
 404         if (ar71xx_soc == AR71XX_SOC_QCA9533 ||
 405            ar71xx_soc == AR71XX_SOC_QCA9533_V2) {
 406                 if (sc->arge_mac_unit == 0) {
 407                         reset_reg |= QCA953X_RESET_GE0_MDIO;
 408                 } else {
 409                         reset_reg |= QCA953X_RESET_GE1_MDIO;
 410                 }
 411         }
 412
 413         ar71xx_device_stop(reset_reg);
 414         DELAY(100);
 415         ar71xx_device_start(reset_reg);
 416
 417         /* Step 3. Reconfigure MAC block */
 418         ARGE_WRITE(sc, AR71XX_MAC_CFG1,
 419                 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
 420                 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
 421
 422         reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
 423         reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
 424         ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
 425
 426         ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
 427 }
 428
 429 /*
 430  * These values map to the divisor values programmed into
 431  * AR71XX_MAC_MII_CFG.
 432  *
 433  * The index of each value corresponds to the divisor section
 434  * value in AR71XX_MAC_MII_CFG (ie, table[0] means '0' in
 435  * AR71XX_MAC_MII_CFG, table[1] means '1', etc.)
 436  */
 437 static const uint32_t ar71xx_mdio_div_table[] = {
 438         4, 4, 6, 8, 10, 14, 20, 28,
 439 };
 440
 441 static const uint32_t ar7240_mdio_div_table[] = {
 442         2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
 443 };
 444
 445 static const uint32_t ar933x_mdio_div_table[] = {
 446         4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
 447 };
 448
 449 /*
 450  * Lookup the divisor to use based on the given frequency.
 451  *
 452  * Returns the divisor to use, or -ve on error.
 453  */
 454 static int
 455 arge_mdio_get_divider(struct arge_softc *sc, unsigned long mdio_clock)
 456 {
 457         unsigned long ref_clock, t;
 458         const uint32_t *table;
 459         int ndivs;
 460         int i;
 461
 462         /*
 463          * This is the base MDIO frequency on the SoC.
 464          * The dividers .. well, divide. Duh.
 465          */
 466         ref_clock = ar71xx_mdio_freq();
 467
 468         /*
 469          * If either clock is undefined, just tell the
 470          * caller to fall through to the defaults.
 471          */
 472         if (ref_clock == 0 || mdio_clock == 0)
 473                 return (-EINVAL);
 474
 475         /*
 476          * Pick the correct table!
 477          */
 478         switch (ar71xx_soc) {
 479         case AR71XX_SOC_AR9330:
 480         case AR71XX_SOC_AR9331:
 481         case AR71XX_SOC_AR9341:
 482         case AR71XX_SOC_AR9342:
 483         case AR71XX_SOC_AR9344:
 484         case AR71XX_SOC_QCA9533:
 485         case AR71XX_SOC_QCA9533_V2:
 486         case AR71XX_SOC_QCA9556:
 487         case AR71XX_SOC_QCA9558:
 488                 table = ar933x_mdio_div_table;
 489                 ndivs = nitems(ar933x_mdio_div_table);
 490                 break;
 491
 492         case AR71XX_SOC_AR7240:
 493         case AR71XX_SOC_AR7241:
 494         case AR71XX_SOC_AR7242:
 495                 table = ar7240_mdio_div_table;
 496                 ndivs = nitems(ar7240_mdio_div_table);
 497                 break;
 498
 499         default:
 500                 table = ar71xx_mdio_div_table;
 501                 ndivs = nitems(ar71xx_mdio_div_table);
 502         }
 503
 504         /*
 505          * Now, walk through the list and find the first divisor
 506          * that falls under the target MDIO frequency.
 507          *
 508          * The divisors go up, but the corresponding frequencies
 509          * are actually decreasing.
 510          */
 511         for (i = 0; i < ndivs; i++) {
 512                 t = ref_clock / table[i];
 513                 if (t <= mdio_clock) {
 514                         return (i);
 515                 }
 516         }
 517
 518         ARGEDEBUG(sc, ARGE_DBG_RESET,
 519             "No divider found; MDIO=%lu Hz; target=%lu Hz\n",
 520                 ref_clock, mdio_clock);
 521         return (-ENOENT);
 522 }
 523
 524 /*
 525  * Fetch the MDIO bus clock rate.
 526  *
 527  * For now, the default is DIV_28 for everything
 528  * bar AR934x, which will be DIV_58.
 529  *
 530  * It will definitely need updating to take into account
 531  * the MDIO bus core clock rate and the target clock
 532  * rate for the chip.
 533  */
 534 static uint32_t
 535 arge_fetch_mdiobus_clock_rate(struct arge_softc *sc)
 536 {
 537         int mdio_freq, div;
 538
 539         /*
 540          * Is the MDIO frequency defined? If so, find a divisor that
 541          * makes reasonable sense.  Don't overshoot the frequency.
 542          */
 543         if (resource_int_value(device_get_name(sc->arge_dev),
 544             device_get_unit(sc->arge_dev),
 545             "mdio_freq",
 546             &mdio_freq) == 0) {
 547                 sc->arge_mdiofreq = mdio_freq;
 548                 div = arge_mdio_get_divider(sc, sc->arge_mdiofreq);
 549                 if (bootverbose)
 550                         device_printf(sc->arge_dev,
 551                             "%s: mdio ref freq=%llu Hz, target freq=%llu Hz,"
 552                             " divisor index=%d\n",
 553                             __func__,
 554                             (unsigned long long) ar71xx_mdio_freq(),
 555                             (unsigned long long) mdio_freq,
 556                             div);
 557                 if (div >= 0)
 558                         return (div);
 559         }
 560
 561         /*
 562          * Default value(s).
 563          *
 564          * XXX obviously these need .. fixing.
 565          *
 566          * From Linux/OpenWRT:
 567          *
 568          * + 7240? DIV_6
 569          * + Builtin-switch port and not 934x? DIV_10
 570          * + Not built-in switch port and 934x? DIV_58
 571          * + .. else DIV_28.
 572          */
 573         switch (ar71xx_soc) {
 574         case AR71XX_SOC_AR9341:
 575         case AR71XX_SOC_AR9342:
 576         case AR71XX_SOC_AR9344:
 577         case AR71XX_SOC_QCA9533:
 578         case AR71XX_SOC_QCA9533_V2:
 579         case AR71XX_SOC_QCA9556:
 580         case AR71XX_SOC_QCA9558:
 581                 return (MAC_MII_CFG_CLOCK_DIV_58);
 582                 break;
 583         default:
 584                 return (MAC_MII_CFG_CLOCK_DIV_28);
 585         }
 586 }
 587
 588 static void
 589 arge_reset_miibus(struct arge_softc *sc)
 590 {
 591         uint32_t mdio_div;
 592
 593         mdio_div = arge_fetch_mdiobus_clock_rate(sc);
 594
 595         /*
 596          * XXX AR934x and later; should we be also resetting the
 597          * MDIO block(s) using the reset register block?
 598          */
 599
 600         /* Reset MII bus; program in the default divisor */
 601         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_div);
 602         DELAY(100);
 603         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_div);
 604         DELAY(100);
 605 }
 606
 607 static void
 608 arge_fetch_pll_config(struct arge_softc *sc)
 609 {
 610         long int val;
 611
 612         if (resource_long_value(device_get_name(sc->arge_dev),
 613             device_get_unit(sc->arge_dev),
 614             "pll_10", &val) == 0) {
 615                 sc->arge_pllcfg.pll_10 = val;
 616                 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
 617                     __func__, (int) val);
 618         }
 619         if (resource_long_value(device_get_name(sc->arge_dev),
 620             device_get_unit(sc->arge_dev),
 621             "pll_100", &val) == 0) {
 622                 sc->arge_pllcfg.pll_100 = val;
 623                 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
 624                     __func__, (int) val);
 625         }
 626         if (resource_long_value(device_get_name(sc->arge_dev),
 627             device_get_unit(sc->arge_dev),
 628             "pll_1000", &val) == 0) {
 629                 sc->arge_pllcfg.pll_1000 = val;
 630                 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
 631                     __func__, (int) val);
 632         }
 633 }
 634
 635 static int
 636 arge_attach(device_t dev)
 637 {
 638         struct ifnet            *ifp;
 639         struct arge_softc       *sc;
 640         int                     error = 0, rid, i;
 641         uint32_t                hint;
 642         long                    eeprom_mac_addr = 0;
 643         int                     miicfg = 0;
 644         int                     readascii = 0;
 645         int                     local_mac = 0;
 646         uint8_t                 local_macaddr[ETHER_ADDR_LEN];
 647         char *                  local_macstr;
 648         char                    devid_str[32];
 649         int                     count;
 650
 651         sc = device_get_softc(dev);
 652         sc->arge_dev = dev;
 653         sc->arge_mac_unit = device_get_unit(dev);
 654
 655         /*
 656          * See if there's a "board" MAC address hint available for
 657          * this particular device.
 658          *
 659          * This is in the environment - it'd be nice to use the resource_*()
 660          * routines, but at the moment the system is booting, the resource hints
 661          * are set to the 'static' map so they're not pulling from kenv.
 662          */
 663         snprintf(devid_str, 32, "hint.%s.%d.macaddr",
 664             device_get_name(dev),
 665             device_get_unit(dev));
 666         if ((local_macstr = kern_getenv(devid_str)) != NULL) {
 667                 uint32_t tmpmac[ETHER_ADDR_LEN];
 668
 669                 /* Have a MAC address; should use it */
 670                 device_printf(dev, "Overriding MAC address from environment: '%s'\n",
 671                     local_macstr);
 672
 673                 /* Extract out the MAC address */
 674                 /* XXX this should all be a generic method */
 675                 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
 676                     &tmpmac[0], &tmpmac[1],
 677                     &tmpmac[2], &tmpmac[3],
 678                     &tmpmac[4], &tmpmac[5]);
 679                 if (count == 6) {
 680                         /* Valid! */
 681                         local_mac = 1;
 682                         for (i = 0; i < ETHER_ADDR_LEN; i++)
 683                                 local_macaddr[i] = tmpmac[i];
 684                 }
 685                 /* Done! */
 686                 freeenv(local_macstr);
 687                 local_macstr = NULL;
 688         }
 689
 690         /*
 691          * Hardware workarounds.
 692          */
 693         switch (ar71xx_soc) {
 694         case AR71XX_SOC_AR9330:
 695         case AR71XX_SOC_AR9331:
 696         case AR71XX_SOC_AR9341:
 697         case AR71XX_SOC_AR9342:
 698         case AR71XX_SOC_AR9344:
 699         case AR71XX_SOC_QCA9533:
 700         case AR71XX_SOC_QCA9533_V2:
 701         case AR71XX_SOC_QCA9556:
 702         case AR71XX_SOC_QCA9558:
 703                 /* Arbitrary alignment */
 704                 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE;
 705                 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE;
 706                 break;
 707         default:
 708                 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE;
 709                 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE;
 710                 break;
 711         }
 712
 713         /*
 714          * Some units (eg the TP-Link WR-1043ND) do not have a convenient
 715          * EEPROM location to read the ethernet MAC address from.
 716          * OpenWRT simply snaffles it from a fixed location.
 717          *
 718          * Since multiple units seem to use this feature, include
 719          * a method of setting the MAC address based on an flash location
 720          * in CPU address space.
 721          *
 722          * Some vendors have decided to store the mac address as a literal
 723          * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of
 724          * an array of numbers.  Expose a hint to turn on this conversion
 725          * feature via strtol()
 726          */
 727          if (local_mac == 0 && resource_long_value(device_get_name(dev),
 728              device_get_unit(dev), "eeprommac", &eeprom_mac_addr) == 0) {
 729                 local_mac = 1;
 730                 int i;
 731                 const char *mac =
 732                     (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
 733                 device_printf(dev, "Overriding MAC from EEPROM\n");
 734                 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 735                         "readascii", &readascii) == 0) {
 736                         device_printf(dev, "Vendor stores MAC in ASCII format\n");
 737                         for (i = 0; i < 6; i++) {
 738                                 local_macaddr[i] = strtol(&(mac[i*3]), NULL, 16);
 739                         }
 740                 } else {
 741                         for (i = 0; i < 6; i++) {
 742                                 local_macaddr[i] = mac[i];
 743                         }
 744                 }
 745         }
 746
 747         KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
 748             ("if_arge: Only MAC0 and MAC1 supported"));
 749
 750         /*
 751          * Fetch the PLL configuration.
 752          */
 753         arge_fetch_pll_config(sc);
 754
 755         /*
 756          * Get the MII configuration, if applicable.
 757          */
 758         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 759             "miimode", &miicfg) == 0) {
 760                 /* XXX bounds check? */
 761                 device_printf(dev, "%s: overriding MII mode to '%s'\n",
 762                     __func__, arge_miicfg_str[miicfg]);
 763                 sc->arge_miicfg = miicfg;
 764         }
 765
 766         /*
 767          *  Get which PHY of 5 available we should use for this unit
 768          */
 769         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 770             "phymask", &sc->arge_phymask) != 0) {
 771                 /*
 772                  * Use port 4 (WAN) for GE0. For any other port use
 773                  * its PHY the same as its unit number
 774                  */
 775                 if (sc->arge_mac_unit == 0)
 776                         sc->arge_phymask = (1 << 4);
 777                 else
 778                         /* Use all phys up to 4 */
 779                         sc->arge_phymask = (1 << 4) - 1;
 780
 781                 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
 782         }
 783
 784         /*
 785          * Get default/hard-coded media & duplex mode.
 786          */
 787         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 788             "media", &hint) != 0)
 789                 hint = 0;
 790
 791         if (hint == 1000)
 792                 sc->arge_media_type = IFM_1000_T;
 793         else if (hint == 100)
 794                 sc->arge_media_type = IFM_100_TX;
 795         else if (hint == 10)
 796                 sc->arge_media_type = IFM_10_T;
 797         else
 798                 sc->arge_media_type = 0;
 799
 800         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 801             "fduplex", &hint) != 0)
 802                 hint = 1;
 803
 804         if (hint)
 805                 sc->arge_duplex_mode = IFM_FDX;
 806         else
 807                 sc->arge_duplex_mode = 0;
 808
 809         mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 810             MTX_DEF);
 811         callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
 812         TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
 813
 814         /* Map control/status registers. */
 815         sc->arge_rid = 0;
 816         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 817             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
 818
 819         if (sc->arge_res == NULL) {
 820                 device_printf(dev, "couldn't map memory\n");
 821                 error = ENXIO;
 822                 goto fail;
 823         }
 824
 825         /* Allocate interrupts */
 826         rid = 0;
 827         sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 828             RF_SHAREABLE | RF_ACTIVE);
 829
 830         if (sc->arge_irq == NULL) {
 831                 device_printf(dev, "couldn't map interrupt\n");
 832                 error = ENXIO;
 833                 goto fail;
 834         }
 835
 836         /* Allocate ifnet structure. */
 837         ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
 838
 839         if (ifp == NULL) {
 840                 device_printf(dev, "couldn't allocate ifnet structure\n");
 841                 error = ENOSPC;
 842                 goto fail;
 843         }
 844
 845         ifp->if_softc = sc;
 846         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 847         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 848         ifp->if_ioctl = arge_ioctl;
 849         ifp->if_start = arge_start;
 850         ifp->if_init = arge_init;
 851         sc->arge_if_flags = ifp->if_flags;
 852
 853         /* XXX: add real size */
 854         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 855         ifp->if_snd.ifq_maxlen = ifqmaxlen;
 856         IFQ_SET_READY(&ifp->if_snd);
 857
 858         /* Tell the upper layer(s) we support long frames. */
 859         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 860
 861         ifp->if_capenable = ifp->if_capabilities;
 862 #ifdef DEVICE_POLLING
 863         ifp->if_capabilities |= IFCAP_POLLING;
 864 #endif
 865
 866         /* If there's a local mac defined, copy that in */
 867         if (local_mac == 1) {
 868                 (void) ar71xx_mac_addr_init(sc->arge_eaddr,
 869                     local_macaddr, 0, 0);
 870         } else {
 871                 /*
 872                  * No MAC address configured. Generate the random one.
 873                  */
 874                 if  (bootverbose)
 875                         device_printf(dev,
 876                             "Generating random ethernet address.\n");
 877                 (void) ar71xx_mac_addr_random_init(sc->arge_eaddr);
 878         }
 879
 880         if (arge_dma_alloc(sc) != 0) {
 881                 error = ENXIO;
 882                 goto fail;
 883         }
 884
 885         /*
 886          * Don't do this for the MDIO bus case - it's already done
 887          * as part of the MDIO bus attachment.
 888          *
 889          * XXX TODO: if we don't do this, we don't ever release the MAC
 890          * from reset and we can't use the port.  Now, if we define ARGE_MDIO
 891          * but we /don't/ define two MDIO busses, then we can't actually
 892          * use both MACs.
 893          */
 894 #if !defined(ARGE_MDIO)
 895         /* Initialize the MAC block */
 896         arge_reset_mac(sc);
 897         arge_reset_miibus(sc);
 898 #endif
 899
 900         /* Configure MII mode, just for convienence */
 901         if (sc->arge_miicfg != 0)
 902                 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
 903
 904         /*
 905          * Set all Ethernet address registers to the same initial values
 906          * set all four addresses to 66-88-aa-cc-dd-ee
 907          */
 908         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
 909             | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
 910             | sc->arge_eaddr[5]);
 911         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
 912             | sc->arge_eaddr[1]);
 913
 914         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
 915             FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
 916
 917         /*
 918          * SoC specific bits.
 919          */
 920         switch (ar71xx_soc) {
 921                 case AR71XX_SOC_AR7240:
 922                 case AR71XX_SOC_AR7241:
 923                 case AR71XX_SOC_AR7242:
 924                 case AR71XX_SOC_AR9330:
 925                 case AR71XX_SOC_AR9331:
 926                 case AR71XX_SOC_AR9341:
 927                 case AR71XX_SOC_AR9342:
 928                 case AR71XX_SOC_AR9344:
 929                 case AR71XX_SOC_QCA9533:
 930                 case AR71XX_SOC_QCA9533_V2:
 931                 case AR71XX_SOC_QCA9556:
 932                 case AR71XX_SOC_QCA9558:
 933                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
 934                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
 935                         break;
 936                 /* AR71xx, AR913x */
 937                 default:
 938                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
 939                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
 940         }
 941
 942         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
 943             FIFO_RX_FILTMATCH_DEFAULT);
 944
 945         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
 946             FIFO_RX_FILTMASK_DEFAULT);
 947
 948 #if defined(ARGE_MDIO)
 949         sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
 950 #endif
 951
 952         device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
 953             ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
 954             "null" : "set");
 955         for (i = 0; i < ARGE_NPHY; i++) {
 956                 if (((1 << i) & sc->arge_phymask) != 0) {
 957                         error = mii_attach(sc->arge_miiproxy != NULL ?
 958                             sc->arge_miiproxy : sc->arge_dev,
 959                             &sc->arge_miibus, sc->arge_ifp,
 960                             arge_ifmedia_upd, arge_ifmedia_sts,
 961                             BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
 962                         if (error != 0) {
 963                                 device_printf(sc->arge_dev, "unable to attach"
 964                                     " PHY %d: %d\n", i, error);
 965                                 goto fail;
 966                         }
 967                 }
 968         }
 969
 970         if (sc->arge_miibus == NULL) {
 971                 /* no PHY, so use hard-coded values */
 972                 ifmedia_init(&sc->arge_ifmedia, 0,
 973                     arge_multiphy_mediachange,
 974                     arge_multiphy_mediastatus);
 975                 ifmedia_add(&sc->arge_ifmedia,
 976                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode,
 977                     0, NULL);
 978                 ifmedia_set(&sc->arge_ifmedia,
 979                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode);
 980                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
 981         }
 982
 983         /* Call MI attach routine. */
 984         ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
 985
 986         /* Hook interrupt last to avoid having to lock softc */
 987         error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
 988             arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
 989
 990         if (error) {
 991                 device_printf(sc->arge_dev, "couldn't set up irq\n");
 992                 ether_ifdetach(sc->arge_ifp);
 993                 goto fail;
 994         }
 995
 996         /* setup sysctl variables */
 997         arge_attach_sysctl(sc->arge_dev);
 998
 999 fail:
1000         if (error)
1001                 arge_detach(dev);
1002
1003         return (error);
1004 }
1005
1006 static int
1007 arge_detach(device_t dev)
1008 {
1009         struct arge_softc       *sc = device_get_softc(dev);
1010         struct ifnet            *ifp = sc->arge_ifp;
1011
1012         KASSERT(mtx_initialized(&sc->arge_mtx),
1013             ("arge mutex not initialized"));
1014
1015         /* These should only be active if attach succeeded */
1016         if (device_is_attached(dev)) {
1017                 ARGE_LOCK(sc);
1018                 sc->arge_detach = 1;
1019 #ifdef DEVICE_POLLING
1020                 if (ifp->if_capenable & IFCAP_POLLING)
1021                         ether_poll_deregister(ifp);
1022 #endif
1023
1024                 arge_stop(sc);
1025                 ARGE_UNLOCK(sc);
1026                 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
1027                 ether_ifdetach(ifp);
1028         }
1029
1030         if (sc->arge_miibus)
1031                 device_delete_child(dev, sc->arge_miibus);
1032
1033         if (sc->arge_miiproxy)
1034                 device_delete_child(dev, sc->arge_miiproxy);
1035
1036         bus_generic_detach(dev);
1037
1038         if (sc->arge_intrhand)
1039                 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
1040
1041         if (sc->arge_res)
1042                 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
1043                     sc->arge_res);
1044
1045         if (ifp)
1046                 if_free(ifp);
1047
1048         arge_dma_free(sc);
1049
1050         mtx_destroy(&sc->arge_mtx);
1051
1052         return (0);
1053
1054 }
1055
1056 static int
1057 arge_suspend(device_t dev)
1058 {
1059
1060         panic("%s", __func__);
1061         return 0;
1062 }
1063
1064 static int
1065 arge_resume(device_t dev)
1066 {
1067
1068         panic("%s", __func__);
1069         return 0;
1070 }
1071
1072 static int
1073 arge_shutdown(device_t dev)
1074 {
1075         struct arge_softc       *sc;
1076
1077         sc = device_get_softc(dev);
1078
1079         ARGE_LOCK(sc);
1080         arge_stop(sc);
1081         ARGE_UNLOCK(sc);
1082
1083         return (0);
1084 }
1085
1086 static void
1087 arge_hinted_child(device_t bus, const char *dname, int dunit)
1088 {
1089         BUS_ADD_CHILD(bus, 0, dname, dunit);
1090         device_printf(bus, "hinted child %s%d\n", dname, dunit);
1091 }
1092
1093 static int
1094 arge_mdio_busy(struct arge_softc *sc)
1095 {
1096         int i,result;
1097
1098         for (i = 0; i < ARGE_MII_TIMEOUT; i++) {
1099                 DELAY(5);
1100                 ARGE_MDIO_BARRIER_READ(sc);
1101                 result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR);
1102                 if (! result)
1103                         return (0);
1104                 DELAY(5);
1105         }
1106         return (-1);
1107 }
1108
1109 static int
1110 arge_miibus_readreg(device_t dev, int phy, int reg)
1111 {
1112         struct arge_softc * sc = device_get_softc(dev);
1113         int result;
1114         uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
1115             | (reg & MAC_MII_REG_MASK);
1116
1117         mtx_lock(&miibus_mtx);
1118         ARGE_MDIO_BARRIER_RW(sc);
1119         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
1120         ARGE_MDIO_BARRIER_WRITE(sc);
1121         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1122         ARGE_MDIO_BARRIER_WRITE(sc);
1123         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
1124
1125         if (arge_mdio_busy(sc) != 0) {
1126                 mtx_unlock(&miibus_mtx);
1127                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
1128                 /* XXX: return ERRNO istead? */
1129                 return (-1);
1130         }
1131
1132         ARGE_MDIO_BARRIER_READ(sc);
1133         result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
1134         ARGE_MDIO_BARRIER_RW(sc);
1135         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
1136         mtx_unlock(&miibus_mtx);
1137
1138         ARGEDEBUG(sc, ARGE_DBG_MII,
1139             "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
1140             __func__, phy, reg, addr, result);
1141
1142         return (result);
1143 }
1144
1145 static int
1146 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
1147 {
1148         struct arge_softc * sc = device_get_softc(dev);
1149         uint32_t addr =
1150             (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
1151
1152         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
1153             phy, reg, data);
1154
1155         mtx_lock(&miibus_mtx);
1156         ARGE_MDIO_BARRIER_RW(sc);
1157         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1158         ARGE_MDIO_BARRIER_WRITE(sc);
1159         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
1160         ARGE_MDIO_BARRIER_WRITE(sc);
1161
1162         if (arge_mdio_busy(sc) != 0) {
1163                 mtx_unlock(&miibus_mtx);
1164                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
1165                 /* XXX: return ERRNO istead? */
1166                 return (-1);
1167         }
1168
1169         mtx_unlock(&miibus_mtx);
1170         return (0);
1171 }
1172
1173 static void
1174 arge_miibus_statchg(device_t dev)
1175 {
1176         struct arge_softc       *sc;
1177
1178         sc = device_get_softc(dev);
1179         taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
1180 }
1181
1182 static void
1183 arge_link_task(void *arg, int pending)
1184 {
1185         struct arge_softc       *sc;
1186         sc = (struct arge_softc *)arg;
1187
1188         ARGE_LOCK(sc);
1189         arge_update_link_locked(sc);
1190         ARGE_UNLOCK(sc);
1191 }
1192
1193 static void
1194 arge_update_link_locked(struct arge_softc *sc)
1195 {
1196         struct mii_data         *mii;
1197         struct ifnet            *ifp;
1198         uint32_t                media, duplex;
1199
1200         mii = device_get_softc(sc->arge_miibus);
1201         ifp = sc->arge_ifp;
1202         if (mii == NULL || ifp == NULL ||
1203             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1204                 return;
1205         }
1206
1207         /*
1208          * If we have a static media type configured, then
1209          * use that.  Some PHY configurations (eg QCA955x -> AR8327)
1210          * use a static speed/duplex between the SoC and switch,
1211          * even though the front-facing PHY speed changes.
1212          */
1213         if (sc->arge_media_type != 0) {
1214                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: fixed; media=%d, duplex=%d\n",
1215                     __func__,
1216                     sc->arge_media_type,
1217                     sc->arge_duplex_mode);
1218                 if (mii->mii_media_status & IFM_ACTIVE) {
1219                         sc->arge_link_status = 1;
1220                 } else {
1221                         sc->arge_link_status = 0;
1222                 }
1223                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
1224         }
1225
1226         if (mii->mii_media_status & IFM_ACTIVE) {
1227
1228                 media = IFM_SUBTYPE(mii->mii_media_active);
1229                 if (media != IFM_NONE) {
1230                         sc->arge_link_status = 1;
1231                         duplex = mii->mii_media_active & IFM_GMASK;
1232                         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
1233                             __func__,
1234                             media,
1235                             duplex);
1236                         arge_set_pll(sc, media, duplex);
1237                 }
1238         } else {
1239                 sc->arge_link_status = 0;
1240         }
1241 }
1242
1243 static void
1244 arge_set_pll(struct arge_softc *sc, int media, int duplex)
1245 {
1246         uint32_t                cfg, ifcontrol, rx_filtmask;
1247         uint32_t                fifo_tx, pll;
1248         int if_speed;
1249
1250         /*
1251          * XXX Verify - is this valid for all chips?
1252          * QCA955x (and likely some of the earlier chips!) define
1253          * this as nibble mode and byte mode, and those have to do
1254          * with the interface type (MII/SMII versus GMII/RGMII.)
1255          */
1256         ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
1257             duplex == IFM_FDX ? "full" : "half");
1258         cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
1259         cfg &= ~(MAC_CFG2_IFACE_MODE_1000
1260             | MAC_CFG2_IFACE_MODE_10_100
1261             | MAC_CFG2_FULL_DUPLEX);
1262
1263         if (duplex == IFM_FDX)
1264                 cfg |= MAC_CFG2_FULL_DUPLEX;
1265
1266         ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
1267         ifcontrol &= ~MAC_IFCONTROL_SPEED;
1268         rx_filtmask =
1269             ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
1270         rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
1271
1272         switch(media) {
1273         case IFM_10_T:
1274                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1275                 if_speed = 10;
1276                 break;
1277         case IFM_100_TX:
1278                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1279                 ifcontrol |= MAC_IFCONTROL_SPEED;
1280                 if_speed = 100;
1281                 break;
1282         case IFM_1000_T:
1283         case IFM_1000_SX:
1284                 cfg |= MAC_CFG2_IFACE_MODE_1000;
1285                 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
1286                 if_speed = 1000;
1287                 break;
1288         default:
1289                 if_speed = 100;
1290                 device_printf(sc->arge_dev,
1291                     "Unknown media %d\n", media);
1292         }
1293
1294         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
1295
1296         switch (ar71xx_soc) {
1297                 case AR71XX_SOC_AR7240:
1298                 case AR71XX_SOC_AR7241:
1299                 case AR71XX_SOC_AR7242:
1300                 case AR71XX_SOC_AR9330:
1301                 case AR71XX_SOC_AR9331:
1302                 case AR71XX_SOC_AR9341:
1303                 case AR71XX_SOC_AR9342:
1304                 case AR71XX_SOC_AR9344:
1305                 case AR71XX_SOC_QCA9533:
1306                 case AR71XX_SOC_QCA9533_V2:
1307                 case AR71XX_SOC_QCA9556:
1308                 case AR71XX_SOC_QCA9558:
1309                         fifo_tx = 0x01f00140;
1310                         break;
1311                 case AR71XX_SOC_AR9130:
1312                 case AR71XX_SOC_AR9132:
1313                         fifo_tx = 0x00780fff;
1314                         break;
1315                 /* AR71xx */
1316                 default:
1317                         fifo_tx = 0x008001ff;
1318         }
1319
1320         ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
1321         ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
1322         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1323             rx_filtmask);
1324         ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
1325
1326         /* fetch PLL registers */
1327         pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
1328         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
1329
1330         /* Override if required by platform data */
1331         if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
1332                 pll = sc->arge_pllcfg.pll_10;
1333         else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
1334                 pll = sc->arge_pllcfg.pll_100;
1335         else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
1336                 pll = sc->arge_pllcfg.pll_1000;
1337         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
1338
1339         /* XXX ensure pll != 0 */
1340         ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
1341
1342         /* set MII registers */
1343         /*
1344          * This was introduced to match what the Linux ag71xx ethernet
1345          * driver does.  For the AR71xx case, it does set the port
1346          * MII speed.  However, if this is done, non-gigabit speeds
1347          * are not at all reliable when speaking via RGMII through
1348          * 'bridge' PHY port that's pretending to be a local PHY.
1349          *
1350          * Until that gets root caused, and until an AR71xx + normal
1351          * PHY board is tested, leave this disabled.
1352          */
1353 #if 0
1354         ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
1355 #endif
1356 }
1357
1358
1359 static void
1360 arge_reset_dma(struct arge_softc *sc)
1361 {
1362
1363         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: called\n", __func__);
1364
1365         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
1366         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
1367
1368         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
1369         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
1370
1371         /* Clear all possible RX interrupts */
1372         while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
1373                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1374
1375         /*
1376          * Clear all possible TX interrupts
1377          */
1378         while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
1379                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1380
1381         /*
1382          * Now Rx/Tx errors
1383          */
1384         ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
1385             DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
1386         ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
1387             DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
1388
1389         /*
1390          * Force a DDR flush so any pending data is properly
1391          * flushed to RAM before underlying buffers are freed.
1392          */
1393         arge_flush_ddr(sc);
1394 }
1395
1396 static void
1397 arge_init(void *xsc)
1398 {
1399         struct arge_softc        *sc = xsc;
1400
1401         ARGE_LOCK(sc);
1402         arge_init_locked(sc);
1403         ARGE_UNLOCK(sc);
1404 }
1405
1406 static void
1407 arge_init_locked(struct arge_softc *sc)
1408 {
1409         struct ifnet            *ifp = sc->arge_ifp;
1410         struct mii_data         *mii;
1411
1412         ARGE_LOCK_ASSERT(sc);
1413
1414         if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1415                 return;
1416
1417         /* Init circular RX list. */
1418         if (arge_rx_ring_init(sc) != 0) {
1419                 device_printf(sc->arge_dev,
1420                     "initialization failed: no memory for rx buffers\n");
1421                 arge_stop(sc);
1422                 return;
1423         }
1424
1425         /* Init tx descriptors. */
1426         arge_tx_ring_init(sc);
1427
1428         arge_reset_dma(sc);
1429
1430         if (sc->arge_miibus) {
1431                 mii = device_get_softc(sc->arge_miibus);
1432                 mii_mediachg(mii);
1433         }
1434         else {
1435                 /*
1436                  * Sun always shines over multiPHY interface
1437                  */
1438                 sc->arge_link_status = 1;
1439         }
1440
1441         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1442         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1443
1444         if (sc->arge_miibus) {
1445                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1446                 arge_update_link_locked(sc);
1447         }
1448
1449         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1450         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1451
1452         /* Start listening */
1453         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1454
1455         /* Enable interrupts */
1456         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1457 }
1458
1459 /*
1460  * Return whether the mbuf chain is correctly aligned
1461  * for the arge TX engine.
1462  *
1463  * All the MACs have a length requirement: any non-final
1464  * fragment (ie, descriptor with MORE bit set) needs to have
1465  * a length divisible by 4.
1466  *
1467  * The AR71xx, AR913x require the start address also be
1468  * DWORD aligned.  The later MACs don't.
1469  */
1470 static int
1471 arge_mbuf_chain_is_tx_aligned(struct arge_softc *sc, struct mbuf *m0)
1472 {
1473         struct mbuf *m;
1474
1475         for (m = m0; m != NULL; m = m->m_next) {
1476                 /*
1477                  * Only do this for chips that require it.
1478                  */
1479                 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1480                     (mtod(m, intptr_t) & 3) != 0) {
1481                         sc->stats.tx_pkts_unaligned_start++;
1482                         return 0;
1483                 }
1484
1485                 /*
1486                  * All chips have this requirement for length.
1487                  */
1488                 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) {
1489                         sc->stats.tx_pkts_unaligned_len++;
1490                         return 0;
1491                 }
1492         }
1493         return 1;
1494 }
1495
1496 /*
1497  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1498  * pointers to the fragment pointers.
1499  */
1500 static int
1501 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
1502 {
1503         struct arge_txdesc      *txd;
1504         struct arge_desc        *desc, *prev_desc;
1505         bus_dma_segment_t       txsegs[ARGE_MAXFRAGS];
1506         int                     error, i, nsegs, prod, prev_prod;
1507         struct mbuf             *m;
1508
1509         ARGE_LOCK_ASSERT(sc);
1510
1511         /*
1512          * Fix mbuf chain based on hardware alignment constraints.
1513          */
1514         m = *m_head;
1515         if (! arge_mbuf_chain_is_tx_aligned(sc, m)) {
1516                 sc->stats.tx_pkts_unaligned++;
1517                 m = m_defrag(*m_head, M_NOWAIT);
1518                 if (m == NULL) {
1519                         *m_head = NULL;
1520                         return (ENOBUFS);
1521                 }
1522                 *m_head = m;
1523         } else
1524                 sc->stats.tx_pkts_aligned++;
1525
1526         prod = sc->arge_cdata.arge_tx_prod;
1527         txd = &sc->arge_cdata.arge_txdesc[prod];
1528         error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
1529             txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1530
1531         if (error == EFBIG) {
1532                 panic("EFBIG");
1533         } else if (error != 0)
1534                 return (error);
1535
1536         if (nsegs == 0) {
1537                 m_freem(*m_head);
1538                 *m_head = NULL;
1539                 return (EIO);
1540         }
1541
1542         /* Check number of available descriptors. */
1543         if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 2)) {
1544                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1545                 sc->stats.tx_pkts_nosegs++;
1546                 return (ENOBUFS);
1547         }
1548
1549         txd->tx_m = *m_head;
1550         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1551             BUS_DMASYNC_PREWRITE);
1552
1553         /*
1554          * Make a list of descriptors for this packet. DMA controller will
1555          * walk through it while arge_link is not zero.
1556          *
1557          * Since we're in a endless circular buffer, ensure that
1558          * the first descriptor in a multi-descriptor ring is always
1559          * set to EMPTY, then un-do it when we're done populating.
1560          */
1561         prev_prod = prod;
1562         desc = prev_desc = NULL;
1563         for (i = 0; i < nsegs; i++) {
1564                 uint32_t tmp;
1565
1566                 desc = &sc->arge_rdata.arge_tx_ring[prod];
1567
1568                 /*
1569                  * Set DESC_EMPTY so the hardware (hopefully) stops at this
1570                  * point.  We don't want it to start transmitting descriptors
1571                  * before we've finished fleshing this out.
1572                  */
1573                 tmp = ARGE_DMASIZE(txsegs[i].ds_len);
1574                 if (i == 0)
1575                         tmp |= ARGE_DESC_EMPTY;
1576                 desc->packet_ctrl = tmp;
1577
1578                 /* XXX Note: only relevant for older MACs; but check length! */
1579                 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1580                     (txsegs[i].ds_addr & 3))
1581                         panic("TX packet address unaligned\n");
1582
1583                 desc->packet_addr = txsegs[i].ds_addr;
1584
1585                 /* link with previous descriptor */
1586                 if (prev_desc)
1587                         prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1588
1589                 sc->arge_cdata.arge_tx_cnt++;
1590                 prev_desc = desc;
1591                 ARGE_INC(prod, ARGE_TX_RING_COUNT);
1592         }
1593
1594         /* Update producer index. */
1595         sc->arge_cdata.arge_tx_prod = prod;
1596
1597         /*
1598          * The descriptors are updated, so enable the first one.
1599          */
1600         desc = &sc->arge_rdata.arge_tx_ring[prev_prod];
1601         desc->packet_ctrl &= ~ ARGE_DESC_EMPTY;
1602
1603         /* Sync descriptors. */
1604         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1605             sc->arge_cdata.arge_tx_ring_map,
1606             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1607
1608         /* Flush writes */
1609         ARGE_BARRIER_WRITE(sc);
1610
1611         /* Start transmitting */
1612         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
1613             __func__);
1614         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1615         return (0);
1616 }
1617
1618 static void
1619 arge_start(struct ifnet *ifp)
1620 {
1621         struct arge_softc        *sc;
1622
1623         sc = ifp->if_softc;
1624
1625         ARGE_LOCK(sc);
1626         arge_start_locked(ifp);
1627         ARGE_UNLOCK(sc);
1628 }
1629
1630 static void
1631 arge_start_locked(struct ifnet *ifp)
1632 {
1633         struct arge_softc       *sc;
1634         struct mbuf             *m_head;
1635         int                     enq = 0;
1636
1637         sc = ifp->if_softc;
1638
1639         ARGE_LOCK_ASSERT(sc);
1640
1641         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1642
1643         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1644             IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1645                 return;
1646
1647         /*
1648          * Before we go any further, check whether we're already full.
1649          * The below check errors out immediately if the ring is full
1650          * and never gets a chance to set this flag. Although it's
1651          * likely never needed, this at least avoids an unexpected
1652          * situation.
1653          */
1654         if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1655                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1656                 ARGEDEBUG(sc, ARGE_DBG_ERR,
1657                     "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1658                     __func__, sc->arge_cdata.arge_tx_cnt,
1659                     ARGE_TX_RING_COUNT - 2);
1660                 return;
1661         }
1662
1663         arge_flush_ddr(sc);
1664
1665         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1666             sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1667                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1668                 if (m_head == NULL)
1669                         break;
1670
1671
1672                 /*
1673                  * Pack the data into the transmit ring.
1674                  */
1675                 if (arge_encap(sc, &m_head)) {
1676                         if (m_head == NULL)
1677                                 break;
1678                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1679                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1680                         break;
1681                 }
1682
1683                 enq++;
1684                 /*
1685                  * If there's a BPF listener, bounce a copy of this frame
1686                  * to him.
1687                  */
1688                 ETHER_BPF_MTAP(ifp, m_head);
1689         }
1690         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
1691             __func__, enq);
1692 }
1693
1694 static void
1695 arge_stop(struct arge_softc *sc)
1696 {
1697         struct ifnet        *ifp;
1698
1699         ARGE_LOCK_ASSERT(sc);
1700
1701         ifp = sc->arge_ifp;
1702         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1703         if (sc->arge_miibus)
1704                 callout_stop(&sc->arge_stat_callout);
1705
1706         /* mask out interrupts */
1707         ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1708
1709         arge_reset_dma(sc);
1710
1711         /* Flush FIFO and free any existing mbufs */
1712         arge_flush_ddr(sc);
1713         arge_rx_ring_free(sc);
1714         arge_tx_ring_free(sc);
1715 }
1716
1717
1718 static int
1719 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1720 {
1721         struct arge_softc               *sc = ifp->if_softc;
1722         struct ifreq            *ifr = (struct ifreq *) data;
1723         struct mii_data         *mii;
1724         int                     error;
1725 #ifdef DEVICE_POLLING
1726         int                     mask;
1727 #endif
1728
1729         switch (command) {
1730         case SIOCSIFFLAGS:
1731                 ARGE_LOCK(sc);
1732                 if ((ifp->if_flags & IFF_UP) != 0) {
1733                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1734                                 if (((ifp->if_flags ^ sc->arge_if_flags)
1735                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1736                                         /* XXX: handle promisc & multi flags */
1737                                 }
1738
1739                         } else {
1740                                 if (!sc->arge_detach)
1741                                         arge_init_locked(sc);
1742                         }
1743                 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1744                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1745                         arge_stop(sc);
1746                 }
1747                 sc->arge_if_flags = ifp->if_flags;
1748                 ARGE_UNLOCK(sc);
1749                 error = 0;
1750                 break;
1751         case SIOCADDMULTI:
1752         case SIOCDELMULTI:
1753                 /* XXX: implement SIOCDELMULTI */
1754                 error = 0;
1755                 break;
1756         case SIOCGIFMEDIA:
1757         case SIOCSIFMEDIA:
1758                 if (sc->arge_miibus) {
1759                         mii = device_get_softc(sc->arge_miibus);
1760                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1761                             command);
1762                 }
1763                 else
1764                         error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
1765                             command);
1766                 break;
1767         case SIOCSIFCAP:
1768                 /* XXX: Check other capabilities */
1769 #ifdef DEVICE_POLLING
1770                 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1771                 if (mask & IFCAP_POLLING) {
1772                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
1773                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1774                                 error = ether_poll_register(arge_poll, ifp);
1775                                 if (error)
1776                                         return error;
1777                                 ARGE_LOCK(sc);
1778                                 ifp->if_capenable |= IFCAP_POLLING;
1779                                 ARGE_UNLOCK(sc);
1780                         } else {
1781                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1782                                 error = ether_poll_deregister(ifp);
1783                                 ARGE_LOCK(sc);
1784                                 ifp->if_capenable &= ~IFCAP_POLLING;
1785                                 ARGE_UNLOCK(sc);
1786                         }
1787                 }
1788                 error = 0;
1789                 break;
1790 #endif
1791         default:
1792                 error = ether_ioctl(ifp, command, data);
1793                 break;
1794         }
1795
1796         return (error);
1797 }
1798
1799 /*
1800  * Set media options.
1801  */
1802 static int
1803 arge_ifmedia_upd(struct ifnet *ifp)
1804 {
1805         struct arge_softc               *sc;
1806         struct mii_data         *mii;
1807         struct mii_softc        *miisc;
1808         int                     error;
1809
1810         sc = ifp->if_softc;
1811         ARGE_LOCK(sc);
1812         mii = device_get_softc(sc->arge_miibus);
1813         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1814                 PHY_RESET(miisc);
1815         error = mii_mediachg(mii);
1816         ARGE_UNLOCK(sc);
1817
1818         return (error);
1819 }
1820
1821 /*
1822  * Report current media status.
1823  */
1824 static void
1825 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1826 {
1827         struct arge_softc               *sc = ifp->if_softc;
1828         struct mii_data         *mii;
1829
1830         mii = device_get_softc(sc->arge_miibus);
1831         ARGE_LOCK(sc);
1832         mii_pollstat(mii);
1833         ifmr->ifm_active = mii->mii_media_active;
1834         ifmr->ifm_status = mii->mii_media_status;
1835         ARGE_UNLOCK(sc);
1836 }
1837
1838 struct arge_dmamap_arg {
1839         bus_addr_t      arge_busaddr;
1840 };
1841
1842 static void
1843 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1844 {
1845         struct arge_dmamap_arg  *ctx;
1846
1847         if (error != 0)
1848                 return;
1849         ctx = arg;
1850         ctx->arge_busaddr = segs[0].ds_addr;
1851 }
1852
1853 static int
1854 arge_dma_alloc(struct arge_softc *sc)
1855 {
1856         struct arge_dmamap_arg  ctx;
1857         struct arge_txdesc      *txd;
1858         struct arge_rxdesc      *rxd;
1859         int                     error, i;
1860         int                     arge_tx_align, arge_rx_align;
1861
1862         /* Assume 4 byte alignment by default */
1863         arge_tx_align = 4;
1864         arge_rx_align = 4;
1865
1866         if (sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE)
1867                 arge_tx_align = 1;
1868         if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
1869                 arge_rx_align = 1;
1870
1871         /* Create parent DMA tag. */
1872         error = bus_dma_tag_create(
1873             bus_get_dma_tag(sc->arge_dev),      /* parent */
1874             1, 0,                       /* alignment, boundary */
1875             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1876             BUS_SPACE_MAXADDR,          /* highaddr */
1877             NULL, NULL,                 /* filter, filterarg */
1878             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1879             0,                          /* nsegments */
1880             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1881             0,                          /* flags */
1882             NULL, NULL,                 /* lockfunc, lockarg */
1883             &sc->arge_cdata.arge_parent_tag);
1884         if (error != 0) {
1885                 device_printf(sc->arge_dev,
1886                     "failed to create parent DMA tag\n");
1887                 goto fail;
1888         }
1889         /* Create tag for Tx ring. */
1890         error = bus_dma_tag_create(
1891             sc->arge_cdata.arge_parent_tag,     /* parent */
1892             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1893             BUS_SPACE_MAXADDR,          /* lowaddr */
1894             BUS_SPACE_MAXADDR,          /* highaddr */
1895             NULL, NULL,                 /* filter, filterarg */
1896             ARGE_TX_DMA_SIZE,           /* maxsize */
1897             1,                          /* nsegments */
1898             ARGE_TX_DMA_SIZE,           /* maxsegsize */
1899             0,                          /* flags */
1900             NULL, NULL,                 /* lockfunc, lockarg */
1901             &sc->arge_cdata.arge_tx_ring_tag);
1902         if (error != 0) {
1903                 device_printf(sc->arge_dev,
1904                     "failed to create Tx ring DMA tag\n");
1905                 goto fail;
1906         }
1907
1908         /* Create tag for Rx ring. */
1909         error = bus_dma_tag_create(
1910             sc->arge_cdata.arge_parent_tag,     /* parent */
1911             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1912             BUS_SPACE_MAXADDR,          /* lowaddr */
1913             BUS_SPACE_MAXADDR,          /* highaddr */
1914             NULL, NULL,                 /* filter, filterarg */
1915             ARGE_RX_DMA_SIZE,           /* maxsize */
1916             1,                          /* nsegments */
1917             ARGE_RX_DMA_SIZE,           /* maxsegsize */
1918             0,                          /* flags */
1919             NULL, NULL,                 /* lockfunc, lockarg */
1920             &sc->arge_cdata.arge_rx_ring_tag);
1921         if (error != 0) {
1922                 device_printf(sc->arge_dev,
1923                     "failed to create Rx ring DMA tag\n");
1924                 goto fail;
1925         }
1926
1927         /* Create tag for Tx buffers. */
1928         error = bus_dma_tag_create(
1929             sc->arge_cdata.arge_parent_tag,     /* parent */
1930             arge_tx_align, 0,           /* alignment, boundary */
1931             BUS_SPACE_MAXADDR,          /* lowaddr */
1932             BUS_SPACE_MAXADDR,          /* highaddr */
1933             NULL, NULL,                 /* filter, filterarg */
1934             MCLBYTES * ARGE_MAXFRAGS,   /* maxsize */
1935             ARGE_MAXFRAGS,              /* nsegments */
1936             MCLBYTES,                   /* maxsegsize */
1937             0,                          /* flags */
1938             NULL, NULL,                 /* lockfunc, lockarg */
1939             &sc->arge_cdata.arge_tx_tag);
1940         if (error != 0) {
1941                 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1942                 goto fail;
1943         }
1944
1945         /* Create tag for Rx buffers. */
1946         error = bus_dma_tag_create(
1947             sc->arge_cdata.arge_parent_tag,     /* parent */
1948             arge_rx_align, 0,           /* alignment, boundary */
1949             BUS_SPACE_MAXADDR,          /* lowaddr */
1950             BUS_SPACE_MAXADDR,          /* highaddr */
1951             NULL, NULL,                 /* filter, filterarg */
1952             MCLBYTES,                   /* maxsize */
1953             ARGE_MAXFRAGS,              /* nsegments */
1954             MCLBYTES,                   /* maxsegsize */
1955             0,                          /* flags */
1956             NULL, NULL,                 /* lockfunc, lockarg */
1957             &sc->arge_cdata.arge_rx_tag);
1958         if (error != 0) {
1959                 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
1960                 goto fail;
1961         }
1962
1963         /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1964         error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
1965             (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
1966             BUS_DMA_COHERENT | BUS_DMA_ZERO,
1967             &sc->arge_cdata.arge_tx_ring_map);
1968         if (error != 0) {
1969                 device_printf(sc->arge_dev,
1970                     "failed to allocate DMA'able memory for Tx ring\n");
1971                 goto fail;
1972         }
1973
1974         ctx.arge_busaddr = 0;
1975         error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
1976             sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
1977             ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1978         if (error != 0 || ctx.arge_busaddr == 0) {
1979                 device_printf(sc->arge_dev,
1980                     "failed to load DMA'able memory for Tx ring\n");
1981                 goto fail;
1982         }
1983         sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
1984
1985         /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1986         error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
1987             (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
1988             BUS_DMA_COHERENT | BUS_DMA_ZERO,
1989             &sc->arge_cdata.arge_rx_ring_map);
1990         if (error != 0) {
1991                 device_printf(sc->arge_dev,
1992                     "failed to allocate DMA'able memory for Rx ring\n");
1993                 goto fail;
1994         }
1995
1996         ctx.arge_busaddr = 0;
1997         error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
1998             sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
1999             ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
2000         if (error != 0 || ctx.arge_busaddr == 0) {
2001                 device_printf(sc->arge_dev,
2002                     "failed to load DMA'able memory for Rx ring\n");
2003                 goto fail;
2004         }
2005         sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
2006
2007         /* Create DMA maps for Tx buffers. */
2008         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2009                 txd = &sc->arge_cdata.arge_txdesc[i];
2010                 txd->tx_m = NULL;
2011                 txd->tx_dmamap = NULL;
2012                 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
2013                     &txd->tx_dmamap);
2014                 if (error != 0) {
2015                         device_printf(sc->arge_dev,
2016                             "failed to create Tx dmamap\n");
2017                         goto fail;
2018                 }
2019         }
2020         /* Create DMA maps for Rx buffers. */
2021         if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
2022             &sc->arge_cdata.arge_rx_sparemap)) != 0) {
2023                 device_printf(sc->arge_dev,
2024                     "failed to create spare Rx dmamap\n");
2025                 goto fail;
2026         }
2027         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2028                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2029                 rxd->rx_m = NULL;
2030                 rxd->rx_dmamap = NULL;
2031                 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
2032                     &rxd->rx_dmamap);
2033                 if (error != 0) {
2034                         device_printf(sc->arge_dev,
2035                             "failed to create Rx dmamap\n");
2036                         goto fail;
2037                 }
2038         }
2039
2040 fail:
2041         return (error);
2042 }
2043
2044 static void
2045 arge_dma_free(struct arge_softc *sc)
2046 {
2047         struct arge_txdesc      *txd;
2048         struct arge_rxdesc      *rxd;
2049         int                     i;
2050
2051         /* Tx ring. */
2052         if (sc->arge_cdata.arge_tx_ring_tag) {
2053                 if (sc->arge_rdata.arge_tx_ring_paddr)
2054                         bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
2055                             sc->arge_cdata.arge_tx_ring_map);
2056                 if (sc->arge_rdata.arge_tx_ring)
2057                         bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
2058                             sc->arge_rdata.arge_tx_ring,
2059                             sc->arge_cdata.arge_tx_ring_map);
2060                 sc->arge_rdata.arge_tx_ring = NULL;
2061                 sc->arge_rdata.arge_tx_ring_paddr = 0;
2062                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
2063                 sc->arge_cdata.arge_tx_ring_tag = NULL;
2064         }
2065         /* Rx ring. */
2066         if (sc->arge_cdata.arge_rx_ring_tag) {
2067                 if (sc->arge_rdata.arge_rx_ring_paddr)
2068                         bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
2069                             sc->arge_cdata.arge_rx_ring_map);
2070                 if (sc->arge_rdata.arge_rx_ring)
2071                         bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
2072                             sc->arge_rdata.arge_rx_ring,
2073                             sc->arge_cdata.arge_rx_ring_map);
2074                 sc->arge_rdata.arge_rx_ring = NULL;
2075                 sc->arge_rdata.arge_rx_ring_paddr = 0;
2076                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
2077                 sc->arge_cdata.arge_rx_ring_tag = NULL;
2078         }
2079         /* Tx buffers. */
2080         if (sc->arge_cdata.arge_tx_tag) {
2081                 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2082                         txd = &sc->arge_cdata.arge_txdesc[i];
2083                         if (txd->tx_dmamap) {
2084                                 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
2085                                     txd->tx_dmamap);
2086                                 txd->tx_dmamap = NULL;
2087                         }
2088                 }
2089                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
2090                 sc->arge_cdata.arge_tx_tag = NULL;
2091         }
2092         /* Rx buffers. */
2093         if (sc->arge_cdata.arge_rx_tag) {
2094                 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2095                         rxd = &sc->arge_cdata.arge_rxdesc[i];
2096                         if (rxd->rx_dmamap) {
2097                                 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
2098                                     rxd->rx_dmamap);
2099                                 rxd->rx_dmamap = NULL;
2100                         }
2101                 }
2102                 if (sc->arge_cdata.arge_rx_sparemap) {
2103                         bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
2104                             sc->arge_cdata.arge_rx_sparemap);
2105                         sc->arge_cdata.arge_rx_sparemap = 0;
2106                 }
2107                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
2108                 sc->arge_cdata.arge_rx_tag = NULL;
2109         }
2110
2111         if (sc->arge_cdata.arge_parent_tag) {
2112                 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
2113                 sc->arge_cdata.arge_parent_tag = NULL;
2114         }
2115 }
2116
2117 /*
2118  * Initialize the transmit descriptors.
2119  */
2120 static int
2121 arge_tx_ring_init(struct arge_softc *sc)
2122 {
2123         struct arge_ring_data   *rd;
2124         struct arge_txdesc      *txd;
2125         bus_addr_t              addr;
2126         int                     i;
2127
2128         sc->arge_cdata.arge_tx_prod = 0;
2129         sc->arge_cdata.arge_tx_cons = 0;
2130         sc->arge_cdata.arge_tx_cnt = 0;
2131
2132         rd = &sc->arge_rdata;
2133         bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
2134         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2135                 if (i == ARGE_TX_RING_COUNT - 1)
2136                         addr = ARGE_TX_RING_ADDR(sc, 0);
2137                 else
2138                         addr = ARGE_TX_RING_ADDR(sc, i + 1);
2139                 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
2140                 rd->arge_tx_ring[i].next_desc = addr;
2141                 txd = &sc->arge_cdata.arge_txdesc[i];
2142                 txd->tx_m = NULL;
2143         }
2144
2145         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2146             sc->arge_cdata.arge_tx_ring_map,
2147             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2148
2149         return (0);
2150 }
2151
2152 /*
2153  * Free the Tx ring, unload any pending dma transaction and free the mbuf.
2154  */
2155 static void
2156 arge_tx_ring_free(struct arge_softc *sc)
2157 {
2158         struct arge_txdesc      *txd;
2159         int                     i;
2160
2161         /* Free the Tx buffers. */
2162         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2163                 txd = &sc->arge_cdata.arge_txdesc[i];
2164                 if (txd->tx_dmamap) {
2165                         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag,
2166                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2167                         bus_dmamap_unload(sc->arge_cdata.arge_tx_tag,
2168                             txd->tx_dmamap);
2169                 }
2170                 if (txd->tx_m)
2171                         m_freem(txd->tx_m);
2172                 txd->tx_m = NULL;
2173         }
2174 }
2175
2176 /*
2177  * Initialize the RX descriptors and allocate mbufs for them. Note that
2178  * we arrange the descriptors in a closed ring, so that the last descriptor
2179  * points back to the first.
2180  */
2181 static int
2182 arge_rx_ring_init(struct arge_softc *sc)
2183 {
2184         struct arge_ring_data   *rd;
2185         struct arge_rxdesc      *rxd;
2186         bus_addr_t              addr;
2187         int                     i;
2188
2189         sc->arge_cdata.arge_rx_cons = 0;
2190
2191         rd = &sc->arge_rdata;
2192         bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
2193         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2194                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2195                 if (rxd->rx_m != NULL) {
2196                         device_printf(sc->arge_dev,
2197                             "%s: ring[%d] rx_m wasn't free?\n",
2198                             __func__,
2199                             i);
2200                 }
2201                 rxd->rx_m = NULL;
2202                 rxd->desc = &rd->arge_rx_ring[i];
2203                 if (i == ARGE_RX_RING_COUNT - 1)
2204                         addr = ARGE_RX_RING_ADDR(sc, 0);
2205                 else
2206                         addr = ARGE_RX_RING_ADDR(sc, i + 1);
2207                 rd->arge_rx_ring[i].next_desc = addr;
2208                 if (arge_newbuf(sc, i) != 0) {
2209                         return (ENOBUFS);
2210                 }
2211         }
2212
2213         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2214             sc->arge_cdata.arge_rx_ring_map,
2215             BUS_DMASYNC_PREWRITE);
2216
2217         return (0);
2218 }
2219
2220 /*
2221  * Free all the buffers in the RX ring.
2222  *
2223  * TODO: ensure that DMA is disabled and no pending DMA
2224  * is lurking in the FIFO.
2225  */
2226 static void
2227 arge_rx_ring_free(struct arge_softc *sc)
2228 {
2229         int i;
2230         struct arge_rxdesc      *rxd;
2231
2232         ARGE_LOCK_ASSERT(sc);
2233
2234         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2235                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2236                 /* Unmap the mbuf */
2237                 if (rxd->rx_m != NULL) {
2238                         bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
2239                             rxd->rx_dmamap);
2240                         m_free(rxd->rx_m);
2241                         rxd->rx_m = NULL;
2242                 }
2243         }
2244 }
2245
2246 /*
2247  * Initialize an RX descriptor and attach an MBUF cluster.
2248  */
2249 static int
2250 arge_newbuf(struct arge_softc *sc, int idx)
2251 {
2252         struct arge_desc                *desc;
2253         struct arge_rxdesc      *rxd;
2254         struct mbuf             *m;
2255         bus_dma_segment_t       segs[1];
2256         bus_dmamap_t            map;
2257         int                     nsegs;
2258
2259         /* XXX TODO: should just allocate an explicit 2KiB buffer */
2260         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2261         if (m == NULL)
2262                 return (ENOBUFS);
2263         m->m_len = m->m_pkthdr.len = MCLBYTES;
2264
2265         /*
2266          * Add extra space to "adjust" (copy) the packet back to be aligned
2267          * for purposes of IPv4/IPv6 header contents.
2268          */
2269         if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE)
2270                 m_adj(m, sizeof(uint64_t));
2271         /*
2272          * If it's a 1-byte aligned buffer, then just offset it two bytes
2273          * and that will give us a hopefully correctly DWORD aligned
2274          * L3 payload - and we won't have to undo it afterwards.
2275          */
2276         else if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
2277                 m_adj(m, sizeof(uint16_t));
2278
2279         if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2280             sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2281                 m_freem(m);
2282                 return (ENOBUFS);
2283         }
2284         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2285
2286         rxd = &sc->arge_cdata.arge_rxdesc[idx];
2287         if (rxd->rx_m != NULL) {
2288                 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2289         }
2290         map = rxd->rx_dmamap;
2291         rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2292         sc->arge_cdata.arge_rx_sparemap = map;
2293         rxd->rx_m = m;
2294         desc = rxd->desc;
2295         if ((sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE) &&
2296             segs[0].ds_addr & 3)
2297                 panic("RX packet address unaligned");
2298         desc->packet_addr = segs[0].ds_addr;
2299         desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2300
2301         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2302             sc->arge_cdata.arge_rx_ring_map,
2303             BUS_DMASYNC_PREWRITE);
2304
2305         return (0);
2306 }
2307
2308 /*
2309  * Move the data backwards 16 bits to (hopefully!) ensure the
2310  * IPv4/IPv6 payload is aligned.
2311  *
2312  * This is required for earlier hardware where the RX path
2313  * requires DWORD aligned buffers.
2314  */
2315 static __inline void
2316 arge_fixup_rx(struct mbuf *m)
2317 {
2318         int             i;
2319         uint16_t        *src, *dst;
2320
2321         src = mtod(m, uint16_t *);
2322         dst = src - 1;
2323
2324         for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
2325                 *dst++ = *src++;
2326         }
2327
2328         if (m->m_len % sizeof(uint16_t))
2329                 *(uint8_t *)dst = *(uint8_t *)src;
2330
2331         m->m_data -= ETHER_ALIGN;
2332 }
2333
2334 #ifdef DEVICE_POLLING
2335 static int
2336 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2337 {
2338         struct arge_softc *sc = ifp->if_softc;
2339         int rx_npkts = 0;
2340
2341         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2342                 ARGE_LOCK(sc);
2343                 arge_tx_locked(sc);
2344                 rx_npkts = arge_rx_locked(sc);
2345                 ARGE_UNLOCK(sc);
2346         }
2347
2348         return (rx_npkts);
2349 }
2350 #endif /* DEVICE_POLLING */
2351
2352
2353 static void
2354 arge_tx_locked(struct arge_softc *sc)
2355 {
2356         struct arge_txdesc      *txd;
2357         struct arge_desc        *cur_tx;
2358         struct ifnet            *ifp;
2359         uint32_t                ctrl;
2360         int                     cons, prod;
2361
2362         ARGE_LOCK_ASSERT(sc);
2363
2364         cons = sc->arge_cdata.arge_tx_cons;
2365         prod = sc->arge_cdata.arge_tx_prod;
2366
2367         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
2368             prod);
2369
2370         if (cons == prod)
2371                 return;
2372
2373         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2374             sc->arge_cdata.arge_tx_ring_map,
2375             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2376
2377         ifp = sc->arge_ifp;
2378         /*
2379          * Go through our tx list and free mbufs for those
2380          * frames that have been transmitted.
2381          */
2382         for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
2383                 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
2384                 ctrl = cur_tx->packet_ctrl;
2385                 /* Check if descriptor has "finished" flag */
2386                 if ((ctrl & ARGE_DESC_EMPTY) == 0)
2387                         break;
2388
2389                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
2390
2391                 sc->arge_cdata.arge_tx_cnt--;
2392                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2393
2394                 txd = &sc->arge_cdata.arge_txdesc[cons];
2395
2396                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2397
2398                 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
2399                     BUS_DMASYNC_POSTWRITE);
2400                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
2401
2402                 /* Free only if it's first descriptor in list */
2403                 if (txd->tx_m)
2404                         m_freem(txd->tx_m);
2405                 txd->tx_m = NULL;
2406
2407                 /* reset descriptor */
2408                 cur_tx->packet_addr = 0;
2409         }
2410
2411         sc->arge_cdata.arge_tx_cons = cons;
2412
2413         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2414             sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
2415 }
2416
2417
2418 static int
2419 arge_rx_locked(struct arge_softc *sc)
2420 {
2421         struct arge_rxdesc      *rxd;
2422         struct ifnet            *ifp = sc->arge_ifp;
2423         int                     cons, prog, packet_len, i;
2424         struct arge_desc        *cur_rx;
2425         struct mbuf             *m;
2426         int                     rx_npkts = 0;
2427
2428         ARGE_LOCK_ASSERT(sc);
2429
2430         cons = sc->arge_cdata.arge_rx_cons;
2431
2432         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2433             sc->arge_cdata.arge_rx_ring_map,
2434             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2435
2436         for (prog = 0; prog < ARGE_RX_RING_COUNT;
2437             ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
2438                 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
2439                 rxd = &sc->arge_cdata.arge_rxdesc[cons];
2440                 m = rxd->rx_m;
2441
2442                 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
2443                        break;
2444
2445                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
2446
2447                 prog++;
2448
2449                 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
2450                 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
2451                     BUS_DMASYNC_POSTREAD);
2452                 m = rxd->rx_m;
2453
2454                 /*
2455                  * If the MAC requires 4 byte alignment then the RX setup
2456                  * routine will have pre-offset things; so un-offset it here.
2457                  */
2458                 if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE)
2459                         arge_fixup_rx(m);
2460
2461                 m->m_pkthdr.rcvif = ifp;
2462                 /* Skip 4 bytes of CRC */
2463                 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
2464                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2465                 rx_npkts++;
2466
2467                 ARGE_UNLOCK(sc);
2468                 (*ifp->if_input)(ifp, m);
2469                 ARGE_LOCK(sc);
2470                 cur_rx->packet_addr = 0;
2471         }
2472
2473         if (prog > 0) {
2474
2475                 i = sc->arge_cdata.arge_rx_cons;
2476                 for (; prog > 0 ; prog--) {
2477                         if (arge_newbuf(sc, i) != 0) {
2478                                 device_printf(sc->arge_dev,
2479                                     "Failed to allocate buffer\n");
2480                                 break;
2481                         }
2482                         ARGE_INC(i, ARGE_RX_RING_COUNT);
2483                 }
2484
2485                 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2486                     sc->arge_cdata.arge_rx_ring_map,
2487                     BUS_DMASYNC_PREWRITE);
2488
2489                 sc->arge_cdata.arge_rx_cons = cons;
2490         }
2491
2492         return (rx_npkts);
2493 }
2494
2495 static int
2496 arge_intr_filter(void *arg)
2497 {
2498         struct arge_softc       *sc = arg;
2499         uint32_t                status, ints;
2500
2501         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2502         ints = ARGE_READ(sc, AR71XX_DMA_INTR);
2503
2504         ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
2505             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2506             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2507         ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2508             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2509             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2510
2511         if (status & DMA_INTR_ALL) {
2512                 sc->arge_intr_status |= status;
2513                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2514                 sc->stats.intr_ok++;
2515                 return (FILTER_SCHEDULE_THREAD);
2516         }
2517
2518         sc->arge_intr_status = 0;
2519         sc->stats.intr_stray++;
2520         return (FILTER_STRAY);
2521 }
2522
2523 static void
2524 arge_intr(void *arg)
2525 {
2526         struct arge_softc       *sc = arg;
2527         uint32_t                status;
2528         struct ifnet            *ifp = sc->arge_ifp;
2529 #ifdef  ARGE_DEBUG
2530         int i;
2531 #endif
2532
2533         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2534         status |= sc->arge_intr_status;
2535
2536         ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2537             "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2538             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2539
2540         /*
2541          * Is it our interrupt at all?
2542          */
2543         if (status == 0) {
2544                 sc->stats.intr_stray2++;
2545                 return;
2546         }
2547
2548 #ifdef  ARGE_DEBUG
2549         for (i = 0; i < 32; i++) {
2550                 if (status & (1U << i)) {
2551                         sc->intr_stats.count[i]++;
2552                 }
2553         }
2554 #endif
2555
2556         if (status & DMA_INTR_RX_BUS_ERROR) {
2557                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2558                 device_printf(sc->arge_dev, "RX bus error");
2559                 return;
2560         }
2561
2562         if (status & DMA_INTR_TX_BUS_ERROR) {
2563                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2564                 device_printf(sc->arge_dev, "TX bus error");
2565                 return;
2566         }
2567
2568         ARGE_LOCK(sc);
2569         arge_flush_ddr(sc);
2570
2571         if (status & DMA_INTR_RX_PKT_RCVD)
2572                 arge_rx_locked(sc);
2573
2574         /*
2575          * RX overrun disables the receiver.
2576          * Clear indication and re-enable rx.
2577          */
2578         if ( status & DMA_INTR_RX_OVERFLOW) {
2579                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2580                 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2581                 sc->stats.rx_overflow++;
2582         }
2583
2584         if (status & DMA_INTR_TX_PKT_SENT)
2585                 arge_tx_locked(sc);
2586         /*
2587          * Underrun turns off TX. Clear underrun indication.
2588          * If there's anything left in the ring, reactivate the tx.
2589          */
2590         if (status & DMA_INTR_TX_UNDERRUN) {
2591                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2592                 sc->stats.tx_underflow++;
2593                 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
2594                     __func__, sc->arge_cdata.arge_tx_cnt);
2595                 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
2596                         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2597                             DMA_TX_CONTROL_EN);
2598                 }
2599         }
2600
2601         /*
2602          * If we've finished TXing and there's space for more packets
2603          * to be queued for TX, do so. Otherwise we may end up in a
2604          * situation where the interface send queue was filled
2605          * whilst the hardware queue was full, then the hardware
2606          * queue was drained by the interface send queue wasn't,
2607          * and thus if_start() is never called to kick-start
2608          * the send process (and all subsequent packets are simply
2609          * discarded.
2610          *
2611          * XXX TODO: make sure that the hardware deals nicely
2612          * with the possibility of the queue being enabled above
2613          * after a TX underrun, then having the hardware queue added
2614          * to below.
2615          */
2616         if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
2617             (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2618                 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2619                         arge_start_locked(ifp);
2620         }
2621
2622         /*
2623          * We handled all bits, clear status
2624          */
2625         sc->arge_intr_status = 0;
2626         ARGE_UNLOCK(sc);
2627         /*
2628          * re-enable all interrupts
2629          */
2630         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2631 }
2632
2633
2634 static void
2635 arge_tick(void *xsc)
2636 {
2637         struct arge_softc       *sc = xsc;
2638         struct mii_data         *mii;
2639
2640         ARGE_LOCK_ASSERT(sc);
2641
2642         if (sc->arge_miibus) {
2643                 mii = device_get_softc(sc->arge_miibus);
2644                 mii_tick(mii);
2645                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
2646         }
2647 }
2648
2649 int
2650 arge_multiphy_mediachange(struct ifnet *ifp)
2651 {
2652         struct arge_softc *sc = ifp->if_softc;
2653         struct ifmedia *ifm = &sc->arge_ifmedia;
2654         struct ifmedia_entry *ife = ifm->ifm_cur;
2655
2656         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2657                 return (EINVAL);
2658
2659         if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
2660                 device_printf(sc->arge_dev,
2661                     "AUTO is not supported for multiphy MAC");
2662                 return (EINVAL);
2663         }
2664
2665         /*
2666          * Ignore everything
2667          */
2668         return (0);
2669 }
2670
2671 void
2672 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2673 {
2674         struct arge_softc *sc = ifp->if_softc;
2675
2676         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2677         ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
2678             sc->arge_duplex_mode;
2679 }
2680
2681 #if defined(ARGE_MDIO)
2682 static int
2683 argemdio_probe(device_t dev)
2684 {
2685         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
2686         return (0);
2687 }
2688
2689 static int
2690 argemdio_attach(device_t dev)
2691 {
2692         struct arge_softc       *sc;
2693         int                     error = 0;
2694
2695         sc = device_get_softc(dev);
2696         sc->arge_dev = dev;
2697         sc->arge_mac_unit = device_get_unit(dev);
2698         sc->arge_rid = 0;
2699         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2700             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
2701         if (sc->arge_res == NULL) {
2702                 device_printf(dev, "couldn't map memory\n");
2703                 error = ENXIO;
2704                 goto fail;
2705         }
2706
2707         /* Reset MAC - required for AR71xx MDIO to successfully occur */
2708         arge_reset_mac(sc);
2709         /* Reset MII bus */
2710         arge_reset_miibus(sc);
2711
2712         bus_generic_probe(dev);
2713         bus_enumerate_hinted_children(dev);
2714         error = bus_generic_attach(dev);
2715 fail:
2716         return (error);
2717 }
2718
2719 static int
2720 argemdio_detach(device_t dev)
2721 {
2722         return (0);
2723 }
2724
2725 #endif