sys/mips/atheros/if_arge.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2009, Oleksandr Tymoshenko
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice unmodified, this list of conditions, and the following
  12  *    disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 /*
  34  * AR71XX gigabit ethernet driver
  35  */
  36 #ifdef HAVE_KERNEL_OPTION_HEADERS
  37 #include "opt_device_polling.h"
  38 #endif
  39
  40 #include "opt_arge.h"
  41
  42 #include <sys/param.h>
  43 #include <sys/endian.h>
  44 #include <sys/systm.h>
  45 #include <sys/sockio.h>
  46 #include <sys/lock.h>
  47 #include <sys/mbuf.h>
  48 #include <sys/malloc.h>
  49 #include <sys/mutex.h>
  50 #include <sys/kernel.h>
  51 #include <sys/module.h>
  52 #include <sys/socket.h>
  53 #include <sys/taskqueue.h>
  54 #include <sys/sysctl.h>
  55
  56 #include <net/if.h>
  57 #include <net/if_var.h>
  58 #include <net/if_media.h>
  59 #include <net/ethernet.h>
  60 #include <net/if_types.h>
  61
  62 #include <net/bpf.h>
  63
  64 #include <machine/bus.h>
  65 #include <machine/cache.h>
  66 #include <machine/resource.h>
  67 #include <vm/vm_param.h>
  68 #include <vm/vm.h>
  69 #include <vm/pmap.h>
  70 #include <sys/bus.h>
  71 #include <sys/rman.h>
  72
  73 #include <dev/mii/mii.h>
  74 #include <dev/mii/miivar.h>
  75
  76 #include <dev/pci/pcireg.h>
  77 #include <dev/pci/pcivar.h>
  78
  79 #include "opt_arge.h"
  80
  81 #if defined(ARGE_MDIO)
  82 #include <dev/mdio/mdio.h>
  83 #include <dev/etherswitch/miiproxy.h>
  84 #include "mdio_if.h"
  85 #endif
  86
  87
  88 MODULE_DEPEND(arge, ether, 1, 1, 1);
  89 MODULE_DEPEND(arge, miibus, 1, 1, 1);
  90 MODULE_VERSION(arge, 1);
  91
  92 #include "miibus_if.h"
  93
  94 #include <net/ethernet.h>
  95
  96 #include <mips/atheros/ar71xxreg.h>
  97 #include <mips/atheros/ar934xreg.h>     /* XXX tsk! */
  98 #include <mips/atheros/qca953xreg.h>    /* XXX tsk! */
  99 #include <mips/atheros/qca955xreg.h>    /* XXX tsk! */
 100 #include <mips/atheros/if_argevar.h>
 101 #include <mips/atheros/ar71xx_setup.h>
 102 #include <mips/atheros/ar71xx_cpudef.h>
 103 #include <mips/atheros/ar71xx_macaddr.h>
 104
 105 typedef enum {
 106         ARGE_DBG_MII    =       0x00000001,
 107         ARGE_DBG_INTR   =       0x00000002,
 108         ARGE_DBG_TX     =       0x00000004,
 109         ARGE_DBG_RX     =       0x00000008,
 110         ARGE_DBG_ERR    =       0x00000010,
 111         ARGE_DBG_RESET  =       0x00000020,
 112         ARGE_DBG_PLL    =       0x00000040,
 113         ARGE_DBG_ANY    =       0xffffffff,
 114 } arge_debug_flags;
 115
 116 static const char * arge_miicfg_str[] = {
 117         "NONE",
 118         "GMII",
 119         "MII",
 120         "RGMII",
 121         "RMII",
 122         "SGMII"
 123 };
 124
 125 #ifdef ARGE_DEBUG
 126 #define ARGEDEBUG(_sc, _m, ...)                                         \
 127         do {                                                            \
 128                 if (((_m) & (_sc)->arge_debug) || ((_m) == ARGE_DBG_ANY)) \
 129                         device_printf((_sc)->arge_dev, __VA_ARGS__);    \
 130         } while (0)
 131 #else
 132 #define ARGEDEBUG(_sc, _m, ...)
 133 #endif
 134
 135 static int arge_attach(device_t);
 136 static int arge_detach(device_t);
 137 static void arge_flush_ddr(struct arge_softc *);
 138 static int arge_ifmedia_upd(struct ifnet *);
 139 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 140 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
 141 static void arge_init(void *);
 142 static void arge_init_locked(struct arge_softc *);
 143 static void arge_link_task(void *, int);
 144 static void arge_update_link_locked(struct arge_softc *sc);
 145 static void arge_set_pll(struct arge_softc *, int, int);
 146 static int arge_miibus_readreg(device_t, int, int);
 147 static void arge_miibus_statchg(device_t);
 148 static int arge_miibus_writereg(device_t, int, int, int);
 149 static int arge_probe(device_t);
 150 static void arge_reset_dma(struct arge_softc *);
 151 static int arge_resume(device_t);
 152 static int arge_rx_ring_init(struct arge_softc *);
 153 static void arge_rx_ring_free(struct arge_softc *sc);
 154 static int arge_tx_ring_init(struct arge_softc *);
 155 static void arge_tx_ring_free(struct arge_softc *);
 156 #ifdef DEVICE_POLLING
 157 static int arge_poll(struct ifnet *, enum poll_cmd, int);
 158 #endif
 159 static int arge_shutdown(device_t);
 160 static void arge_start(struct ifnet *);
 161 static void arge_start_locked(struct ifnet *);
 162 static void arge_stop(struct arge_softc *);
 163 static int arge_suspend(device_t);
 164
 165 static int arge_rx_locked(struct arge_softc *);
 166 static void arge_tx_locked(struct arge_softc *);
 167 static void arge_intr(void *);
 168 static int arge_intr_filter(void *);
 169 static void arge_tick(void *);
 170
 171 static void arge_hinted_child(device_t bus, const char *dname, int dunit);
 172
 173 /*
 174  * ifmedia callbacks for multiPHY MAC
 175  */
 176 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
 177 int arge_multiphy_mediachange(struct ifnet *);
 178
 179 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 180 static int arge_dma_alloc(struct arge_softc *);
 181 static void arge_dma_free(struct arge_softc *);
 182 static int arge_newbuf(struct arge_softc *, int);
 183 static __inline void arge_fixup_rx(struct mbuf *);
 184
 185 static device_method_t arge_methods[] = {
 186         /* Device interface */
 187         DEVMETHOD(device_probe,         arge_probe),
 188         DEVMETHOD(device_attach,        arge_attach),
 189         DEVMETHOD(device_detach,        arge_detach),
 190         DEVMETHOD(device_suspend,       arge_suspend),
 191         DEVMETHOD(device_resume,        arge_resume),
 192         DEVMETHOD(device_shutdown,      arge_shutdown),
 193
 194         /* MII interface */
 195         DEVMETHOD(miibus_readreg,       arge_miibus_readreg),
 196         DEVMETHOD(miibus_writereg,      arge_miibus_writereg),
 197         DEVMETHOD(miibus_statchg,       arge_miibus_statchg),
 198
 199         /* bus interface */
 200         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 201         DEVMETHOD(bus_hinted_child,     arge_hinted_child),
 202
 203         DEVMETHOD_END
 204 };
 205
 206 static driver_t arge_driver = {
 207         "arge",
 208         arge_methods,
 209         sizeof(struct arge_softc)
 210 };
 211
 212 static devclass_t arge_devclass;
 213
 214 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
 215 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
 216
 217 #if defined(ARGE_MDIO)
 218 static int argemdio_probe(device_t);
 219 static int argemdio_attach(device_t);
 220 static int argemdio_detach(device_t);
 221
 222 /*
 223  * Declare an additional, separate driver for accessing the MDIO bus.
 224  */
 225 static device_method_t argemdio_methods[] = {
 226         /* Device interface */
 227         DEVMETHOD(device_probe,         argemdio_probe),
 228         DEVMETHOD(device_attach,        argemdio_attach),
 229         DEVMETHOD(device_detach,        argemdio_detach),
 230
 231         /* bus interface */
 232         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 233
 234         /* MDIO access */
 235         DEVMETHOD(mdio_readreg,         arge_miibus_readreg),
 236         DEVMETHOD(mdio_writereg,        arge_miibus_writereg),
 237 };
 238
 239 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
 240     sizeof(struct arge_softc));
 241 static devclass_t argemdio_devclass;
 242
 243 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
 244 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
 245 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
 246 #endif
 247
 248 static struct mtx miibus_mtx;
 249
 250 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
 251
 252 /*
 253  * Flushes all
 254  *
 255  * XXX this needs to be done at interrupt time! Grr!
 256  */
 257 static void
 258 arge_flush_ddr(struct arge_softc *sc)
 259 {
 260         switch (sc->arge_mac_unit) {
 261         case 0:
 262                 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE0);
 263                 break;
 264         case 1:
 265                 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_GE1);
 266                 break;
 267         default:
 268                 device_printf(sc->arge_dev, "%s: unknown unit (%d)\n",
 269                     __func__,
 270                     sc->arge_mac_unit);
 271                 break;
 272         }
 273 }
 274
 275 static int
 276 arge_probe(device_t dev)
 277 {
 278
 279         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
 280         return (BUS_PROBE_NOWILDCARD);
 281 }
 282
 283 #ifdef  ARGE_DEBUG
 284 static void
 285 arge_attach_intr_sysctl(device_t dev, struct sysctl_oid_list *parent)
 286 {
 287         struct arge_softc *sc = device_get_softc(dev);
 288         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 289         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 290         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
 291         char sn[8];
 292         int i;
 293
 294         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "intr",
 295             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt statistics");
 296         child = SYSCTL_CHILDREN(tree);
 297         for (i = 0; i < 32; i++) {
 298                 snprintf(sn, sizeof(sn), "%d", i);
 299                 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD,
 300                     &sc->intr_stats.count[i], 0, "");
 301         }
 302 }
 303 #endif
 304
 305 static void
 306 arge_attach_sysctl(device_t dev)
 307 {
 308         struct arge_softc *sc = device_get_softc(dev);
 309         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 310         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 311
 312 #ifdef  ARGE_DEBUG
 313         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 314                 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
 315                 "arge interface debugging flags");
 316         arge_attach_intr_sysctl(dev, SYSCTL_CHILDREN(tree));
 317 #endif
 318
 319         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 320                 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
 321                 "number of TX aligned packets");
 322
 323         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 324                 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
 325                 0, "number of TX unaligned packets");
 326
 327         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 328                 "tx_pkts_unaligned_start", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_start,
 329                 0, "number of TX unaligned packets (start)");
 330
 331         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 332                 "tx_pkts_unaligned_len", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_len,
 333                 0, "number of TX unaligned packets (len)");
 334
 335         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 336                 "tx_pkts_unaligned_tooshort", CTLFLAG_RW,
 337                 &sc->stats.tx_pkts_unaligned_tooshort,
 338                 0, "number of TX unaligned packets (mbuf length < 4 bytes)");
 339
 340         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 341                 "tx_pkts_nosegs", CTLFLAG_RW, &sc->stats.tx_pkts_nosegs,
 342                 0, "number of TX packets fail with no ring slots avail");
 343
 344         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 345                 "intr_stray_filter", CTLFLAG_RW, &sc->stats.intr_stray,
 346                 0, "number of stray interrupts (filter)");
 347
 348         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 349                 "intr_stray_intr", CTLFLAG_RW, &sc->stats.intr_stray2,
 350                 0, "number of stray interrupts (intr)");
 351
 352         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 353                 "intr_ok", CTLFLAG_RW, &sc->stats.intr_ok,
 354                 0, "number of OK interrupts");
 355
 356         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 357                 "tx_underflow", CTLFLAG_RW, &sc->stats.tx_underflow,
 358                 0, "Number of TX underflows");
 359         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 360                 "rx_overflow", CTLFLAG_RW, &sc->stats.rx_overflow,
 361                 0, "Number of RX overflows");
 362 #ifdef  ARGE_DEBUG
 363         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
 364             CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
 365         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
 366             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
 367         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
 368             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
 369 #endif
 370 }
 371
 372 static void
 373 arge_reset_mac(struct arge_softc *sc)
 374 {
 375         uint32_t reg;
 376         uint32_t reset_reg;
 377
 378         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s called\n", __func__);
 379
 380         /* Step 1. Soft-reset MAC */
 381         ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
 382         DELAY(20);
 383
 384         /* Step 2. Punt the MAC core from the central reset register */
 385         /*
 386          * XXX TODO: migrate this (and other) chip specific stuff into
 387          * a chipdef method.
 388          */
 389         if (sc->arge_mac_unit == 0) {
 390                 reset_reg = RST_RESET_GE0_MAC;
 391         } else {
 392                 reset_reg = RST_RESET_GE1_MAC;
 393         }
 394
 395         /*
 396          * AR934x (and later) also needs the MDIO block reset.
 397          * XXX should methodize this!
 398          */
 399         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
 400            ar71xx_soc == AR71XX_SOC_AR9342 ||
 401            ar71xx_soc == AR71XX_SOC_AR9344) {
 402                 if (sc->arge_mac_unit == 0) {
 403                         reset_reg |= AR934X_RESET_GE0_MDIO;
 404                 } else {
 405                         reset_reg |= AR934X_RESET_GE1_MDIO;
 406                 }
 407         }
 408
 409         if (ar71xx_soc == AR71XX_SOC_QCA9556 ||
 410            ar71xx_soc == AR71XX_SOC_QCA9558) {
 411                 if (sc->arge_mac_unit == 0) {
 412                         reset_reg |= QCA955X_RESET_GE0_MDIO;
 413                 } else {
 414                         reset_reg |= QCA955X_RESET_GE1_MDIO;
 415                 }
 416         }
 417
 418         if (ar71xx_soc == AR71XX_SOC_QCA9533 ||
 419            ar71xx_soc == AR71XX_SOC_QCA9533_V2) {
 420                 if (sc->arge_mac_unit == 0) {
 421                         reset_reg |= QCA953X_RESET_GE0_MDIO;
 422                 } else {
 423                         reset_reg |= QCA953X_RESET_GE1_MDIO;
 424                 }
 425         }
 426
 427         ar71xx_device_stop(reset_reg);
 428         DELAY(100);
 429         ar71xx_device_start(reset_reg);
 430
 431         /* Step 3. Reconfigure MAC block */
 432         ARGE_WRITE(sc, AR71XX_MAC_CFG1,
 433                 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
 434                 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
 435
 436         reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
 437         reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
 438         ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
 439
 440         ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
 441 }
 442
 443 /*
 444  * These values map to the divisor values programmed into
 445  * AR71XX_MAC_MII_CFG.
 446  *
 447  * The index of each value corresponds to the divisor section
 448  * value in AR71XX_MAC_MII_CFG (ie, table[0] means '0' in
 449  * AR71XX_MAC_MII_CFG, table[1] means '1', etc.)
 450  */
 451 static const uint32_t ar71xx_mdio_div_table[] = {
 452         4, 4, 6, 8, 10, 14, 20, 28,
 453 };
 454
 455 static const uint32_t ar7240_mdio_div_table[] = {
 456         2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
 457 };
 458
 459 static const uint32_t ar933x_mdio_div_table[] = {
 460         4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
 461 };
 462
 463 /*
 464  * Lookup the divisor to use based on the given frequency.
 465  *
 466  * Returns the divisor to use, or -ve on error.
 467  */
 468 static int
 469 arge_mdio_get_divider(struct arge_softc *sc, unsigned long mdio_clock)
 470 {
 471         unsigned long ref_clock, t;
 472         const uint32_t *table;
 473         int ndivs;
 474         int i;
 475
 476         /*
 477          * This is the base MDIO frequency on the SoC.
 478          * The dividers .. well, divide. Duh.
 479          */
 480         ref_clock = ar71xx_mdio_freq();
 481
 482         /*
 483          * If either clock is undefined, just tell the
 484          * caller to fall through to the defaults.
 485          */
 486         if (ref_clock == 0 || mdio_clock == 0)
 487                 return (-EINVAL);
 488
 489         /*
 490          * Pick the correct table!
 491          */
 492         switch (ar71xx_soc) {
 493         case AR71XX_SOC_AR9330:
 494         case AR71XX_SOC_AR9331:
 495         case AR71XX_SOC_AR9341:
 496         case AR71XX_SOC_AR9342:
 497         case AR71XX_SOC_AR9344:
 498         case AR71XX_SOC_QCA9533:
 499         case AR71XX_SOC_QCA9533_V2:
 500         case AR71XX_SOC_QCA9556:
 501         case AR71XX_SOC_QCA9558:
 502                 table = ar933x_mdio_div_table;
 503                 ndivs = nitems(ar933x_mdio_div_table);
 504                 break;
 505
 506         case AR71XX_SOC_AR7240:
 507         case AR71XX_SOC_AR7241:
 508         case AR71XX_SOC_AR7242:
 509                 table = ar7240_mdio_div_table;
 510                 ndivs = nitems(ar7240_mdio_div_table);
 511                 break;
 512
 513         default:
 514                 table = ar71xx_mdio_div_table;
 515                 ndivs = nitems(ar71xx_mdio_div_table);
 516         }
 517
 518         /*
 519          * Now, walk through the list and find the first divisor
 520          * that falls under the target MDIO frequency.
 521          *
 522          * The divisors go up, but the corresponding frequencies
 523          * are actually decreasing.
 524          */
 525         for (i = 0; i < ndivs; i++) {
 526                 t = ref_clock / table[i];
 527                 if (t <= mdio_clock) {
 528                         return (i);
 529                 }
 530         }
 531
 532         ARGEDEBUG(sc, ARGE_DBG_RESET,
 533             "No divider found; MDIO=%lu Hz; target=%lu Hz\n",
 534                 ref_clock, mdio_clock);
 535         return (-ENOENT);
 536 }
 537
 538 /*
 539  * Fetch the MDIO bus clock rate.
 540  *
 541  * For now, the default is DIV_28 for everything
 542  * bar AR934x, which will be DIV_58.
 543  *
 544  * It will definitely need updating to take into account
 545  * the MDIO bus core clock rate and the target clock
 546  * rate for the chip.
 547  */
 548 static uint32_t
 549 arge_fetch_mdiobus_clock_rate(struct arge_softc *sc)
 550 {
 551         int mdio_freq, div;
 552
 553         /*
 554          * Is the MDIO frequency defined? If so, find a divisor that
 555          * makes reasonable sense.  Don't overshoot the frequency.
 556          */
 557         if (resource_int_value(device_get_name(sc->arge_dev),
 558             device_get_unit(sc->arge_dev),
 559             "mdio_freq",
 560             &mdio_freq) == 0) {
 561                 sc->arge_mdiofreq = mdio_freq;
 562                 div = arge_mdio_get_divider(sc, sc->arge_mdiofreq);
 563                 if (bootverbose)
 564                         device_printf(sc->arge_dev,
 565                             "%s: mdio ref freq=%llu Hz, target freq=%llu Hz,"
 566                             " divisor index=%d\n",
 567                             __func__,
 568                             (unsigned long long) ar71xx_mdio_freq(),
 569                             (unsigned long long) mdio_freq,
 570                             div);
 571                 if (div >= 0)
 572                         return (div);
 573         }
 574
 575         /*
 576          * Default value(s).
 577          *
 578          * XXX obviously these need .. fixing.
 579          *
 580          * From Linux/OpenWRT:
 581          *
 582          * + 7240? DIV_6
 583          * + Builtin-switch port and not 934x? DIV_10
 584          * + Not built-in switch port and 934x? DIV_58
 585          * + .. else DIV_28.
 586          */
 587         switch (ar71xx_soc) {
 588         case AR71XX_SOC_AR9341:
 589         case AR71XX_SOC_AR9342:
 590         case AR71XX_SOC_AR9344:
 591         case AR71XX_SOC_QCA9533:
 592         case AR71XX_SOC_QCA9533_V2:
 593         case AR71XX_SOC_QCA9556:
 594         case AR71XX_SOC_QCA9558:
 595                 return (MAC_MII_CFG_CLOCK_DIV_58);
 596                 break;
 597         default:
 598                 return (MAC_MII_CFG_CLOCK_DIV_28);
 599         }
 600 }
 601
 602 static void
 603 arge_reset_miibus(struct arge_softc *sc)
 604 {
 605         uint32_t mdio_div;
 606
 607         mdio_div = arge_fetch_mdiobus_clock_rate(sc);
 608
 609         /*
 610          * XXX AR934x and later; should we be also resetting the
 611          * MDIO block(s) using the reset register block?
 612          */
 613
 614         /* Reset MII bus; program in the default divisor */
 615         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_div);
 616         DELAY(100);
 617         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_div);
 618         DELAY(100);
 619 }
 620
 621 static void
 622 arge_fetch_pll_config(struct arge_softc *sc)
 623 {
 624         long int val;
 625
 626         if (resource_long_value(device_get_name(sc->arge_dev),
 627             device_get_unit(sc->arge_dev),
 628             "pll_10", &val) == 0) {
 629                 sc->arge_pllcfg.pll_10 = val;
 630                 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
 631                     __func__, (int) val);
 632         }
 633         if (resource_long_value(device_get_name(sc->arge_dev),
 634             device_get_unit(sc->arge_dev),
 635             "pll_100", &val) == 0) {
 636                 sc->arge_pllcfg.pll_100 = val;
 637                 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
 638                     __func__, (int) val);
 639         }
 640         if (resource_long_value(device_get_name(sc->arge_dev),
 641             device_get_unit(sc->arge_dev),
 642             "pll_1000", &val) == 0) {
 643                 sc->arge_pllcfg.pll_1000 = val;
 644                 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
 645                     __func__, (int) val);
 646         }
 647 }
 648
 649 static int
 650 arge_attach(device_t dev)
 651 {
 652         struct ifnet            *ifp;
 653         struct arge_softc       *sc;
 654         int                     error = 0, rid, i;
 655         uint32_t                hint;
 656         long                    eeprom_mac_addr = 0;
 657         int                     miicfg = 0;
 658         int                     readascii = 0;
 659         int                     local_mac = 0;
 660         uint8_t                 local_macaddr[ETHER_ADDR_LEN];
 661         char *                  local_macstr;
 662         char                    devid_str[32];
 663         int                     count;
 664
 665         sc = device_get_softc(dev);
 666         sc->arge_dev = dev;
 667         sc->arge_mac_unit = device_get_unit(dev);
 668
 669         /*
 670          * See if there's a "board" MAC address hint available for
 671          * this particular device.
 672          *
 673          * This is in the environment - it'd be nice to use the resource_*()
 674          * routines, but at the moment the system is booting, the resource hints
 675          * are set to the 'static' map so they're not pulling from kenv.
 676          */
 677         snprintf(devid_str, 32, "hint.%s.%d.macaddr",
 678             device_get_name(dev),
 679             device_get_unit(dev));
 680         if ((local_macstr = kern_getenv(devid_str)) != NULL) {
 681                 uint32_t tmpmac[ETHER_ADDR_LEN];
 682
 683                 /* Have a MAC address; should use it */
 684                 device_printf(dev, "Overriding MAC address from environment: '%s'\n",
 685                     local_macstr);
 686
 687                 /* Extract out the MAC address */
 688                 /* XXX this should all be a generic method */
 689                 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
 690                     &tmpmac[0], &tmpmac[1],
 691                     &tmpmac[2], &tmpmac[3],
 692                     &tmpmac[4], &tmpmac[5]);
 693                 if (count == 6) {
 694                         /* Valid! */
 695                         local_mac = 1;
 696                         for (i = 0; i < ETHER_ADDR_LEN; i++)
 697                                 local_macaddr[i] = tmpmac[i];
 698                 }
 699                 /* Done! */
 700                 freeenv(local_macstr);
 701                 local_macstr = NULL;
 702         }
 703
 704         /*
 705          * Hardware workarounds.
 706          */
 707         switch (ar71xx_soc) {
 708         case AR71XX_SOC_AR9330:
 709         case AR71XX_SOC_AR9331:
 710         case AR71XX_SOC_AR9341:
 711         case AR71XX_SOC_AR9342:
 712         case AR71XX_SOC_AR9344:
 713         case AR71XX_SOC_QCA9533:
 714         case AR71XX_SOC_QCA9533_V2:
 715         case AR71XX_SOC_QCA9556:
 716         case AR71XX_SOC_QCA9558:
 717                 /* Arbitrary alignment */
 718                 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE;
 719                 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE;
 720                 break;
 721         default:
 722                 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE;
 723                 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE;
 724                 break;
 725         }
 726
 727         /*
 728          * Some units (eg the TP-Link WR-1043ND) do not have a convenient
 729          * EEPROM location to read the ethernet MAC address from.
 730          * OpenWRT simply snaffles it from a fixed location.
 731          *
 732          * Since multiple units seem to use this feature, include
 733          * a method of setting the MAC address based on an flash location
 734          * in CPU address space.
 735          *
 736          * Some vendors have decided to store the mac address as a literal
 737          * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of
 738          * an array of numbers.  Expose a hint to turn on this conversion
 739          * feature via strtol()
 740          */
 741          if (local_mac == 0 && resource_long_value(device_get_name(dev),
 742              device_get_unit(dev), "eeprommac", &eeprom_mac_addr) == 0) {
 743                 local_mac = 1;
 744                 int i;
 745                 const char *mac =
 746                     (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
 747                 device_printf(dev, "Overriding MAC from EEPROM\n");
 748                 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 749                         "readascii", &readascii) == 0) {
 750                         device_printf(dev, "Vendor stores MAC in ASCII format\n");
 751                         for (i = 0; i < 6; i++) {
 752                                 local_macaddr[i] = strtol(&(mac[i*3]), NULL, 16);
 753                         }
 754                 } else {
 755                         for (i = 0; i < 6; i++) {
 756                                 local_macaddr[i] = mac[i];
 757                         }
 758                 }
 759         }
 760
 761         KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
 762             ("if_arge: Only MAC0 and MAC1 supported"));
 763
 764         /*
 765          * Fetch the PLL configuration.
 766          */
 767         arge_fetch_pll_config(sc);
 768
 769         /*
 770          * Get the MII configuration, if applicable.
 771          */
 772         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 773             "miimode", &miicfg) == 0) {
 774                 /* XXX bounds check? */
 775                 device_printf(dev, "%s: overriding MII mode to '%s'\n",
 776                     __func__, arge_miicfg_str[miicfg]);
 777                 sc->arge_miicfg = miicfg;
 778         }
 779
 780         /*
 781          *  Get which PHY of 5 available we should use for this unit
 782          */
 783         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 784             "phymask", &sc->arge_phymask) != 0) {
 785                 /*
 786                  * Use port 4 (WAN) for GE0. For any other port use
 787                  * its PHY the same as its unit number
 788                  */
 789                 if (sc->arge_mac_unit == 0)
 790                         sc->arge_phymask = (1 << 4);
 791                 else
 792                         /* Use all phys up to 4 */
 793                         sc->arge_phymask = (1 << 4) - 1;
 794
 795                 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
 796         }
 797
 798         /*
 799          * Get default/hard-coded media & duplex mode.
 800          */
 801         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 802             "media", &hint) != 0)
 803                 hint = 0;
 804
 805         if (hint == 1000)
 806                 sc->arge_media_type = IFM_1000_T;
 807         else if (hint == 100)
 808                 sc->arge_media_type = IFM_100_TX;
 809         else if (hint == 10)
 810                 sc->arge_media_type = IFM_10_T;
 811         else
 812                 sc->arge_media_type = 0;
 813
 814         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 815             "fduplex", &hint) != 0)
 816                 hint = 1;
 817
 818         if (hint)
 819                 sc->arge_duplex_mode = IFM_FDX;
 820         else
 821                 sc->arge_duplex_mode = 0;
 822
 823         mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 824             MTX_DEF);
 825         callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
 826         TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
 827
 828         /* Map control/status registers. */
 829         sc->arge_rid = 0;
 830         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 831             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
 832
 833         if (sc->arge_res == NULL) {
 834                 device_printf(dev, "couldn't map memory\n");
 835                 error = ENXIO;
 836                 goto fail;
 837         }
 838
 839         /* Allocate interrupts */
 840         rid = 0;
 841         sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 842             RF_SHAREABLE | RF_ACTIVE);
 843
 844         if (sc->arge_irq == NULL) {
 845                 device_printf(dev, "couldn't map interrupt\n");
 846                 error = ENXIO;
 847                 goto fail;
 848         }
 849
 850         /* Allocate ifnet structure. */
 851         ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
 852
 853         if (ifp == NULL) {
 854                 device_printf(dev, "couldn't allocate ifnet structure\n");
 855                 error = ENOSPC;
 856                 goto fail;
 857         }
 858
 859         ifp->if_softc = sc;
 860         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 861         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 862         ifp->if_ioctl = arge_ioctl;
 863         ifp->if_start = arge_start;
 864         ifp->if_init = arge_init;
 865         sc->arge_if_flags = ifp->if_flags;
 866
 867         /* XXX: add real size */
 868         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 869         ifp->if_snd.ifq_maxlen = ifqmaxlen;
 870         IFQ_SET_READY(&ifp->if_snd);
 871
 872         /* Tell the upper layer(s) we support long frames. */
 873         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 874
 875         ifp->if_capenable = ifp->if_capabilities;
 876 #ifdef DEVICE_POLLING
 877         ifp->if_capabilities |= IFCAP_POLLING;
 878 #endif
 879
 880         /* If there's a local mac defined, copy that in */
 881         if (local_mac == 1) {
 882                 (void) ar71xx_mac_addr_init(sc->arge_eaddr,
 883                     local_macaddr, 0, 0);
 884         } else {
 885                 /*
 886                  * No MAC address configured. Generate the random one.
 887                  */
 888                 if  (bootverbose)
 889                         device_printf(dev,
 890                             "Generating random ethernet address.\n");
 891                 if (ar71xx_mac_addr_random_init(ifp, (void *) sc->arge_eaddr) < 0) {
 892                         device_printf(dev, "Failed to choose random MAC address\n");
 893                         error = EINVAL;
 894                         goto fail;
 895                 }
 896         }
 897
 898         if (arge_dma_alloc(sc) != 0) {
 899                 error = ENXIO;
 900                 goto fail;
 901         }
 902
 903         /*
 904          * Don't do this for the MDIO bus case - it's already done
 905          * as part of the MDIO bus attachment.
 906          *
 907          * XXX TODO: if we don't do this, we don't ever release the MAC
 908          * from reset and we can't use the port.  Now, if we define ARGE_MDIO
 909          * but we /don't/ define two MDIO busses, then we can't actually
 910          * use both MACs.
 911          */
 912 #if !defined(ARGE_MDIO)
 913         /* Initialize the MAC block */
 914         arge_reset_mac(sc);
 915         arge_reset_miibus(sc);
 916 #endif
 917
 918         /* Configure MII mode, just for convienence */
 919         if (sc->arge_miicfg != 0)
 920                 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
 921
 922         /*
 923          * Set all Ethernet address registers to the same initial values
 924          * set all four addresses to 66-88-aa-cc-dd-ee
 925          */
 926         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
 927             | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
 928             | sc->arge_eaddr[5]);
 929         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
 930             | sc->arge_eaddr[1]);
 931
 932         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
 933             FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
 934
 935         /*
 936          * SoC specific bits.
 937          */
 938         switch (ar71xx_soc) {
 939                 case AR71XX_SOC_AR7240:
 940                 case AR71XX_SOC_AR7241:
 941                 case AR71XX_SOC_AR7242:
 942                 case AR71XX_SOC_AR9330:
 943                 case AR71XX_SOC_AR9331:
 944                 case AR71XX_SOC_AR9341:
 945                 case AR71XX_SOC_AR9342:
 946                 case AR71XX_SOC_AR9344:
 947                 case AR71XX_SOC_QCA9533:
 948                 case AR71XX_SOC_QCA9533_V2:
 949                 case AR71XX_SOC_QCA9556:
 950                 case AR71XX_SOC_QCA9558:
 951                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
 952                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
 953                         break;
 954                 /* AR71xx, AR913x */
 955                 default:
 956                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
 957                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
 958         }
 959
 960         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
 961             FIFO_RX_FILTMATCH_DEFAULT);
 962
 963         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
 964             FIFO_RX_FILTMASK_DEFAULT);
 965
 966 #if defined(ARGE_MDIO)
 967         sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
 968 #endif
 969
 970         device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
 971             ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
 972             "null" : "set");
 973         for (i = 0; i < ARGE_NPHY; i++) {
 974                 if (((1 << i) & sc->arge_phymask) != 0) {
 975                         error = mii_attach(sc->arge_miiproxy != NULL ?
 976                             sc->arge_miiproxy : sc->arge_dev,
 977                             &sc->arge_miibus, sc->arge_ifp,
 978                             arge_ifmedia_upd, arge_ifmedia_sts,
 979                             BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
 980                         if (error != 0) {
 981                                 device_printf(sc->arge_dev, "unable to attach"
 982                                     " PHY %d: %d\n", i, error);
 983                                 goto fail;
 984                         }
 985                 }
 986         }
 987
 988         if (sc->arge_miibus == NULL) {
 989                 /* no PHY, so use hard-coded values */
 990                 ifmedia_init(&sc->arge_ifmedia, 0,
 991                     arge_multiphy_mediachange,
 992                     arge_multiphy_mediastatus);
 993                 ifmedia_add(&sc->arge_ifmedia,
 994                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode,
 995                     0, NULL);
 996                 ifmedia_set(&sc->arge_ifmedia,
 997                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode);
 998                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
 999         }
1000
1001         /* Call MI attach routine. */
1002         ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
1003
1004         /* Hook interrupt last to avoid having to lock softc */
1005         error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
1006             arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
1007
1008         if (error) {
1009                 device_printf(sc->arge_dev, "couldn't set up irq\n");
1010                 ether_ifdetach(sc->arge_ifp);
1011                 goto fail;
1012         }
1013
1014         /* setup sysctl variables */
1015         arge_attach_sysctl(sc->arge_dev);
1016
1017 fail:
1018         if (error)
1019                 arge_detach(dev);
1020
1021         return (error);
1022 }
1023
1024 static int
1025 arge_detach(device_t dev)
1026 {
1027         struct arge_softc       *sc = device_get_softc(dev);
1028         struct ifnet            *ifp = sc->arge_ifp;
1029
1030         KASSERT(mtx_initialized(&sc->arge_mtx),
1031             ("arge mutex not initialized"));
1032
1033         /* These should only be active if attach succeeded */
1034         if (device_is_attached(dev)) {
1035                 ARGE_LOCK(sc);
1036                 sc->arge_detach = 1;
1037 #ifdef DEVICE_POLLING
1038                 if (ifp->if_capenable & IFCAP_POLLING)
1039                         ether_poll_deregister(ifp);
1040 #endif
1041
1042                 arge_stop(sc);
1043                 ARGE_UNLOCK(sc);
1044                 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
1045                 ether_ifdetach(ifp);
1046         }
1047
1048         if (sc->arge_miibus)
1049                 device_delete_child(dev, sc->arge_miibus);
1050
1051         if (sc->arge_miiproxy)
1052                 device_delete_child(dev, sc->arge_miiproxy);
1053
1054         bus_generic_detach(dev);
1055
1056         if (sc->arge_intrhand)
1057                 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
1058
1059         if (sc->arge_res)
1060                 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
1061                     sc->arge_res);
1062
1063         if (ifp)
1064                 if_free(ifp);
1065
1066         arge_dma_free(sc);
1067
1068         mtx_destroy(&sc->arge_mtx);
1069
1070         return (0);
1071
1072 }
1073
1074 static int
1075 arge_suspend(device_t dev)
1076 {
1077
1078         panic("%s", __func__);
1079         return 0;
1080 }
1081
1082 static int
1083 arge_resume(device_t dev)
1084 {
1085
1086         panic("%s", __func__);
1087         return 0;
1088 }
1089
1090 static int
1091 arge_shutdown(device_t dev)
1092 {
1093         struct arge_softc       *sc;
1094
1095         sc = device_get_softc(dev);
1096
1097         ARGE_LOCK(sc);
1098         arge_stop(sc);
1099         ARGE_UNLOCK(sc);
1100
1101         return (0);
1102 }
1103
1104 static void
1105 arge_hinted_child(device_t bus, const char *dname, int dunit)
1106 {
1107         BUS_ADD_CHILD(bus, 0, dname, dunit);
1108         device_printf(bus, "hinted child %s%d\n", dname, dunit);
1109 }
1110
1111 static int
1112 arge_mdio_busy(struct arge_softc *sc)
1113 {
1114         int i,result;
1115
1116         for (i = 0; i < ARGE_MII_TIMEOUT; i++) {
1117                 DELAY(5);
1118                 ARGE_MDIO_BARRIER_READ(sc);
1119                 result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR);
1120                 if (! result)
1121                         return (0);
1122                 DELAY(5);
1123         }
1124         return (-1);
1125 }
1126
1127 static int
1128 arge_miibus_readreg(device_t dev, int phy, int reg)
1129 {
1130         struct arge_softc * sc = device_get_softc(dev);
1131         int result;
1132         uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
1133             | (reg & MAC_MII_REG_MASK);
1134
1135         mtx_lock(&miibus_mtx);
1136         ARGE_MDIO_BARRIER_RW(sc);
1137         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
1138         ARGE_MDIO_BARRIER_WRITE(sc);
1139         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1140         ARGE_MDIO_BARRIER_WRITE(sc);
1141         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
1142
1143         if (arge_mdio_busy(sc) != 0) {
1144                 mtx_unlock(&miibus_mtx);
1145                 ARGEDEBUG(sc, ARGE_DBG_ANY, "%s timedout\n", __func__);
1146                 /* XXX: return ERRNO istead? */
1147                 return (-1);
1148         }
1149
1150         ARGE_MDIO_BARRIER_READ(sc);
1151         result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
1152         ARGE_MDIO_BARRIER_RW(sc);
1153         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
1154         mtx_unlock(&miibus_mtx);
1155
1156         ARGEDEBUG(sc, ARGE_DBG_MII,
1157             "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
1158             __func__, phy, reg, addr, result);
1159
1160         return (result);
1161 }
1162
1163 static int
1164 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
1165 {
1166         struct arge_softc * sc = device_get_softc(dev);
1167         uint32_t addr =
1168             (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
1169
1170         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
1171             phy, reg, data);
1172
1173         mtx_lock(&miibus_mtx);
1174         ARGE_MDIO_BARRIER_RW(sc);
1175         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1176         ARGE_MDIO_BARRIER_WRITE(sc);
1177         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
1178         ARGE_MDIO_BARRIER_WRITE(sc);
1179
1180         if (arge_mdio_busy(sc) != 0) {
1181                 mtx_unlock(&miibus_mtx);
1182                 ARGEDEBUG(sc, ARGE_DBG_ANY, "%s timedout\n", __func__);
1183                 /* XXX: return ERRNO istead? */
1184                 return (-1);
1185         }
1186
1187         mtx_unlock(&miibus_mtx);
1188         return (0);
1189 }
1190
1191 static void
1192 arge_miibus_statchg(device_t dev)
1193 {
1194         struct arge_softc       *sc;
1195
1196         sc = device_get_softc(dev);
1197         taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
1198 }
1199
1200 static void
1201 arge_link_task(void *arg, int pending)
1202 {
1203         struct arge_softc       *sc;
1204         sc = (struct arge_softc *)arg;
1205
1206         ARGE_LOCK(sc);
1207         arge_update_link_locked(sc);
1208         ARGE_UNLOCK(sc);
1209 }
1210
1211 static void
1212 arge_update_link_locked(struct arge_softc *sc)
1213 {
1214         struct mii_data         *mii;
1215         struct ifnet            *ifp;
1216         uint32_t                media, duplex;
1217
1218         mii = device_get_softc(sc->arge_miibus);
1219         ifp = sc->arge_ifp;
1220         if (mii == NULL || ifp == NULL ||
1221             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1222                 return;
1223         }
1224
1225         /*
1226          * If we have a static media type configured, then
1227          * use that.  Some PHY configurations (eg QCA955x -> AR8327)
1228          * use a static speed/duplex between the SoC and switch,
1229          * even though the front-facing PHY speed changes.
1230          */
1231         if (sc->arge_media_type != 0) {
1232                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: fixed; media=%d, duplex=%d\n",
1233                     __func__,
1234                     sc->arge_media_type,
1235                     sc->arge_duplex_mode);
1236                 if (mii->mii_media_status & IFM_ACTIVE) {
1237                         sc->arge_link_status = 1;
1238                 } else {
1239                         sc->arge_link_status = 0;
1240                 }
1241                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
1242         }
1243
1244         if (mii->mii_media_status & IFM_ACTIVE) {
1245
1246                 media = IFM_SUBTYPE(mii->mii_media_active);
1247                 if (media != IFM_NONE) {
1248                         sc->arge_link_status = 1;
1249                         duplex = mii->mii_media_active & IFM_GMASK;
1250                         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
1251                             __func__,
1252                             media,
1253                             duplex);
1254                         arge_set_pll(sc, media, duplex);
1255                 }
1256         } else {
1257                 sc->arge_link_status = 0;
1258         }
1259 }
1260
1261 static void
1262 arge_set_pll(struct arge_softc *sc, int media, int duplex)
1263 {
1264         uint32_t                cfg, ifcontrol, rx_filtmask;
1265         uint32_t                fifo_tx, pll;
1266         int if_speed;
1267
1268         /*
1269          * XXX Verify - is this valid for all chips?
1270          * QCA955x (and likely some of the earlier chips!) define
1271          * this as nibble mode and byte mode, and those have to do
1272          * with the interface type (MII/SMII versus GMII/RGMII.)
1273          */
1274         ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
1275             duplex == IFM_FDX ? "full" : "half");
1276         cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
1277         cfg &= ~(MAC_CFG2_IFACE_MODE_1000
1278             | MAC_CFG2_IFACE_MODE_10_100
1279             | MAC_CFG2_FULL_DUPLEX);
1280
1281         if (duplex == IFM_FDX)
1282                 cfg |= MAC_CFG2_FULL_DUPLEX;
1283
1284         ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
1285         ifcontrol &= ~MAC_IFCONTROL_SPEED;
1286         rx_filtmask =
1287             ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
1288         rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
1289
1290         switch(media) {
1291         case IFM_10_T:
1292                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1293                 if_speed = 10;
1294                 break;
1295         case IFM_100_TX:
1296                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1297                 ifcontrol |= MAC_IFCONTROL_SPEED;
1298                 if_speed = 100;
1299                 break;
1300         case IFM_1000_T:
1301         case IFM_1000_SX:
1302                 cfg |= MAC_CFG2_IFACE_MODE_1000;
1303                 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
1304                 if_speed = 1000;
1305                 break;
1306         default:
1307                 if_speed = 100;
1308                 device_printf(sc->arge_dev,
1309                     "Unknown media %d\n", media);
1310         }
1311
1312         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
1313
1314         switch (ar71xx_soc) {
1315                 case AR71XX_SOC_AR7240:
1316                 case AR71XX_SOC_AR7241:
1317                 case AR71XX_SOC_AR7242:
1318                 case AR71XX_SOC_AR9330:
1319                 case AR71XX_SOC_AR9331:
1320                 case AR71XX_SOC_AR9341:
1321                 case AR71XX_SOC_AR9342:
1322                 case AR71XX_SOC_AR9344:
1323                 case AR71XX_SOC_QCA9533:
1324                 case AR71XX_SOC_QCA9533_V2:
1325                 case AR71XX_SOC_QCA9556:
1326                 case AR71XX_SOC_QCA9558:
1327                         fifo_tx = 0x01f00140;
1328                         break;
1329                 case AR71XX_SOC_AR9130:
1330                 case AR71XX_SOC_AR9132:
1331                         fifo_tx = 0x00780fff;
1332                         break;
1333                 /* AR71xx */
1334                 default:
1335                         fifo_tx = 0x008001ff;
1336         }
1337
1338         ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
1339         ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
1340         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1341             rx_filtmask);
1342         ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
1343
1344         /* fetch PLL registers */
1345         pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
1346         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
1347
1348         /* Override if required by platform data */
1349         if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
1350                 pll = sc->arge_pllcfg.pll_10;
1351         else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
1352                 pll = sc->arge_pllcfg.pll_100;
1353         else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
1354                 pll = sc->arge_pllcfg.pll_1000;
1355         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
1356
1357         /* XXX ensure pll != 0 */
1358         ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
1359
1360         /* set MII registers */
1361         /*
1362          * This was introduced to match what the Linux ag71xx ethernet
1363          * driver does.  For the AR71xx case, it does set the port
1364          * MII speed.  However, if this is done, non-gigabit speeds
1365          * are not at all reliable when speaking via RGMII through
1366          * 'bridge' PHY port that's pretending to be a local PHY.
1367          *
1368          * Until that gets root caused, and until an AR71xx + normal
1369          * PHY board is tested, leave this disabled.
1370          */
1371 #if 0
1372         ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
1373 #endif
1374 }
1375
1376
1377 static void
1378 arge_reset_dma(struct arge_softc *sc)
1379 {
1380         uint32_t val;
1381
1382         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: called\n", __func__);
1383
1384         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
1385         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
1386
1387         /* Give hardware a chance to finish */
1388         DELAY(1000);
1389
1390         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
1391         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
1392
1393         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: RX_STATUS=%08x, TX_STATUS=%08x\n",
1394             __func__,
1395             ARGE_READ(sc, AR71XX_DMA_RX_STATUS),
1396             ARGE_READ(sc, AR71XX_DMA_TX_STATUS));
1397
1398         /* Clear all possible RX interrupts */
1399         while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
1400                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1401
1402         /*
1403          * Clear all possible TX interrupts
1404          */
1405         while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
1406                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1407
1408         /*
1409          * Now Rx/Tx errors
1410          */
1411         ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
1412             DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
1413         ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
1414             DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
1415
1416         /*
1417          * Force a DDR flush so any pending data is properly
1418          * flushed to RAM before underlying buffers are freed.
1419          */
1420         arge_flush_ddr(sc);
1421
1422         /* Check if we cleared RX status */
1423         val = ARGE_READ(sc, AR71XX_DMA_RX_STATUS);
1424         if (val != 0) {
1425                 device_printf(sc->arge_dev,
1426                     "%s: unable to clear DMA_RX_STATUS: %08x\n",
1427                     __func__, val);
1428         }
1429
1430         /* Check if we cleared TX status */
1431         val = ARGE_READ(sc, AR71XX_DMA_TX_STATUS);
1432         /* Mask out reserved bits */
1433         val = val & 0x00ffffff;
1434         if (val != 0) {
1435                 device_printf(sc->arge_dev,
1436                     "%s: unable to clear DMA_TX_STATUS: %08x\n",
1437                     __func__, val);
1438         }
1439 }
1440
1441 static void
1442 arge_init(void *xsc)
1443 {
1444         struct arge_softc        *sc = xsc;
1445
1446         ARGE_LOCK(sc);
1447         arge_init_locked(sc);
1448         ARGE_UNLOCK(sc);
1449 }
1450
1451 static void
1452 arge_init_locked(struct arge_softc *sc)
1453 {
1454         struct ifnet            *ifp = sc->arge_ifp;
1455         struct mii_data         *mii;
1456
1457         ARGE_LOCK_ASSERT(sc);
1458
1459         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: called\n", __func__);
1460
1461         if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1462                 return;
1463
1464         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: init'ing\n", __func__);
1465
1466         /* Init circular RX list. */
1467         if (arge_rx_ring_init(sc) != 0) {
1468                 device_printf(sc->arge_dev,
1469                     "initialization failed: no memory for rx buffers\n");
1470                 arge_stop(sc);
1471                 return;
1472         }
1473
1474         /* Init tx descriptors. */
1475         arge_tx_ring_init(sc);
1476
1477         /* Restart DMA */
1478         arge_reset_dma(sc);
1479
1480         if (sc->arge_miibus) {
1481                 mii = device_get_softc(sc->arge_miibus);
1482                 mii_mediachg(mii);
1483         }
1484         else {
1485                 /*
1486                  * Sun always shines over multiPHY interface
1487                  */
1488                 sc->arge_link_status = 1;
1489         }
1490
1491         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1492         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1493
1494         if (sc->arge_miibus) {
1495                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1496                 arge_update_link_locked(sc);
1497         }
1498
1499         ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: desc ring; TX=0x%x, RX=0x%x\n",
1500             __func__,
1501             ARGE_TX_RING_ADDR(sc, 0),
1502             ARGE_RX_RING_ADDR(sc, 0));
1503
1504         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1505         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1506
1507         /* Start listening */
1508         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1509
1510         /* Enable interrupts */
1511         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1512 }
1513
1514 /*
1515  * Return whether the mbuf chain is correctly aligned
1516  * for the arge TX engine.
1517  *
1518  * All the MACs have a length requirement: any non-final
1519  * fragment (ie, descriptor with MORE bit set) needs to have
1520  * a length divisible by 4.
1521  *
1522  * The AR71xx, AR913x require the start address also be
1523  * DWORD aligned.  The later MACs don't.
1524  */
1525 static int
1526 arge_mbuf_chain_is_tx_aligned(struct arge_softc *sc, struct mbuf *m0)
1527 {
1528         struct mbuf *m;
1529
1530         for (m = m0; m != NULL; m = m->m_next) {
1531                 /*
1532                  * Only do this for chips that require it.
1533                  */
1534                 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1535                     (mtod(m, intptr_t) & 3) != 0) {
1536                         sc->stats.tx_pkts_unaligned_start++;
1537                         return 0;
1538                 }
1539
1540                 /*
1541                  * All chips have this requirement for length.
1542                  */
1543                 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) {
1544                         sc->stats.tx_pkts_unaligned_len++;
1545                         return 0;
1546                 }
1547
1548                 /*
1549                  * All chips have this requirement for length being greater
1550                  * than 4.
1551                  */
1552                 if ((m->m_next != NULL) && ((m->m_len < 4))) {
1553                         sc->stats.tx_pkts_unaligned_tooshort++;
1554                         return 0;
1555                 }
1556         }
1557         return 1;
1558 }
1559
1560 /*
1561  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1562  * pointers to the fragment pointers.
1563  */
1564 static int
1565 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
1566 {
1567         struct arge_txdesc      *txd;
1568         struct arge_desc        *desc, *prev_desc;
1569         bus_dma_segment_t       txsegs[ARGE_MAXFRAGS];
1570         int                     error, i, nsegs, prod, prev_prod;
1571         struct mbuf             *m;
1572
1573         ARGE_LOCK_ASSERT(sc);
1574
1575         /*
1576          * Fix mbuf chain based on hardware alignment constraints.
1577          */
1578         m = *m_head;
1579         if (! arge_mbuf_chain_is_tx_aligned(sc, m)) {
1580                 sc->stats.tx_pkts_unaligned++;
1581                 m = m_defrag(*m_head, M_NOWAIT);
1582                 if (m == NULL) {
1583                         m_freem(*m_head);
1584                         *m_head = NULL;
1585                         return (ENOBUFS);
1586                 }
1587                 *m_head = m;
1588         } else
1589                 sc->stats.tx_pkts_aligned++;
1590
1591         prod = sc->arge_cdata.arge_tx_prod;
1592         txd = &sc->arge_cdata.arge_txdesc[prod];
1593         error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
1594             txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1595
1596         if (error == EFBIG) {
1597                 panic("EFBIG");
1598         } else if (error != 0)
1599                 return (error);
1600
1601         if (nsegs == 0) {
1602                 m_freem(*m_head);
1603                 *m_head = NULL;
1604                 return (EIO);
1605         }
1606
1607         /* Check number of available descriptors. */
1608         if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 2)) {
1609                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1610                 sc->stats.tx_pkts_nosegs++;
1611                 return (ENOBUFS);
1612         }
1613
1614         txd->tx_m = *m_head;
1615         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1616             BUS_DMASYNC_PREWRITE);
1617
1618         /*
1619          * Make a list of descriptors for this packet. DMA controller will
1620          * walk through it while arge_link is not zero.
1621          *
1622          * Since we're in a endless circular buffer, ensure that
1623          * the first descriptor in a multi-descriptor ring is always
1624          * set to EMPTY, then un-do it when we're done populating.
1625          */
1626         prev_prod = prod;
1627         desc = prev_desc = NULL;
1628         for (i = 0; i < nsegs; i++) {
1629                 uint32_t tmp;
1630
1631                 desc = &sc->arge_rdata.arge_tx_ring[prod];
1632
1633                 /*
1634                  * Set DESC_EMPTY so the hardware (hopefully) stops at this
1635                  * point.  We don't want it to start transmitting descriptors
1636                  * before we've finished fleshing this out.
1637                  */
1638                 tmp = ARGE_DMASIZE(txsegs[i].ds_len);
1639                 if (i == 0)
1640                         tmp |= ARGE_DESC_EMPTY;
1641                 desc->packet_ctrl = tmp;
1642
1643                 ARGEDEBUG(sc, ARGE_DBG_TX, " [%d / %d] addr=0x%x, len=%d\n",
1644                     i,
1645                     prod,
1646                     (uint32_t) txsegs[i].ds_addr, (int) txsegs[i].ds_len);
1647
1648                 /* XXX Note: only relevant for older MACs; but check length! */
1649                 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1650                     (txsegs[i].ds_addr & 3))
1651                         panic("TX packet address unaligned\n");
1652
1653                 desc->packet_addr = txsegs[i].ds_addr;
1654
1655                 /* link with previous descriptor */
1656                 if (prev_desc)
1657                         prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1658
1659                 sc->arge_cdata.arge_tx_cnt++;
1660                 prev_desc = desc;
1661                 ARGE_INC(prod, ARGE_TX_RING_COUNT);
1662         }
1663
1664         /* Update producer index. */
1665         sc->arge_cdata.arge_tx_prod = prod;
1666
1667         /*
1668          * The descriptors are updated, so enable the first one.
1669          */
1670         desc = &sc->arge_rdata.arge_tx_ring[prev_prod];
1671         desc->packet_ctrl &= ~ ARGE_DESC_EMPTY;
1672
1673         /* Sync descriptors. */
1674         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1675             sc->arge_cdata.arge_tx_ring_map,
1676             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1677
1678         /* Flush writes */
1679         ARGE_BARRIER_WRITE(sc);
1680
1681         /* Start transmitting */
1682         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
1683             __func__);
1684         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1685         return (0);
1686 }
1687
1688 static void
1689 arge_start(struct ifnet *ifp)
1690 {
1691         struct arge_softc        *sc;
1692
1693         sc = ifp->if_softc;
1694
1695         ARGE_LOCK(sc);
1696         arge_start_locked(ifp);
1697         ARGE_UNLOCK(sc);
1698 }
1699
1700 static void
1701 arge_start_locked(struct ifnet *ifp)
1702 {
1703         struct arge_softc       *sc;
1704         struct mbuf             *m_head;
1705         int                     enq = 0;
1706
1707         sc = ifp->if_softc;
1708
1709         ARGE_LOCK_ASSERT(sc);
1710
1711         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1712
1713         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1714             IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1715                 return;
1716
1717         /*
1718          * Before we go any further, check whether we're already full.
1719          * The below check errors out immediately if the ring is full
1720          * and never gets a chance to set this flag. Although it's
1721          * likely never needed, this at least avoids an unexpected
1722          * situation.
1723          */
1724         if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1725                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1726                 ARGEDEBUG(sc, ARGE_DBG_ERR,
1727                     "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1728                     __func__, sc->arge_cdata.arge_tx_cnt,
1729                     ARGE_TX_RING_COUNT - 2);
1730                 return;
1731         }
1732
1733         arge_flush_ddr(sc);
1734
1735         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1736             sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1737                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1738                 if (m_head == NULL)
1739                         break;
1740
1741
1742                 /*
1743                  * Pack the data into the transmit ring.
1744                  */
1745                 if (arge_encap(sc, &m_head)) {
1746                         if (m_head == NULL)
1747                                 break;
1748                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1749                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1750                         break;
1751                 }
1752
1753                 enq++;
1754                 /*
1755                  * If there's a BPF listener, bounce a copy of this frame
1756                  * to him.
1757                  */
1758                 ETHER_BPF_MTAP(ifp, m_head);
1759         }
1760         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
1761             __func__, enq);
1762 }
1763
1764 static void
1765 arge_stop(struct arge_softc *sc)
1766 {
1767         struct ifnet        *ifp;
1768
1769         ARGE_LOCK_ASSERT(sc);
1770
1771         ifp = sc->arge_ifp;
1772         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1773         if (sc->arge_miibus)
1774                 callout_stop(&sc->arge_stat_callout);
1775
1776         /* mask out interrupts */
1777         ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1778
1779         arge_reset_dma(sc);
1780
1781         /* Flush FIFO and free any existing mbufs */
1782         arge_flush_ddr(sc);
1783         arge_rx_ring_free(sc);
1784         arge_tx_ring_free(sc);
1785 }
1786
1787
1788 static int
1789 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1790 {
1791         struct arge_softc               *sc = ifp->if_softc;
1792         struct ifreq            *ifr = (struct ifreq *) data;
1793         struct mii_data         *mii;
1794         int                     error;
1795 #ifdef DEVICE_POLLING
1796         int                     mask;
1797 #endif
1798
1799         switch (command) {
1800         case SIOCSIFFLAGS:
1801                 ARGE_LOCK(sc);
1802                 if ((ifp->if_flags & IFF_UP) != 0) {
1803                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1804                                 if (((ifp->if_flags ^ sc->arge_if_flags)
1805                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1806                                         /* XXX: handle promisc & multi flags */
1807                                 }
1808
1809                         } else {
1810                                 if (!sc->arge_detach)
1811                                         arge_init_locked(sc);
1812                         }
1813                 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1814                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1815                         arge_stop(sc);
1816                 }
1817                 sc->arge_if_flags = ifp->if_flags;
1818                 ARGE_UNLOCK(sc);
1819                 error = 0;
1820                 break;
1821         case SIOCADDMULTI:
1822         case SIOCDELMULTI:
1823                 /* XXX: implement SIOCDELMULTI */
1824                 error = 0;
1825                 break;
1826         case SIOCGIFMEDIA:
1827         case SIOCSIFMEDIA:
1828                 if (sc->arge_miibus) {
1829                         mii = device_get_softc(sc->arge_miibus);
1830                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1831                             command);
1832                 }
1833                 else
1834                         error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
1835                             command);
1836                 break;
1837         case SIOCSIFCAP:
1838                 /* XXX: Check other capabilities */
1839 #ifdef DEVICE_POLLING
1840                 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1841                 if (mask & IFCAP_POLLING) {
1842                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
1843                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1844                                 error = ether_poll_register(arge_poll, ifp);
1845                                 if (error)
1846                                         return error;
1847                                 ARGE_LOCK(sc);
1848                                 ifp->if_capenable |= IFCAP_POLLING;
1849                                 ARGE_UNLOCK(sc);
1850                         } else {
1851                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1852                                 error = ether_poll_deregister(ifp);
1853                                 ARGE_LOCK(sc);
1854                                 ifp->if_capenable &= ~IFCAP_POLLING;
1855                                 ARGE_UNLOCK(sc);
1856                         }
1857                 }
1858                 error = 0;
1859                 break;
1860 #endif
1861         default:
1862                 error = ether_ioctl(ifp, command, data);
1863                 break;
1864         }
1865
1866         return (error);
1867 }
1868
1869 /*
1870  * Set media options.
1871  */
1872 static int
1873 arge_ifmedia_upd(struct ifnet *ifp)
1874 {
1875         struct arge_softc               *sc;
1876         struct mii_data         *mii;
1877         struct mii_softc        *miisc;
1878         int                     error;
1879
1880         sc = ifp->if_softc;
1881         ARGE_LOCK(sc);
1882         mii = device_get_softc(sc->arge_miibus);
1883         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1884                 PHY_RESET(miisc);
1885         error = mii_mediachg(mii);
1886         ARGE_UNLOCK(sc);
1887
1888         return (error);
1889 }
1890
1891 /*
1892  * Report current media status.
1893  */
1894 static void
1895 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1896 {
1897         struct arge_softc               *sc = ifp->if_softc;
1898         struct mii_data         *mii;
1899
1900         mii = device_get_softc(sc->arge_miibus);
1901         ARGE_LOCK(sc);
1902         mii_pollstat(mii);
1903         ifmr->ifm_active = mii->mii_media_active;
1904         ifmr->ifm_status = mii->mii_media_status;
1905         ARGE_UNLOCK(sc);
1906 }
1907
1908 struct arge_dmamap_arg {
1909         bus_addr_t      arge_busaddr;
1910 };
1911
1912 static void
1913 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1914 {
1915         struct arge_dmamap_arg  *ctx;
1916
1917         if (error != 0)
1918                 return;
1919         ctx = arg;
1920         ctx->arge_busaddr = segs[0].ds_addr;
1921 }
1922
1923 static int
1924 arge_dma_alloc(struct arge_softc *sc)
1925 {
1926         struct arge_dmamap_arg  ctx;
1927         struct arge_txdesc      *txd;
1928         struct arge_rxdesc      *rxd;
1929         int                     error, i;
1930         int                     arge_tx_align, arge_rx_align;
1931
1932         /* Assume 4 byte alignment by default */
1933         arge_tx_align = 4;
1934         arge_rx_align = 4;
1935
1936         if (sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE)
1937                 arge_tx_align = 1;
1938         if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
1939                 arge_rx_align = 1;
1940
1941         /* Create parent DMA tag. */
1942         error = bus_dma_tag_create(
1943             bus_get_dma_tag(sc->arge_dev),      /* parent */
1944             1, 0,                       /* alignment, boundary */
1945             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1946             BUS_SPACE_MAXADDR,          /* highaddr */
1947             NULL, NULL,                 /* filter, filterarg */
1948             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1949             0,                          /* nsegments */
1950             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1951             0,                          /* flags */
1952             NULL, NULL,                 /* lockfunc, lockarg */
1953             &sc->arge_cdata.arge_parent_tag);
1954         if (error != 0) {
1955                 device_printf(sc->arge_dev,
1956                     "failed to create parent DMA tag\n");
1957                 goto fail;
1958         }
1959         /* Create tag for Tx ring. */
1960         error = bus_dma_tag_create(
1961             sc->arge_cdata.arge_parent_tag,     /* parent */
1962             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1963             BUS_SPACE_MAXADDR,          /* lowaddr */
1964             BUS_SPACE_MAXADDR,          /* highaddr */
1965             NULL, NULL,                 /* filter, filterarg */
1966             ARGE_TX_DMA_SIZE,           /* maxsize */
1967             1,                          /* nsegments */
1968             ARGE_TX_DMA_SIZE,           /* maxsegsize */
1969             0,                          /* flags */
1970             NULL, NULL,                 /* lockfunc, lockarg */
1971             &sc->arge_cdata.arge_tx_ring_tag);
1972         if (error != 0) {
1973                 device_printf(sc->arge_dev,
1974                     "failed to create Tx ring DMA tag\n");
1975                 goto fail;
1976         }
1977
1978         /* Create tag for Rx ring. */
1979         error = bus_dma_tag_create(
1980             sc->arge_cdata.arge_parent_tag,     /* parent */
1981             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1982             BUS_SPACE_MAXADDR,          /* lowaddr */
1983             BUS_SPACE_MAXADDR,          /* highaddr */
1984             NULL, NULL,                 /* filter, filterarg */
1985             ARGE_RX_DMA_SIZE,           /* maxsize */
1986             1,                          /* nsegments */
1987             ARGE_RX_DMA_SIZE,           /* maxsegsize */
1988             0,                          /* flags */
1989             NULL, NULL,                 /* lockfunc, lockarg */
1990             &sc->arge_cdata.arge_rx_ring_tag);
1991         if (error != 0) {
1992                 device_printf(sc->arge_dev,
1993                     "failed to create Rx ring DMA tag\n");
1994                 goto fail;
1995         }
1996
1997         /* Create tag for Tx buffers. */
1998         error = bus_dma_tag_create(
1999             sc->arge_cdata.arge_parent_tag,     /* parent */
2000             arge_tx_align, 0,           /* alignment, boundary */
2001             BUS_SPACE_MAXADDR,          /* lowaddr */
2002             BUS_SPACE_MAXADDR,          /* highaddr */
2003             NULL, NULL,                 /* filter, filterarg */
2004             MCLBYTES * ARGE_MAXFRAGS,   /* maxsize */
2005             ARGE_MAXFRAGS,              /* nsegments */
2006             MCLBYTES,                   /* maxsegsize */
2007             0,                          /* flags */
2008             NULL, NULL,                 /* lockfunc, lockarg */
2009             &sc->arge_cdata.arge_tx_tag);
2010         if (error != 0) {
2011                 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
2012                 goto fail;
2013         }
2014
2015         /* Create tag for Rx buffers. */
2016         error = bus_dma_tag_create(
2017             sc->arge_cdata.arge_parent_tag,     /* parent */
2018             arge_rx_align, 0,           /* alignment, boundary */
2019             BUS_SPACE_MAXADDR,          /* lowaddr */
2020             BUS_SPACE_MAXADDR,          /* highaddr */
2021             NULL, NULL,                 /* filter, filterarg */
2022             MCLBYTES,                   /* maxsize */
2023             ARGE_MAXFRAGS,              /* nsegments */
2024             MCLBYTES,                   /* maxsegsize */
2025             0,                          /* flags */
2026             NULL, NULL,                 /* lockfunc, lockarg */
2027             &sc->arge_cdata.arge_rx_tag);
2028         if (error != 0) {
2029                 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
2030                 goto fail;
2031         }
2032
2033         /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2034         error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
2035             (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
2036             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2037             &sc->arge_cdata.arge_tx_ring_map);
2038         if (error != 0) {
2039                 device_printf(sc->arge_dev,
2040                     "failed to allocate DMA'able memory for Tx ring\n");
2041                 goto fail;
2042         }
2043
2044         ctx.arge_busaddr = 0;
2045         error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
2046             sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
2047             ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
2048         if (error != 0 || ctx.arge_busaddr == 0) {
2049                 device_printf(sc->arge_dev,
2050                     "failed to load DMA'able memory for Tx ring\n");
2051                 goto fail;
2052         }
2053         sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
2054
2055         /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2056         error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
2057             (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
2058             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2059             &sc->arge_cdata.arge_rx_ring_map);
2060         if (error != 0) {
2061                 device_printf(sc->arge_dev,
2062                     "failed to allocate DMA'able memory for Rx ring\n");
2063                 goto fail;
2064         }
2065
2066         ctx.arge_busaddr = 0;
2067         error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
2068             sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
2069             ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
2070         if (error != 0 || ctx.arge_busaddr == 0) {
2071                 device_printf(sc->arge_dev,
2072                     "failed to load DMA'able memory for Rx ring\n");
2073                 goto fail;
2074         }
2075         sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
2076
2077         /* Create DMA maps for Tx buffers. */
2078         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2079                 txd = &sc->arge_cdata.arge_txdesc[i];
2080                 txd->tx_m = NULL;
2081                 txd->tx_dmamap = NULL;
2082                 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
2083                     &txd->tx_dmamap);
2084                 if (error != 0) {
2085                         device_printf(sc->arge_dev,
2086                             "failed to create Tx dmamap\n");
2087                         goto fail;
2088                 }
2089         }
2090         /* Create DMA maps for Rx buffers. */
2091         if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
2092             &sc->arge_cdata.arge_rx_sparemap)) != 0) {
2093                 device_printf(sc->arge_dev,
2094                     "failed to create spare Rx dmamap\n");
2095                 goto fail;
2096         }
2097         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2098                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2099                 rxd->rx_m = NULL;
2100                 rxd->rx_dmamap = NULL;
2101                 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
2102                     &rxd->rx_dmamap);
2103                 if (error != 0) {
2104                         device_printf(sc->arge_dev,
2105                             "failed to create Rx dmamap\n");
2106                         goto fail;
2107                 }
2108         }
2109
2110 fail:
2111         return (error);
2112 }
2113
2114 static void
2115 arge_dma_free(struct arge_softc *sc)
2116 {
2117         struct arge_txdesc      *txd;
2118         struct arge_rxdesc      *rxd;
2119         int                     i;
2120
2121         /* Tx ring. */
2122         if (sc->arge_cdata.arge_tx_ring_tag) {
2123                 if (sc->arge_rdata.arge_tx_ring_paddr)
2124                         bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
2125                             sc->arge_cdata.arge_tx_ring_map);
2126                 if (sc->arge_rdata.arge_tx_ring)
2127                         bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
2128                             sc->arge_rdata.arge_tx_ring,
2129                             sc->arge_cdata.arge_tx_ring_map);
2130                 sc->arge_rdata.arge_tx_ring = NULL;
2131                 sc->arge_rdata.arge_tx_ring_paddr = 0;
2132                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
2133                 sc->arge_cdata.arge_tx_ring_tag = NULL;
2134         }
2135         /* Rx ring. */
2136         if (sc->arge_cdata.arge_rx_ring_tag) {
2137                 if (sc->arge_rdata.arge_rx_ring_paddr)
2138                         bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
2139                             sc->arge_cdata.arge_rx_ring_map);
2140                 if (sc->arge_rdata.arge_rx_ring)
2141                         bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
2142                             sc->arge_rdata.arge_rx_ring,
2143                             sc->arge_cdata.arge_rx_ring_map);
2144                 sc->arge_rdata.arge_rx_ring = NULL;
2145                 sc->arge_rdata.arge_rx_ring_paddr = 0;
2146                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
2147                 sc->arge_cdata.arge_rx_ring_tag = NULL;
2148         }
2149         /* Tx buffers. */
2150         if (sc->arge_cdata.arge_tx_tag) {
2151                 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2152                         txd = &sc->arge_cdata.arge_txdesc[i];
2153                         if (txd->tx_dmamap) {
2154                                 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
2155                                     txd->tx_dmamap);
2156                                 txd->tx_dmamap = NULL;
2157                         }
2158                 }
2159                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
2160                 sc->arge_cdata.arge_tx_tag = NULL;
2161         }
2162         /* Rx buffers. */
2163         if (sc->arge_cdata.arge_rx_tag) {
2164                 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2165                         rxd = &sc->arge_cdata.arge_rxdesc[i];
2166                         if (rxd->rx_dmamap) {
2167                                 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
2168                                     rxd->rx_dmamap);
2169                                 rxd->rx_dmamap = NULL;
2170                         }
2171                 }
2172                 if (sc->arge_cdata.arge_rx_sparemap) {
2173                         bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
2174                             sc->arge_cdata.arge_rx_sparemap);
2175                         sc->arge_cdata.arge_rx_sparemap = 0;
2176                 }
2177                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
2178                 sc->arge_cdata.arge_rx_tag = NULL;
2179         }
2180
2181         if (sc->arge_cdata.arge_parent_tag) {
2182                 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
2183                 sc->arge_cdata.arge_parent_tag = NULL;
2184         }
2185 }
2186
2187 /*
2188  * Initialize the transmit descriptors.
2189  */
2190 static int
2191 arge_tx_ring_init(struct arge_softc *sc)
2192 {
2193         struct arge_ring_data   *rd;
2194         struct arge_txdesc      *txd;
2195         bus_addr_t              addr;
2196         int                     i;
2197
2198         sc->arge_cdata.arge_tx_prod = 0;
2199         sc->arge_cdata.arge_tx_cons = 0;
2200         sc->arge_cdata.arge_tx_cnt = 0;
2201
2202         rd = &sc->arge_rdata;
2203         bzero(rd->arge_tx_ring, sizeof(*rd->arge_tx_ring));
2204         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2205                 if (i == ARGE_TX_RING_COUNT - 1)
2206                         addr = ARGE_TX_RING_ADDR(sc, 0);
2207                 else
2208                         addr = ARGE_TX_RING_ADDR(sc, i + 1);
2209                 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
2210                 rd->arge_tx_ring[i].next_desc = addr;
2211                 txd = &sc->arge_cdata.arge_txdesc[i];
2212                 txd->tx_m = NULL;
2213         }
2214
2215         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2216             sc->arge_cdata.arge_tx_ring_map,
2217             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2218
2219         return (0);
2220 }
2221
2222 /*
2223  * Free the Tx ring, unload any pending dma transaction and free the mbuf.
2224  */
2225 static void
2226 arge_tx_ring_free(struct arge_softc *sc)
2227 {
2228         struct arge_txdesc      *txd;
2229         int                     i;
2230
2231         /* Free the Tx buffers. */
2232         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
2233                 txd = &sc->arge_cdata.arge_txdesc[i];
2234                 if (txd->tx_dmamap) {
2235                         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag,
2236                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2237                         bus_dmamap_unload(sc->arge_cdata.arge_tx_tag,
2238                             txd->tx_dmamap);
2239                 }
2240                 if (txd->tx_m)
2241                         m_freem(txd->tx_m);
2242                 txd->tx_m = NULL;
2243         }
2244 }
2245
2246 /*
2247  * Initialize the RX descriptors and allocate mbufs for them. Note that
2248  * we arrange the descriptors in a closed ring, so that the last descriptor
2249  * points back to the first.
2250  */
2251 static int
2252 arge_rx_ring_init(struct arge_softc *sc)
2253 {
2254         struct arge_ring_data   *rd;
2255         struct arge_rxdesc      *rxd;
2256         bus_addr_t              addr;
2257         int                     i;
2258
2259         sc->arge_cdata.arge_rx_cons = 0;
2260
2261         rd = &sc->arge_rdata;
2262         bzero(rd->arge_rx_ring, sizeof(*rd->arge_rx_ring));
2263         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2264                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2265                 if (rxd->rx_m != NULL) {
2266                         device_printf(sc->arge_dev,
2267                             "%s: ring[%d] rx_m wasn't free?\n",
2268                             __func__,
2269                             i);
2270                 }
2271                 rxd->rx_m = NULL;
2272                 rxd->desc = &rd->arge_rx_ring[i];
2273                 if (i == ARGE_RX_RING_COUNT - 1)
2274                         addr = ARGE_RX_RING_ADDR(sc, 0);
2275                 else
2276                         addr = ARGE_RX_RING_ADDR(sc, i + 1);
2277                 rd->arge_rx_ring[i].next_desc = addr;
2278                 if (arge_newbuf(sc, i) != 0) {
2279                         return (ENOBUFS);
2280                 }
2281         }
2282
2283         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2284             sc->arge_cdata.arge_rx_ring_map,
2285             BUS_DMASYNC_PREWRITE);
2286
2287         return (0);
2288 }
2289
2290 /*
2291  * Free all the buffers in the RX ring.
2292  *
2293  * TODO: ensure that DMA is disabled and no pending DMA
2294  * is lurking in the FIFO.
2295  */
2296 static void
2297 arge_rx_ring_free(struct arge_softc *sc)
2298 {
2299         int i;
2300         struct arge_rxdesc      *rxd;
2301
2302         ARGE_LOCK_ASSERT(sc);
2303
2304         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2305                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2306                 /* Unmap the mbuf */
2307                 if (rxd->rx_m != NULL) {
2308                         bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
2309                             rxd->rx_dmamap);
2310                         m_free(rxd->rx_m);
2311                         rxd->rx_m = NULL;
2312                 }
2313         }
2314 }
2315
2316 /*
2317  * Initialize an RX descriptor and attach an MBUF cluster.
2318  */
2319 static int
2320 arge_newbuf(struct arge_softc *sc, int idx)
2321 {
2322         struct arge_desc                *desc;
2323         struct arge_rxdesc      *rxd;
2324         struct mbuf             *m;
2325         bus_dma_segment_t       segs[1];
2326         bus_dmamap_t            map;
2327         int                     nsegs;
2328
2329         /* XXX TODO: should just allocate an explicit 2KiB buffer */
2330         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2331         if (m == NULL)
2332                 return (ENOBUFS);
2333         m->m_len = m->m_pkthdr.len = MCLBYTES;
2334
2335         /*
2336          * Add extra space to "adjust" (copy) the packet back to be aligned
2337          * for purposes of IPv4/IPv6 header contents.
2338          */
2339         if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE)
2340                 m_adj(m, sizeof(uint64_t));
2341         /*
2342          * If it's a 1-byte aligned buffer, then just offset it two bytes
2343          * and that will give us a hopefully correctly DWORD aligned
2344          * L3 payload - and we won't have to undo it afterwards.
2345          */
2346         else if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
2347                 m_adj(m, sizeof(uint16_t));
2348
2349         if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2350             sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2351                 m_freem(m);
2352                 return (ENOBUFS);
2353         }
2354         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2355
2356         rxd = &sc->arge_cdata.arge_rxdesc[idx];
2357         if (rxd->rx_m != NULL) {
2358                 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2359         }
2360         map = rxd->rx_dmamap;
2361         rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2362         sc->arge_cdata.arge_rx_sparemap = map;
2363         rxd->rx_m = m;
2364         desc = rxd->desc;
2365         if ((sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE) &&
2366             segs[0].ds_addr & 3)
2367                 panic("RX packet address unaligned");
2368         desc->packet_addr = segs[0].ds_addr;
2369         desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2370
2371         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2372             sc->arge_cdata.arge_rx_ring_map,
2373             BUS_DMASYNC_PREWRITE);
2374
2375         return (0);
2376 }
2377
2378 /*
2379  * Move the data backwards 16 bits to (hopefully!) ensure the
2380  * IPv4/IPv6 payload is aligned.
2381  *
2382  * This is required for earlier hardware where the RX path
2383  * requires DWORD aligned buffers.
2384  */
2385 static __inline void
2386 arge_fixup_rx(struct mbuf *m)
2387 {
2388         int             i;
2389         uint16_t        *src, *dst;
2390
2391         src = mtod(m, uint16_t *);
2392         dst = src - 1;
2393
2394         for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
2395                 *dst++ = *src++;
2396         }
2397
2398         if (m->m_len % sizeof(uint16_t))
2399                 *(uint8_t *)dst = *(uint8_t *)src;
2400
2401         m->m_data -= ETHER_ALIGN;
2402 }
2403
2404 #ifdef DEVICE_POLLING
2405 static int
2406 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2407 {
2408         struct arge_softc *sc = ifp->if_softc;
2409         int rx_npkts = 0;
2410
2411         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2412                 ARGE_LOCK(sc);
2413                 arge_tx_locked(sc);
2414                 rx_npkts = arge_rx_locked(sc);
2415                 ARGE_UNLOCK(sc);
2416         }
2417
2418         return (rx_npkts);
2419 }
2420 #endif /* DEVICE_POLLING */
2421
2422
2423 static void
2424 arge_tx_locked(struct arge_softc *sc)
2425 {
2426         struct arge_txdesc      *txd;
2427         struct arge_desc        *cur_tx;
2428         struct ifnet            *ifp;
2429         uint32_t                ctrl;
2430         int                     cons, prod;
2431
2432         ARGE_LOCK_ASSERT(sc);
2433
2434         cons = sc->arge_cdata.arge_tx_cons;
2435         prod = sc->arge_cdata.arge_tx_prod;
2436
2437         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
2438             prod);
2439
2440         if (cons == prod)
2441                 return;
2442
2443         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2444             sc->arge_cdata.arge_tx_ring_map,
2445             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2446
2447         ifp = sc->arge_ifp;
2448         /*
2449          * Go through our tx list and free mbufs for those
2450          * frames that have been transmitted.
2451          */
2452         for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
2453                 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
2454                 ctrl = cur_tx->packet_ctrl;
2455                 /* Check if descriptor has "finished" flag */
2456                 if ((ctrl & ARGE_DESC_EMPTY) == 0)
2457                         break;
2458
2459                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
2460
2461                 sc->arge_cdata.arge_tx_cnt--;
2462                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2463
2464                 txd = &sc->arge_cdata.arge_txdesc[cons];
2465
2466                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2467
2468                 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
2469                     BUS_DMASYNC_POSTWRITE);
2470                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
2471
2472                 /* Free only if it's first descriptor in list */
2473                 if (txd->tx_m)
2474                         m_freem(txd->tx_m);
2475                 txd->tx_m = NULL;
2476
2477                 /* reset descriptor */
2478                 cur_tx->packet_addr = 0;
2479         }
2480
2481         sc->arge_cdata.arge_tx_cons = cons;
2482
2483         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2484             sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
2485 }
2486
2487
2488 static int
2489 arge_rx_locked(struct arge_softc *sc)
2490 {
2491         struct arge_rxdesc      *rxd;
2492         struct ifnet            *ifp = sc->arge_ifp;
2493         int                     cons, prog, packet_len, i;
2494         struct arge_desc        *cur_rx;
2495         struct mbuf             *m;
2496         int                     rx_npkts = 0;
2497
2498         ARGE_LOCK_ASSERT(sc);
2499
2500         cons = sc->arge_cdata.arge_rx_cons;
2501
2502         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2503             sc->arge_cdata.arge_rx_ring_map,
2504             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2505
2506         for (prog = 0; prog < ARGE_RX_RING_COUNT;
2507             ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
2508                 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
2509                 rxd = &sc->arge_cdata.arge_rxdesc[cons];
2510                 m = rxd->rx_m;
2511
2512                 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
2513                        break;
2514
2515                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
2516
2517                 prog++;
2518
2519                 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
2520                 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
2521                     BUS_DMASYNC_POSTREAD);
2522                 m = rxd->rx_m;
2523
2524                 /*
2525                  * If the MAC requires 4 byte alignment then the RX setup
2526                  * routine will have pre-offset things; so un-offset it here.
2527                  */
2528                 if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE)
2529                         arge_fixup_rx(m);
2530
2531                 m->m_pkthdr.rcvif = ifp;
2532                 /* Skip 4 bytes of CRC */
2533                 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
2534                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2535                 rx_npkts++;
2536
2537                 ARGE_UNLOCK(sc);
2538                 (*ifp->if_input)(ifp, m);
2539                 ARGE_LOCK(sc);
2540                 cur_rx->packet_addr = 0;
2541         }
2542
2543         if (prog > 0) {
2544
2545                 i = sc->arge_cdata.arge_rx_cons;
2546                 for (; prog > 0 ; prog--) {
2547                         if (arge_newbuf(sc, i) != 0) {
2548                                 device_printf(sc->arge_dev,
2549                                     "Failed to allocate buffer\n");
2550                                 break;
2551                         }
2552                         ARGE_INC(i, ARGE_RX_RING_COUNT);
2553                 }
2554
2555                 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2556                     sc->arge_cdata.arge_rx_ring_map,
2557                     BUS_DMASYNC_PREWRITE);
2558
2559                 sc->arge_cdata.arge_rx_cons = cons;
2560         }
2561
2562         return (rx_npkts);
2563 }
2564
2565 static int
2566 arge_intr_filter(void *arg)
2567 {
2568         struct arge_softc       *sc = arg;
2569         uint32_t                status, ints;
2570
2571         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2572         ints = ARGE_READ(sc, AR71XX_DMA_INTR);
2573
2574         ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
2575             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2576             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2577         ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2578             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2579             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2580
2581         if (status & DMA_INTR_ALL) {
2582                 sc->arge_intr_status |= status;
2583                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2584                 sc->stats.intr_ok++;
2585                 return (FILTER_SCHEDULE_THREAD);
2586         }
2587
2588         sc->arge_intr_status = 0;
2589         sc->stats.intr_stray++;
2590         return (FILTER_STRAY);
2591 }
2592
2593 static void
2594 arge_intr(void *arg)
2595 {
2596         struct arge_softc       *sc = arg;
2597         uint32_t                status;
2598         struct ifnet            *ifp = sc->arge_ifp;
2599 #ifdef  ARGE_DEBUG
2600         int i;
2601 #endif
2602
2603         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2604         status |= sc->arge_intr_status;
2605
2606         ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2607             "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2608             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2609
2610         /*
2611          * Is it our interrupt at all?
2612          */
2613         if (status == 0) {
2614                 sc->stats.intr_stray2++;
2615                 return;
2616         }
2617
2618 #ifdef  ARGE_DEBUG
2619         for (i = 0; i < 32; i++) {
2620                 if (status & (1U << i)) {
2621                         sc->intr_stats.count[i]++;
2622                 }
2623         }
2624 #endif
2625
2626         if (status & DMA_INTR_RX_BUS_ERROR) {
2627                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2628                 device_printf(sc->arge_dev, "RX bus error");
2629                 return;
2630         }
2631
2632         if (status & DMA_INTR_TX_BUS_ERROR) {
2633                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2634                 device_printf(sc->arge_dev, "TX bus error");
2635                 return;
2636         }
2637
2638         ARGE_LOCK(sc);
2639         arge_flush_ddr(sc);
2640
2641         if (status & DMA_INTR_RX_PKT_RCVD)
2642                 arge_rx_locked(sc);
2643
2644         /*
2645          * RX overrun disables the receiver.
2646          * Clear indication and re-enable rx.
2647          */
2648         if ( status & DMA_INTR_RX_OVERFLOW) {
2649                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2650                 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2651                 sc->stats.rx_overflow++;
2652         }
2653
2654         if (status & DMA_INTR_TX_PKT_SENT)
2655                 arge_tx_locked(sc);
2656         /*
2657          * Underrun turns off TX. Clear underrun indication.
2658          * If there's anything left in the ring, reactivate the tx.
2659          */
2660         if (status & DMA_INTR_TX_UNDERRUN) {
2661                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2662                 sc->stats.tx_underflow++;
2663                 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
2664                     __func__, sc->arge_cdata.arge_tx_cnt);
2665                 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
2666                         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2667                             DMA_TX_CONTROL_EN);
2668                 }
2669         }
2670
2671         /*
2672          * If we've finished RX /or/ TX and there's space for more packets
2673          * to be queued for TX, do so. Otherwise we may end up in a
2674          * situation where the interface send queue was filled
2675          * whilst the hardware queue was full, then the hardware
2676          * queue was drained by the interface send queue wasn't,
2677          * and thus if_start() is never called to kick-start
2678          * the send process (and all subsequent packets are simply
2679          * discarded.
2680          *
2681          * XXX TODO: make sure that the hardware deals nicely
2682          * with the possibility of the queue being enabled above
2683          * after a TX underrun, then having the hardware queue added
2684          * to below.
2685          */
2686          if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2687                 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2688                         arge_start_locked(ifp);
2689         }
2690
2691         /*
2692          * We handled all bits, clear status
2693          */
2694         sc->arge_intr_status = 0;
2695         ARGE_UNLOCK(sc);
2696         /*
2697          * re-enable all interrupts
2698          */
2699         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2700 }
2701
2702
2703 static void
2704 arge_tick(void *xsc)
2705 {
2706         struct arge_softc       *sc = xsc;
2707         struct mii_data         *mii;
2708
2709         ARGE_LOCK_ASSERT(sc);
2710
2711         if (sc->arge_miibus) {
2712                 mii = device_get_softc(sc->arge_miibus);
2713                 mii_tick(mii);
2714                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
2715         }
2716 }
2717
2718 int
2719 arge_multiphy_mediachange(struct ifnet *ifp)
2720 {
2721         struct arge_softc *sc = ifp->if_softc;
2722         struct ifmedia *ifm = &sc->arge_ifmedia;
2723         struct ifmedia_entry *ife = ifm->ifm_cur;
2724
2725         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2726                 return (EINVAL);
2727
2728         if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
2729                 device_printf(sc->arge_dev,
2730                     "AUTO is not supported for multiphy MAC");
2731                 return (EINVAL);
2732         }
2733
2734         /*
2735          * Ignore everything
2736          */
2737         return (0);
2738 }
2739
2740 void
2741 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2742 {
2743         struct arge_softc *sc = ifp->if_softc;
2744
2745         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2746         ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
2747             sc->arge_duplex_mode;
2748 }
2749
2750 #if defined(ARGE_MDIO)
2751 static int
2752 argemdio_probe(device_t dev)
2753 {
2754         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
2755         return (0);
2756 }
2757
2758 static int
2759 argemdio_attach(device_t dev)
2760 {
2761         struct arge_softc       *sc;
2762         int                     error = 0;
2763 #ifdef  ARGE_DEBUG
2764         struct sysctl_ctx_list *ctx;
2765         struct sysctl_oid *tree;
2766 #endif
2767         sc = device_get_softc(dev);
2768         sc->arge_dev = dev;
2769         sc->arge_mac_unit = device_get_unit(dev);
2770         sc->arge_rid = 0;
2771         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2772             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
2773         if (sc->arge_res == NULL) {
2774                 device_printf(dev, "couldn't map memory\n");
2775                 error = ENXIO;
2776                 goto fail;
2777         }
2778
2779 #ifdef  ARGE_DEBUG
2780         ctx = device_get_sysctl_ctx(dev);
2781         tree = device_get_sysctl_tree(dev);
2782         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2783                 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
2784                 "argemdio interface debugging flags");
2785 #endif
2786
2787         /* Reset MAC - required for AR71xx MDIO to successfully occur */
2788         arge_reset_mac(sc);
2789         /* Reset MII bus */
2790         arge_reset_miibus(sc);
2791
2792         bus_generic_probe(dev);
2793         bus_enumerate_hinted_children(dev);
2794         error = bus_generic_attach(dev);
2795 fail:
2796         return (error);
2797 }
2798
2799 static int
2800 argemdio_detach(device_t dev)
2801 {
2802         return (0);
2803 }
2804
2805 #endif