2 * Copyright (c) 2009, Oleksandr Tymoshenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * AR71XX gigabit ethernet driver
34 #ifdef HAVE_KERNEL_OPTION_HEADERS
35 #include "opt_device_polling.h"
40 #include <sys/param.h>
41 #include <sys/endian.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/taskqueue.h>
50 #include <sys/sysctl.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
61 #include <machine/bus.h>
62 #include <machine/cache.h>
63 #include <machine/resource.h>
64 #include <vm/vm_param.h>
67 #include <machine/pmap.h>
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
79 #if defined(ARGE_MDIO)
80 #include <dev/etherswitch/mdio.h>
81 #include <dev/etherswitch/miiproxy.h>
86 MODULE_DEPEND(arge, ether, 1, 1, 1);
87 MODULE_DEPEND(arge, miibus, 1, 1, 1);
88 MODULE_VERSION(arge, 1);
90 #include "miibus_if.h"
92 #include <mips/atheros/ar71xxreg.h>
93 #include <mips/atheros/if_argevar.h>
94 #include <mips/atheros/ar71xx_setup.h>
95 #include <mips/atheros/ar71xx_cpudef.h>
98 ARGE_DBG_MII = 0x00000001,
99 ARGE_DBG_INTR = 0x00000002,
100 ARGE_DBG_TX = 0x00000004,
101 ARGE_DBG_RX = 0x00000008,
102 ARGE_DBG_ERR = 0x00000010,
103 ARGE_DBG_RESET = 0x00000020,
104 ARGE_DBG_PLL = 0x00000040,
107 static const char * arge_miicfg_str[] = {
116 #define ARGEDEBUG(_sc, _m, ...) \
118 if ((_m) & (_sc)->arge_debug) \
119 device_printf((_sc)->arge_dev, __VA_ARGS__); \
122 #define ARGEDEBUG(_sc, _m, ...)
125 static int arge_attach(device_t);
126 static int arge_detach(device_t);
127 static void arge_flush_ddr(struct arge_softc *);
128 static int arge_ifmedia_upd(struct ifnet *);
129 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
130 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
131 static void arge_init(void *);
132 static void arge_init_locked(struct arge_softc *);
133 static void arge_link_task(void *, int);
134 static void arge_update_link_locked(struct arge_softc *sc);
135 static void arge_set_pll(struct arge_softc *, int, int);
136 static int arge_miibus_readreg(device_t, int, int);
137 static void arge_miibus_statchg(device_t);
138 static int arge_miibus_writereg(device_t, int, int, int);
139 static int arge_probe(device_t);
140 static void arge_reset_dma(struct arge_softc *);
141 static int arge_resume(device_t);
142 static int arge_rx_ring_init(struct arge_softc *);
143 static void arge_rx_ring_free(struct arge_softc *sc);
144 static int arge_tx_ring_init(struct arge_softc *);
145 #ifdef DEVICE_POLLING
146 static int arge_poll(struct ifnet *, enum poll_cmd, int);
148 static int arge_shutdown(device_t);
149 static void arge_start(struct ifnet *);
150 static void arge_start_locked(struct ifnet *);
151 static void arge_stop(struct arge_softc *);
152 static int arge_suspend(device_t);
154 static int arge_rx_locked(struct arge_softc *);
155 static void arge_tx_locked(struct arge_softc *);
156 static void arge_intr(void *);
157 static int arge_intr_filter(void *);
158 static void arge_tick(void *);
160 static void arge_hinted_child(device_t bus, const char *dname, int dunit);
163 * ifmedia callbacks for multiPHY MAC
165 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
166 int arge_multiphy_mediachange(struct ifnet *);
168 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
169 static int arge_dma_alloc(struct arge_softc *);
170 static void arge_dma_free(struct arge_softc *);
171 static int arge_newbuf(struct arge_softc *, int);
172 static __inline void arge_fixup_rx(struct mbuf *);
174 static device_method_t arge_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_probe, arge_probe),
177 DEVMETHOD(device_attach, arge_attach),
178 DEVMETHOD(device_detach, arge_detach),
179 DEVMETHOD(device_suspend, arge_suspend),
180 DEVMETHOD(device_resume, arge_resume),
181 DEVMETHOD(device_shutdown, arge_shutdown),
184 DEVMETHOD(miibus_readreg, arge_miibus_readreg),
185 DEVMETHOD(miibus_writereg, arge_miibus_writereg),
186 DEVMETHOD(miibus_statchg, arge_miibus_statchg),
189 DEVMETHOD(bus_add_child, device_add_child_ordered),
190 DEVMETHOD(bus_hinted_child, arge_hinted_child),
195 static driver_t arge_driver = {
198 sizeof(struct arge_softc)
201 static devclass_t arge_devclass;
203 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
204 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
206 #if defined(ARGE_MDIO)
207 static int argemdio_probe(device_t);
208 static int argemdio_attach(device_t);
209 static int argemdio_detach(device_t);
212 * Declare an additional, separate driver for accessing the MDIO bus.
214 static device_method_t argemdio_methods[] = {
215 /* Device interface */
216 DEVMETHOD(device_probe, argemdio_probe),
217 DEVMETHOD(device_attach, argemdio_attach),
218 DEVMETHOD(device_detach, argemdio_detach),
221 DEVMETHOD(bus_add_child, device_add_child_ordered),
224 DEVMETHOD(mdio_readreg, arge_miibus_readreg),
225 DEVMETHOD(mdio_writereg, arge_miibus_writereg),
228 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
229 sizeof(struct arge_softc));
230 static devclass_t argemdio_devclass;
232 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
233 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
234 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
238 * RedBoot passes MAC address to entry point as environment
239 * variable. platfrom_start parses it and stores in this variable
241 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
243 static struct mtx miibus_mtx;
245 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
251 arge_flush_ddr(struct arge_softc *sc)
254 ar71xx_device_flush_ddr_ge(sc->arge_mac_unit);
258 arge_probe(device_t dev)
261 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
266 arge_attach_sysctl(device_t dev)
268 struct arge_softc *sc = device_get_softc(dev);
269 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
270 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
273 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
274 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
275 "arge interface debugging flags");
278 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
279 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
280 "number of TX aligned packets");
282 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
283 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
284 0, "number of TX unaligned packets");
287 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
288 CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
289 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
290 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
291 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
292 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
297 arge_reset_mac(struct arge_softc *sc)
301 /* Step 1. Soft-reset MAC */
302 ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
305 /* Step 2. Punt the MAC core from the central reset register */
306 ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC :
309 ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC :
312 /* Step 3. Reconfigure MAC block */
313 ARGE_WRITE(sc, AR71XX_MAC_CFG1,
314 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
315 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
317 reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
318 reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
319 ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
321 ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
325 arge_reset_miibus(struct arge_softc *sc)
329 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET);
331 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28);
336 arge_fetch_pll_config(struct arge_softc *sc)
340 if (resource_long_value(device_get_name(sc->arge_dev),
341 device_get_unit(sc->arge_dev),
342 "pll_10", &val) == 0) {
343 sc->arge_pllcfg.pll_10 = val;
344 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
345 __func__, (int) val);
347 if (resource_long_value(device_get_name(sc->arge_dev),
348 device_get_unit(sc->arge_dev),
349 "pll_100", &val) == 0) {
350 sc->arge_pllcfg.pll_100 = val;
351 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
352 __func__, (int) val);
354 if (resource_long_value(device_get_name(sc->arge_dev),
355 device_get_unit(sc->arge_dev),
356 "pll_1000", &val) == 0) {
357 sc->arge_pllcfg.pll_1000 = val;
358 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
359 __func__, (int) val);
364 arge_attach(device_t dev)
367 struct arge_softc *sc;
370 int is_base_mac_empty, i;
372 long eeprom_mac_addr = 0;
375 sc = device_get_softc(dev);
377 sc->arge_mac_unit = device_get_unit(dev);
380 * Some units (eg the TP-Link WR-1043ND) do not have a convenient
381 * EEPROM location to read the ethernet MAC address from.
382 * OpenWRT simply snaffles it from a fixed location.
384 * Since multiple units seem to use this feature, include
385 * a method of setting the MAC address based on an flash location
386 * in CPU address space.
388 if (sc->arge_mac_unit == 0 &&
389 resource_long_value(device_get_name(dev), device_get_unit(dev),
390 "eeprommac", &eeprom_mac_addr) == 0) {
393 (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
394 device_printf(dev, "Overriding MAC from EEPROM\n");
395 for (i = 0; i < 6; i++) {
396 ar711_base_mac[i] = mac[i];
400 KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
401 ("if_arge: Only MAC0 and MAC1 supported"));
404 * Fetch the PLL configuration.
406 arge_fetch_pll_config(sc);
409 * Get the MII configuration, if applicable.
411 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
412 "miimode", &miicfg) == 0) {
413 /* XXX bounds check? */
414 device_printf(dev, "%s: overriding MII mode to '%s'\n",
415 __func__, arge_miicfg_str[miicfg]);
416 sc->arge_miicfg = miicfg;
420 * Get which PHY of 5 available we should use for this unit
422 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
423 "phymask", &sc->arge_phymask) != 0) {
425 * Use port 4 (WAN) for GE0. For any other port use
426 * its PHY the same as its unit number
428 if (sc->arge_mac_unit == 0)
429 sc->arge_phymask = (1 << 4);
431 /* Use all phys up to 4 */
432 sc->arge_phymask = (1 << 4) - 1;
434 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
438 * Get default media & duplex mode, by default its Base100T
441 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
442 "media", &hint) != 0)
446 sc->arge_media_type = IFM_1000_T;
448 sc->arge_media_type = IFM_100_TX;
450 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
451 "fduplex", &hint) != 0)
455 sc->arge_duplex_mode = IFM_FDX;
457 sc->arge_duplex_mode = 0;
459 mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
461 callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
462 TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
464 /* Map control/status registers. */
466 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
467 &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
469 if (sc->arge_res == NULL) {
470 device_printf(dev, "couldn't map memory\n");
475 /* Allocate interrupts */
477 sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
478 RF_SHAREABLE | RF_ACTIVE);
480 if (sc->arge_irq == NULL) {
481 device_printf(dev, "couldn't map interrupt\n");
486 /* Allocate ifnet structure. */
487 ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
490 device_printf(dev, "couldn't allocate ifnet structure\n");
496 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
497 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
498 ifp->if_ioctl = arge_ioctl;
499 ifp->if_start = arge_start;
500 ifp->if_init = arge_init;
501 sc->arge_if_flags = ifp->if_flags;
503 /* XXX: add real size */
504 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
505 ifp->if_snd.ifq_maxlen = ifqmaxlen;
506 IFQ_SET_READY(&ifp->if_snd);
508 ifp->if_capenable = ifp->if_capabilities;
509 #ifdef DEVICE_POLLING
510 ifp->if_capabilities |= IFCAP_POLLING;
513 is_base_mac_empty = 1;
514 for (i = 0; i < ETHER_ADDR_LEN; i++) {
515 sc->arge_eaddr[i] = ar711_base_mac[i] & 0xff;
516 if (sc->arge_eaddr[i] != 0)
517 is_base_mac_empty = 0;
520 if (is_base_mac_empty) {
522 * No MAC address configured. Generate the random one.
526 "Generating random ethernet address.\n");
529 sc->arge_eaddr[0] = 'b';
530 sc->arge_eaddr[1] = 's';
531 sc->arge_eaddr[2] = 'd';
532 sc->arge_eaddr[3] = (rnd >> 24) & 0xff;
533 sc->arge_eaddr[4] = (rnd >> 16) & 0xff;
534 sc->arge_eaddr[5] = (rnd >> 8) & 0xff;
536 if (sc->arge_mac_unit != 0)
537 sc->arge_eaddr[5] += sc->arge_mac_unit;
539 if (arge_dma_alloc(sc) != 0) {
545 * Don't do this for the MDIO bus case - it's already done
546 * as part of the MDIO bus attachment.
548 #if !defined(ARGE_MDIO)
549 /* Initialize the MAC block */
551 arge_reset_miibus(sc);
554 /* Configure MII mode, just for convienence */
555 if (sc->arge_miicfg != 0)
556 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
559 * Set all Ethernet address registers to the same initial values
560 * set all four addresses to 66-88-aa-cc-dd-ee
562 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
563 | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
564 | sc->arge_eaddr[5]);
565 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
566 | sc->arge_eaddr[1]);
568 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
569 FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
571 switch (ar71xx_soc) {
572 case AR71XX_SOC_AR7240:
573 case AR71XX_SOC_AR7241:
574 case AR71XX_SOC_AR7242:
575 case AR71XX_SOC_AR9330:
576 case AR71XX_SOC_AR9331:
577 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
578 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
581 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
582 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
585 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
586 FIFO_RX_FILTMATCH_DEFAULT);
588 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
589 FIFO_RX_FILTMASK_DEFAULT);
591 #if defined(ARGE_MDIO)
592 sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
595 device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
596 ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
598 for (i = 0; i < ARGE_NPHY; i++) {
599 if (((1 << i) & sc->arge_phymask) != 0) {
600 error = mii_attach(sc->arge_miiproxy != NULL ?
601 sc->arge_miiproxy : sc->arge_dev,
602 &sc->arge_miibus, sc->arge_ifp,
603 arge_ifmedia_upd, arge_ifmedia_sts,
604 BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
606 device_printf(sc->arge_dev, "unable to attach"
607 " PHY %d: %d\n", i, error);
612 if (sc->arge_miibus == NULL) {
613 /* no PHY, so use hard-coded values */
614 ifmedia_init(&sc->arge_ifmedia, 0,
615 arge_multiphy_mediachange,
616 arge_multiphy_mediastatus);
617 ifmedia_add(&sc->arge_ifmedia,
618 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode,
620 ifmedia_set(&sc->arge_ifmedia,
621 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode);
622 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
625 /* Call MI attach routine. */
626 ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
628 /* Hook interrupt last to avoid having to lock softc */
629 error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
630 arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
633 device_printf(sc->arge_dev, "couldn't set up irq\n");
634 ether_ifdetach(sc->arge_ifp);
638 /* setup sysctl variables */
639 arge_attach_sysctl(sc->arge_dev);
649 arge_detach(device_t dev)
651 struct arge_softc *sc = device_get_softc(dev);
652 struct ifnet *ifp = sc->arge_ifp;
654 KASSERT(mtx_initialized(&sc->arge_mtx),
655 ("arge mutex not initialized"));
657 /* These should only be active if attach succeeded */
658 if (device_is_attached(dev)) {
661 #ifdef DEVICE_POLLING
662 if (ifp->if_capenable & IFCAP_POLLING)
663 ether_poll_deregister(ifp);
668 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
673 device_delete_child(dev, sc->arge_miibus);
675 if (sc->arge_miiproxy)
676 device_delete_child(dev, sc->arge_miiproxy);
678 bus_generic_detach(dev);
680 if (sc->arge_intrhand)
681 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
684 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
692 mtx_destroy(&sc->arge_mtx);
699 arge_suspend(device_t dev)
702 panic("%s", __func__);
707 arge_resume(device_t dev)
710 panic("%s", __func__);
715 arge_shutdown(device_t dev)
717 struct arge_softc *sc;
719 sc = device_get_softc(dev);
729 arge_hinted_child(device_t bus, const char *dname, int dunit)
731 BUS_ADD_CHILD(bus, 0, dname, dunit);
732 device_printf(bus, "hinted child %s%d\n", dname, dunit);
736 arge_miibus_readreg(device_t dev, int phy, int reg)
738 struct arge_softc * sc = device_get_softc(dev);
740 uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
741 | (reg & MAC_MII_REG_MASK);
743 mtx_lock(&miibus_mtx);
744 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
745 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
746 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
748 i = ARGE_MII_TIMEOUT;
749 while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
750 MAC_MII_INDICATOR_BUSY) && (i--))
754 mtx_unlock(&miibus_mtx);
755 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
756 /* XXX: return ERRNO istead? */
760 result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
761 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
762 mtx_unlock(&miibus_mtx);
764 ARGEDEBUG(sc, ARGE_DBG_MII,
765 "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
766 __func__, phy, reg, addr, result);
772 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
774 struct arge_softc * sc = device_get_softc(dev);
777 (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
779 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
782 mtx_lock(&miibus_mtx);
783 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
784 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
786 i = ARGE_MII_TIMEOUT;
787 while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
788 MAC_MII_INDICATOR_BUSY) && (i--))
791 mtx_unlock(&miibus_mtx);
794 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
795 /* XXX: return ERRNO istead? */
803 arge_miibus_statchg(device_t dev)
805 struct arge_softc *sc;
807 sc = device_get_softc(dev);
808 taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
812 arge_link_task(void *arg, int pending)
814 struct arge_softc *sc;
815 sc = (struct arge_softc *)arg;
818 arge_update_link_locked(sc);
823 arge_update_link_locked(struct arge_softc *sc)
825 struct mii_data *mii;
827 uint32_t media, duplex;
829 mii = device_get_softc(sc->arge_miibus);
831 if (mii == NULL || ifp == NULL ||
832 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
836 if (mii->mii_media_status & IFM_ACTIVE) {
838 media = IFM_SUBTYPE(mii->mii_media_active);
839 if (media != IFM_NONE) {
840 sc->arge_link_status = 1;
841 duplex = mii->mii_media_active & IFM_GMASK;
842 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
846 arge_set_pll(sc, media, duplex);
849 sc->arge_link_status = 0;
854 arge_set_pll(struct arge_softc *sc, int media, int duplex)
856 uint32_t cfg, ifcontrol, rx_filtmask;
857 uint32_t fifo_tx, pll;
860 ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
861 duplex == IFM_FDX ? "full" : "half");
862 cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
863 cfg &= ~(MAC_CFG2_IFACE_MODE_1000
864 | MAC_CFG2_IFACE_MODE_10_100
865 | MAC_CFG2_FULL_DUPLEX);
867 if (duplex == IFM_FDX)
868 cfg |= MAC_CFG2_FULL_DUPLEX;
870 ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
871 ifcontrol &= ~MAC_IFCONTROL_SPEED;
873 ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
874 rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
878 cfg |= MAC_CFG2_IFACE_MODE_10_100;
882 cfg |= MAC_CFG2_IFACE_MODE_10_100;
883 ifcontrol |= MAC_IFCONTROL_SPEED;
888 cfg |= MAC_CFG2_IFACE_MODE_1000;
889 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
894 device_printf(sc->arge_dev,
895 "Unknown media %d\n", media);
898 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
900 switch (ar71xx_soc) {
901 case AR71XX_SOC_AR7240:
902 case AR71XX_SOC_AR7241:
903 case AR71XX_SOC_AR7242:
904 case AR71XX_SOC_AR9330:
905 case AR71XX_SOC_AR9331:
906 fifo_tx = 0x01f00140;
908 case AR71XX_SOC_AR9130:
909 case AR71XX_SOC_AR9132:
910 fifo_tx = 0x00780fff;
913 fifo_tx = 0x008001ff;
916 ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
917 ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
918 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
920 ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
922 /* fetch PLL registers */
923 pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
924 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
926 /* Override if required by platform data */
927 if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
928 pll = sc->arge_pllcfg.pll_10;
929 else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
930 pll = sc->arge_pllcfg.pll_100;
931 else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
932 pll = sc->arge_pllcfg.pll_1000;
933 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
935 /* XXX ensure pll != 0 */
936 ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
938 /* set MII registers */
940 * This was introduced to match what the Linux ag71xx ethernet
941 * driver does. For the AR71xx case, it does set the port
942 * MII speed. However, if this is done, non-gigabit speeds
943 * are not at all reliable when speaking via RGMII through
944 * 'bridge' PHY port that's pretending to be a local PHY.
946 * Until that gets root caused, and until an AR71xx + normal
947 * PHY board is tested, leave this disabled.
950 ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
956 arge_reset_dma(struct arge_softc *sc)
958 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
959 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
961 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
962 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
964 /* Clear all possible RX interrupts */
965 while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
966 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
969 * Clear all possible TX interrupts
971 while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
972 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
977 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
978 DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
979 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
980 DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
983 * Force a DDR flush so any pending data is properly
984 * flushed to RAM before underlying buffers are freed.
994 struct arge_softc *sc = xsc;
997 arge_init_locked(sc);
1002 arge_init_locked(struct arge_softc *sc)
1004 struct ifnet *ifp = sc->arge_ifp;
1005 struct mii_data *mii;
1007 ARGE_LOCK_ASSERT(sc);
1011 /* Init circular RX list. */
1012 if (arge_rx_ring_init(sc) != 0) {
1013 device_printf(sc->arge_dev,
1014 "initialization failed: no memory for rx buffers\n");
1019 /* Init tx descriptors. */
1020 arge_tx_ring_init(sc);
1024 if (sc->arge_miibus) {
1025 mii = device_get_softc(sc->arge_miibus);
1030 * Sun always shines over multiPHY interface
1032 sc->arge_link_status = 1;
1035 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1036 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1038 if (sc->arge_miibus) {
1039 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1040 arge_update_link_locked(sc);
1043 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1044 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1046 /* Start listening */
1047 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1049 /* Enable interrupts */
1050 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1054 * Return whether the mbuf chain is correctly aligned
1055 * for the arge TX engine.
1057 * The TX engine requires each fragment to be aligned to a
1058 * 4 byte boundary and the size of each fragment except
1059 * the last to be a multiple of 4 bytes.
1062 arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
1066 for (m = m0; m != NULL; m = m->m_next) {
1067 if((mtod(m, intptr_t) & 3) != 0)
1069 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
1076 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1077 * pointers to the fragment pointers.
1080 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
1082 struct arge_txdesc *txd;
1083 struct arge_desc *desc, *prev_desc;
1084 bus_dma_segment_t txsegs[ARGE_MAXFRAGS];
1085 int error, i, nsegs, prod, prev_prod;
1088 ARGE_LOCK_ASSERT(sc);
1091 * Fix mbuf chain, all fragments should be 4 bytes aligned and
1095 if (! arge_mbuf_chain_is_tx_aligned(m)) {
1096 sc->stats.tx_pkts_unaligned++;
1097 m = m_defrag(*m_head, M_NOWAIT);
1104 sc->stats.tx_pkts_aligned++;
1106 prod = sc->arge_cdata.arge_tx_prod;
1107 txd = &sc->arge_cdata.arge_txdesc[prod];
1108 error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
1109 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1111 if (error == EFBIG) {
1113 } else if (error != 0)
1122 /* Check number of available descriptors. */
1123 if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
1124 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1128 txd->tx_m = *m_head;
1129 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1130 BUS_DMASYNC_PREWRITE);
1133 * Make a list of descriptors for this packet. DMA controller will
1134 * walk through it while arge_link is not zero.
1137 desc = prev_desc = NULL;
1138 for (i = 0; i < nsegs; i++) {
1139 desc = &sc->arge_rdata.arge_tx_ring[prod];
1140 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
1142 if (txsegs[i].ds_addr & 3)
1143 panic("TX packet address unaligned\n");
1145 desc->packet_addr = txsegs[i].ds_addr;
1147 /* link with previous descriptor */
1149 prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1151 sc->arge_cdata.arge_tx_cnt++;
1153 ARGE_INC(prod, ARGE_TX_RING_COUNT);
1156 /* Update producer index. */
1157 sc->arge_cdata.arge_tx_prod = prod;
1159 /* Sync descriptors. */
1160 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1161 sc->arge_cdata.arge_tx_ring_map,
1162 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1164 /* Start transmitting */
1165 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
1167 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1172 arge_start(struct ifnet *ifp)
1174 struct arge_softc *sc;
1179 arge_start_locked(ifp);
1184 arge_start_locked(struct ifnet *ifp)
1186 struct arge_softc *sc;
1187 struct mbuf *m_head;
1192 ARGE_LOCK_ASSERT(sc);
1194 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1196 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1197 IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1201 * Before we go any further, check whether we're already full.
1202 * The below check errors out immediately if the ring is full
1203 * and never gets a chance to set this flag. Although it's
1204 * likely never needed, this at least avoids an unexpected
1207 if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1208 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1209 ARGEDEBUG(sc, ARGE_DBG_ERR,
1210 "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1211 __func__, sc->arge_cdata.arge_tx_cnt,
1212 ARGE_TX_RING_COUNT - 2);
1218 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1219 sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1220 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1226 * Pack the data into the transmit ring.
1228 if (arge_encap(sc, &m_head)) {
1231 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1232 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1238 * If there's a BPF listener, bounce a copy of this frame
1241 ETHER_BPF_MTAP(ifp, m_head);
1243 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
1248 arge_stop(struct arge_softc *sc)
1252 ARGE_LOCK_ASSERT(sc);
1255 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1256 if (sc->arge_miibus)
1257 callout_stop(&sc->arge_stat_callout);
1259 /* mask out interrupts */
1260 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1264 /* Flush FIFO and free any existing mbufs */
1266 arge_rx_ring_free(sc);
1271 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1273 struct arge_softc *sc = ifp->if_softc;
1274 struct ifreq *ifr = (struct ifreq *) data;
1275 struct mii_data *mii;
1277 #ifdef DEVICE_POLLING
1284 if ((ifp->if_flags & IFF_UP) != 0) {
1285 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1286 if (((ifp->if_flags ^ sc->arge_if_flags)
1287 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1288 /* XXX: handle promisc & multi flags */
1292 if (!sc->arge_detach)
1293 arge_init_locked(sc);
1295 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1296 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1299 sc->arge_if_flags = ifp->if_flags;
1305 /* XXX: implement SIOCDELMULTI */
1310 if (sc->arge_miibus) {
1311 mii = device_get_softc(sc->arge_miibus);
1312 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1316 error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
1320 /* XXX: Check other capabilities */
1321 #ifdef DEVICE_POLLING
1322 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1323 if (mask & IFCAP_POLLING) {
1324 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1325 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1326 error = ether_poll_register(arge_poll, ifp);
1330 ifp->if_capenable |= IFCAP_POLLING;
1333 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1334 error = ether_poll_deregister(ifp);
1336 ifp->if_capenable &= ~IFCAP_POLLING;
1344 error = ether_ioctl(ifp, command, data);
1352 * Set media options.
1355 arge_ifmedia_upd(struct ifnet *ifp)
1357 struct arge_softc *sc;
1358 struct mii_data *mii;
1359 struct mii_softc *miisc;
1364 mii = device_get_softc(sc->arge_miibus);
1365 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1367 error = mii_mediachg(mii);
1374 * Report current media status.
1377 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1379 struct arge_softc *sc = ifp->if_softc;
1380 struct mii_data *mii;
1382 mii = device_get_softc(sc->arge_miibus);
1385 ifmr->ifm_active = mii->mii_media_active;
1386 ifmr->ifm_status = mii->mii_media_status;
1390 struct arge_dmamap_arg {
1391 bus_addr_t arge_busaddr;
1395 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1397 struct arge_dmamap_arg *ctx;
1402 ctx->arge_busaddr = segs[0].ds_addr;
1406 arge_dma_alloc(struct arge_softc *sc)
1408 struct arge_dmamap_arg ctx;
1409 struct arge_txdesc *txd;
1410 struct arge_rxdesc *rxd;
1413 /* Create parent DMA tag. */
1414 error = bus_dma_tag_create(
1415 bus_get_dma_tag(sc->arge_dev), /* parent */
1416 1, 0, /* alignment, boundary */
1417 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1418 BUS_SPACE_MAXADDR, /* highaddr */
1419 NULL, NULL, /* filter, filterarg */
1420 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1422 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1424 NULL, NULL, /* lockfunc, lockarg */
1425 &sc->arge_cdata.arge_parent_tag);
1427 device_printf(sc->arge_dev,
1428 "failed to create parent DMA tag\n");
1431 /* Create tag for Tx ring. */
1432 error = bus_dma_tag_create(
1433 sc->arge_cdata.arge_parent_tag, /* parent */
1434 ARGE_RING_ALIGN, 0, /* alignment, boundary */
1435 BUS_SPACE_MAXADDR, /* lowaddr */
1436 BUS_SPACE_MAXADDR, /* highaddr */
1437 NULL, NULL, /* filter, filterarg */
1438 ARGE_TX_DMA_SIZE, /* maxsize */
1440 ARGE_TX_DMA_SIZE, /* maxsegsize */
1442 NULL, NULL, /* lockfunc, lockarg */
1443 &sc->arge_cdata.arge_tx_ring_tag);
1445 device_printf(sc->arge_dev,
1446 "failed to create Tx ring DMA tag\n");
1450 /* Create tag for Rx ring. */
1451 error = bus_dma_tag_create(
1452 sc->arge_cdata.arge_parent_tag, /* parent */
1453 ARGE_RING_ALIGN, 0, /* alignment, boundary */
1454 BUS_SPACE_MAXADDR, /* lowaddr */
1455 BUS_SPACE_MAXADDR, /* highaddr */
1456 NULL, NULL, /* filter, filterarg */
1457 ARGE_RX_DMA_SIZE, /* maxsize */
1459 ARGE_RX_DMA_SIZE, /* maxsegsize */
1461 NULL, NULL, /* lockfunc, lockarg */
1462 &sc->arge_cdata.arge_rx_ring_tag);
1464 device_printf(sc->arge_dev,
1465 "failed to create Rx ring DMA tag\n");
1469 /* Create tag for Tx buffers. */
1470 error = bus_dma_tag_create(
1471 sc->arge_cdata.arge_parent_tag, /* parent */
1472 sizeof(uint32_t), 0, /* alignment, boundary */
1473 BUS_SPACE_MAXADDR, /* lowaddr */
1474 BUS_SPACE_MAXADDR, /* highaddr */
1475 NULL, NULL, /* filter, filterarg */
1476 MCLBYTES * ARGE_MAXFRAGS, /* maxsize */
1477 ARGE_MAXFRAGS, /* nsegments */
1478 MCLBYTES, /* maxsegsize */
1480 NULL, NULL, /* lockfunc, lockarg */
1481 &sc->arge_cdata.arge_tx_tag);
1483 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1487 /* Create tag for Rx buffers. */
1488 error = bus_dma_tag_create(
1489 sc->arge_cdata.arge_parent_tag, /* parent */
1490 ARGE_RX_ALIGN, 0, /* alignment, boundary */
1491 BUS_SPACE_MAXADDR, /* lowaddr */
1492 BUS_SPACE_MAXADDR, /* highaddr */
1493 NULL, NULL, /* filter, filterarg */
1494 MCLBYTES, /* maxsize */
1495 ARGE_MAXFRAGS, /* nsegments */
1496 MCLBYTES, /* maxsegsize */
1498 NULL, NULL, /* lockfunc, lockarg */
1499 &sc->arge_cdata.arge_rx_tag);
1501 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
1505 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1506 error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
1507 (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
1508 BUS_DMA_COHERENT | BUS_DMA_ZERO,
1509 &sc->arge_cdata.arge_tx_ring_map);
1511 device_printf(sc->arge_dev,
1512 "failed to allocate DMA'able memory for Tx ring\n");
1516 ctx.arge_busaddr = 0;
1517 error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
1518 sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
1519 ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1520 if (error != 0 || ctx.arge_busaddr == 0) {
1521 device_printf(sc->arge_dev,
1522 "failed to load DMA'able memory for Tx ring\n");
1525 sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
1527 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1528 error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
1529 (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
1530 BUS_DMA_COHERENT | BUS_DMA_ZERO,
1531 &sc->arge_cdata.arge_rx_ring_map);
1533 device_printf(sc->arge_dev,
1534 "failed to allocate DMA'able memory for Rx ring\n");
1538 ctx.arge_busaddr = 0;
1539 error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
1540 sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
1541 ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1542 if (error != 0 || ctx.arge_busaddr == 0) {
1543 device_printf(sc->arge_dev,
1544 "failed to load DMA'able memory for Rx ring\n");
1547 sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
1549 /* Create DMA maps for Tx buffers. */
1550 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1551 txd = &sc->arge_cdata.arge_txdesc[i];
1553 txd->tx_dmamap = NULL;
1554 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
1557 device_printf(sc->arge_dev,
1558 "failed to create Tx dmamap\n");
1562 /* Create DMA maps for Rx buffers. */
1563 if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1564 &sc->arge_cdata.arge_rx_sparemap)) != 0) {
1565 device_printf(sc->arge_dev,
1566 "failed to create spare Rx dmamap\n");
1569 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1570 rxd = &sc->arge_cdata.arge_rxdesc[i];
1572 rxd->rx_dmamap = NULL;
1573 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1576 device_printf(sc->arge_dev,
1577 "failed to create Rx dmamap\n");
1587 arge_dma_free(struct arge_softc *sc)
1589 struct arge_txdesc *txd;
1590 struct arge_rxdesc *rxd;
1594 if (sc->arge_cdata.arge_tx_ring_tag) {
1595 if (sc->arge_cdata.arge_tx_ring_map)
1596 bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
1597 sc->arge_cdata.arge_tx_ring_map);
1598 if (sc->arge_cdata.arge_tx_ring_map &&
1599 sc->arge_rdata.arge_tx_ring)
1600 bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
1601 sc->arge_rdata.arge_tx_ring,
1602 sc->arge_cdata.arge_tx_ring_map);
1603 sc->arge_rdata.arge_tx_ring = NULL;
1604 sc->arge_cdata.arge_tx_ring_map = NULL;
1605 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
1606 sc->arge_cdata.arge_tx_ring_tag = NULL;
1609 if (sc->arge_cdata.arge_rx_ring_tag) {
1610 if (sc->arge_cdata.arge_rx_ring_map)
1611 bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
1612 sc->arge_cdata.arge_rx_ring_map);
1613 if (sc->arge_cdata.arge_rx_ring_map &&
1614 sc->arge_rdata.arge_rx_ring)
1615 bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
1616 sc->arge_rdata.arge_rx_ring,
1617 sc->arge_cdata.arge_rx_ring_map);
1618 sc->arge_rdata.arge_rx_ring = NULL;
1619 sc->arge_cdata.arge_rx_ring_map = NULL;
1620 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
1621 sc->arge_cdata.arge_rx_ring_tag = NULL;
1624 if (sc->arge_cdata.arge_tx_tag) {
1625 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1626 txd = &sc->arge_cdata.arge_txdesc[i];
1627 if (txd->tx_dmamap) {
1628 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
1630 txd->tx_dmamap = NULL;
1633 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
1634 sc->arge_cdata.arge_tx_tag = NULL;
1637 if (sc->arge_cdata.arge_rx_tag) {
1638 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1639 rxd = &sc->arge_cdata.arge_rxdesc[i];
1640 if (rxd->rx_dmamap) {
1641 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1643 rxd->rx_dmamap = NULL;
1646 if (sc->arge_cdata.arge_rx_sparemap) {
1647 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1648 sc->arge_cdata.arge_rx_sparemap);
1649 sc->arge_cdata.arge_rx_sparemap = 0;
1651 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
1652 sc->arge_cdata.arge_rx_tag = NULL;
1655 if (sc->arge_cdata.arge_parent_tag) {
1656 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
1657 sc->arge_cdata.arge_parent_tag = NULL;
1662 * Initialize the transmit descriptors.
1665 arge_tx_ring_init(struct arge_softc *sc)
1667 struct arge_ring_data *rd;
1668 struct arge_txdesc *txd;
1672 sc->arge_cdata.arge_tx_prod = 0;
1673 sc->arge_cdata.arge_tx_cons = 0;
1674 sc->arge_cdata.arge_tx_cnt = 0;
1676 rd = &sc->arge_rdata;
1677 bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
1678 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1679 if (i == ARGE_TX_RING_COUNT - 1)
1680 addr = ARGE_TX_RING_ADDR(sc, 0);
1682 addr = ARGE_TX_RING_ADDR(sc, i + 1);
1683 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
1684 rd->arge_tx_ring[i].next_desc = addr;
1685 txd = &sc->arge_cdata.arge_txdesc[i];
1689 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1690 sc->arge_cdata.arge_tx_ring_map,
1691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1697 * Initialize the RX descriptors and allocate mbufs for them. Note that
1698 * we arrange the descriptors in a closed ring, so that the last descriptor
1699 * points back to the first.
1702 arge_rx_ring_init(struct arge_softc *sc)
1704 struct arge_ring_data *rd;
1705 struct arge_rxdesc *rxd;
1709 sc->arge_cdata.arge_rx_cons = 0;
1711 rd = &sc->arge_rdata;
1712 bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
1713 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1714 rxd = &sc->arge_cdata.arge_rxdesc[i];
1715 if (rxd->rx_m != NULL) {
1716 device_printf(sc->arge_dev,
1717 "%s: ring[%d] rx_m wasn't free?\n",
1722 rxd->desc = &rd->arge_rx_ring[i];
1723 if (i == ARGE_RX_RING_COUNT - 1)
1724 addr = ARGE_RX_RING_ADDR(sc, 0);
1726 addr = ARGE_RX_RING_ADDR(sc, i + 1);
1727 rd->arge_rx_ring[i].next_desc = addr;
1728 if (arge_newbuf(sc, i) != 0) {
1733 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1734 sc->arge_cdata.arge_rx_ring_map,
1735 BUS_DMASYNC_PREWRITE);
1741 * Free all the buffers in the RX ring.
1743 * TODO: ensure that DMA is disabled and no pending DMA
1744 * is lurking in the FIFO.
1747 arge_rx_ring_free(struct arge_softc *sc)
1750 struct arge_rxdesc *rxd;
1752 ARGE_LOCK_ASSERT(sc);
1754 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1755 rxd = &sc->arge_cdata.arge_rxdesc[i];
1756 /* Unmap the mbuf */
1757 if (rxd->rx_m != NULL) {
1758 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
1767 * Initialize an RX descriptor and attach an MBUF cluster.
1770 arge_newbuf(struct arge_softc *sc, int idx)
1772 struct arge_desc *desc;
1773 struct arge_rxdesc *rxd;
1775 bus_dma_segment_t segs[1];
1779 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1782 m->m_len = m->m_pkthdr.len = MCLBYTES;
1783 m_adj(m, sizeof(uint64_t));
1785 if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
1786 sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1790 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1792 rxd = &sc->arge_cdata.arge_rxdesc[idx];
1793 if (rxd->rx_m != NULL) {
1794 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
1796 map = rxd->rx_dmamap;
1797 rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
1798 sc->arge_cdata.arge_rx_sparemap = map;
1801 if (segs[0].ds_addr & 3)
1802 panic("RX packet address unaligned");
1803 desc->packet_addr = segs[0].ds_addr;
1804 desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
1806 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1807 sc->arge_cdata.arge_rx_ring_map,
1808 BUS_DMASYNC_PREWRITE);
1813 static __inline void
1814 arge_fixup_rx(struct mbuf *m)
1817 uint16_t *src, *dst;
1819 src = mtod(m, uint16_t *);
1822 for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
1826 if (m->m_len % sizeof(uint16_t))
1827 *(uint8_t *)dst = *(uint8_t *)src;
1829 m->m_data -= ETHER_ALIGN;
1832 #ifdef DEVICE_POLLING
1834 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1836 struct arge_softc *sc = ifp->if_softc;
1839 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1842 rx_npkts = arge_rx_locked(sc);
1848 #endif /* DEVICE_POLLING */
1852 arge_tx_locked(struct arge_softc *sc)
1854 struct arge_txdesc *txd;
1855 struct arge_desc *cur_tx;
1860 ARGE_LOCK_ASSERT(sc);
1862 cons = sc->arge_cdata.arge_tx_cons;
1863 prod = sc->arge_cdata.arge_tx_prod;
1865 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
1871 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1872 sc->arge_cdata.arge_tx_ring_map,
1873 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1877 * Go through our tx list and free mbufs for those
1878 * frames that have been transmitted.
1880 for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
1881 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
1882 ctrl = cur_tx->packet_ctrl;
1883 /* Check if descriptor has "finished" flag */
1884 if ((ctrl & ARGE_DESC_EMPTY) == 0)
1887 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1889 sc->arge_cdata.arge_tx_cnt--;
1890 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1892 txd = &sc->arge_cdata.arge_txdesc[cons];
1896 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1897 BUS_DMASYNC_POSTWRITE);
1898 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1900 /* Free only if it's first descriptor in list */
1905 /* reset descriptor */
1906 cur_tx->packet_addr = 0;
1909 sc->arge_cdata.arge_tx_cons = cons;
1911 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1912 sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1917 arge_rx_locked(struct arge_softc *sc)
1919 struct arge_rxdesc *rxd;
1920 struct ifnet *ifp = sc->arge_ifp;
1921 int cons, prog, packet_len, i;
1922 struct arge_desc *cur_rx;
1926 ARGE_LOCK_ASSERT(sc);
1928 cons = sc->arge_cdata.arge_rx_cons;
1930 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1931 sc->arge_cdata.arge_rx_ring_map,
1932 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1934 for (prog = 0; prog < ARGE_RX_RING_COUNT;
1935 ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
1936 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
1937 rxd = &sc->arge_cdata.arge_rxdesc[cons];
1940 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
1943 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1947 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
1948 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
1949 BUS_DMASYNC_POSTREAD);
1953 m->m_pkthdr.rcvif = ifp;
1954 /* Skip 4 bytes of CRC */
1955 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
1960 (*ifp->if_input)(ifp, m);
1962 cur_rx->packet_addr = 0;
1967 i = sc->arge_cdata.arge_rx_cons;
1968 for (; prog > 0 ; prog--) {
1969 if (arge_newbuf(sc, i) != 0) {
1970 device_printf(sc->arge_dev,
1971 "Failed to allocate buffer\n");
1974 ARGE_INC(i, ARGE_RX_RING_COUNT);
1977 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1978 sc->arge_cdata.arge_rx_ring_map,
1979 BUS_DMASYNC_PREWRITE);
1981 sc->arge_cdata.arge_rx_cons = cons;
1988 arge_intr_filter(void *arg)
1990 struct arge_softc *sc = arg;
1991 uint32_t status, ints;
1993 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
1994 ints = ARGE_READ(sc, AR71XX_DMA_INTR);
1996 ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
1997 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
1998 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
1999 ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2000 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2001 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2003 if (status & DMA_INTR_ALL) {
2004 sc->arge_intr_status |= status;
2005 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2006 return (FILTER_SCHEDULE_THREAD);
2009 sc->arge_intr_status = 0;
2010 return (FILTER_STRAY);
2014 arge_intr(void *arg)
2016 struct arge_softc *sc = arg;
2018 struct ifnet *ifp = sc->arge_ifp;
2020 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2021 status |= sc->arge_intr_status;
2023 ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2024 "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2025 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2028 * Is it our interrupt at all?
2033 if (status & DMA_INTR_RX_BUS_ERROR) {
2034 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2035 device_printf(sc->arge_dev, "RX bus error");
2039 if (status & DMA_INTR_TX_BUS_ERROR) {
2040 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2041 device_printf(sc->arge_dev, "TX bus error");
2047 if (status & DMA_INTR_RX_PKT_RCVD)
2051 * RX overrun disables the receiver.
2052 * Clear indication and re-enable rx.
2054 if ( status & DMA_INTR_RX_OVERFLOW) {
2055 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2056 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2057 sc->stats.rx_overflow++;
2060 if (status & DMA_INTR_TX_PKT_SENT)
2063 * Underrun turns off TX. Clear underrun indication.
2064 * If there's anything left in the ring, reactivate the tx.
2066 if (status & DMA_INTR_TX_UNDERRUN) {
2067 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2068 sc->stats.tx_underflow++;
2069 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
2070 __func__, sc->arge_cdata.arge_tx_cnt);
2071 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
2072 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2078 * If we've finished TXing and there's space for more packets
2079 * to be queued for TX, do so. Otherwise we may end up in a
2080 * situation where the interface send queue was filled
2081 * whilst the hardware queue was full, then the hardware
2082 * queue was drained by the interface send queue wasn't,
2083 * and thus if_start() is never called to kick-start
2084 * the send process (and all subsequent packets are simply
2087 * XXX TODO: make sure that the hardware deals nicely
2088 * with the possibility of the queue being enabled above
2089 * after a TX underrun, then having the hardware queue added
2092 if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
2093 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2094 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2095 arge_start_locked(ifp);
2099 * We handled all bits, clear status
2101 sc->arge_intr_status = 0;
2104 * re-enable all interrupts
2106 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2111 arge_tick(void *xsc)
2113 struct arge_softc *sc = xsc;
2114 struct mii_data *mii;
2116 ARGE_LOCK_ASSERT(sc);
2118 if (sc->arge_miibus) {
2119 mii = device_get_softc(sc->arge_miibus);
2121 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
2126 arge_multiphy_mediachange(struct ifnet *ifp)
2128 struct arge_softc *sc = ifp->if_softc;
2129 struct ifmedia *ifm = &sc->arge_ifmedia;
2130 struct ifmedia_entry *ife = ifm->ifm_cur;
2132 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2135 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
2136 device_printf(sc->arge_dev,
2137 "AUTO is not supported for multiphy MAC");
2148 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2150 struct arge_softc *sc = ifp->if_softc;
2152 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2153 ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
2154 sc->arge_duplex_mode;
2157 #if defined(ARGE_MDIO)
2159 argemdio_probe(device_t dev)
2161 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
2166 argemdio_attach(device_t dev)
2168 struct arge_softc *sc;
2171 sc = device_get_softc(dev);
2173 sc->arge_mac_unit = device_get_unit(dev);
2175 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2176 &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
2177 if (sc->arge_res == NULL) {
2178 device_printf(dev, "couldn't map memory\n");
2183 /* Reset MAC - required for AR71xx MDIO to successfully occur */
2186 arge_reset_miibus(sc);
2188 bus_generic_probe(dev);
2189 bus_enumerate_hinted_children(dev);
2190 error = bus_generic_attach(dev);
2196 argemdio_detach(device_t dev)