sys/mips/atheros/if_arge.c

   1 /*-
   2  * Copyright (c) 2009, Oleksandr Tymoshenko
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 /*
  32  * AR71XX gigabit ethernet driver
  33  */
  34 #ifdef HAVE_KERNEL_OPTION_HEADERS
  35 #include "opt_device_polling.h"
  36 #endif
  37
  38 #include "opt_arge.h"
  39
  40 #include <sys/param.h>
  41 #include <sys/endian.h>
  42 #include <sys/systm.h>
  43 #include <sys/sockio.h>
  44 #include <sys/lock.h>
  45 #include <sys/mbuf.h>
  46 #include <sys/malloc.h>
  47 #include <sys/mutex.h>
  48 #include <sys/kernel.h>
  49 #include <sys/module.h>
  50 #include <sys/socket.h>
  51 #include <sys/taskqueue.h>
  52 #include <sys/sysctl.h>
  53
  54 #include <net/if.h>
  55 #include <net/if_var.h>
  56 #include <net/if_media.h>
  57 #include <net/ethernet.h>
  58 #include <net/if_types.h>
  59
  60 #include <net/bpf.h>
  61
  62 #include <machine/bus.h>
  63 #include <machine/cache.h>
  64 #include <machine/resource.h>
  65 #include <vm/vm_param.h>
  66 #include <vm/vm.h>
  67 #include <vm/pmap.h>
  68 #include <machine/pmap.h>
  69 #include <sys/bus.h>
  70 #include <sys/rman.h>
  71
  72 #include <dev/mii/mii.h>
  73 #include <dev/mii/miivar.h>
  74
  75 #include <dev/pci/pcireg.h>
  76 #include <dev/pci/pcivar.h>
  77
  78 #include "opt_arge.h"
  79
  80 #if defined(ARGE_MDIO)
  81 #include <dev/etherswitch/mdio.h>
  82 #include <dev/etherswitch/miiproxy.h>
  83 #include "mdio_if.h"
  84 #endif
  85
  86
  87 MODULE_DEPEND(arge, ether, 1, 1, 1);
  88 MODULE_DEPEND(arge, miibus, 1, 1, 1);
  89 MODULE_VERSION(arge, 1);
  90
  91 #include "miibus_if.h"
  92
  93 #include <mips/atheros/ar71xxreg.h>
  94 #include <mips/atheros/ar934xreg.h>     /* XXX tsk! */
  95 #include <mips/atheros/if_argevar.h>
  96 #include <mips/atheros/ar71xx_setup.h>
  97 #include <mips/atheros/ar71xx_cpudef.h>
  98
  99 typedef enum {
 100         ARGE_DBG_MII    =       0x00000001,
 101         ARGE_DBG_INTR   =       0x00000002,
 102         ARGE_DBG_TX     =       0x00000004,
 103         ARGE_DBG_RX     =       0x00000008,
 104         ARGE_DBG_ERR    =       0x00000010,
 105         ARGE_DBG_RESET  =       0x00000020,
 106         ARGE_DBG_PLL    =       0x00000040,
 107 } arge_debug_flags;
 108
 109 static const char * arge_miicfg_str[] = {
 110         "NONE",
 111         "GMII",
 112         "MII",
 113         "RGMII",
 114         "RMII"
 115 };
 116
 117 #ifdef ARGE_DEBUG
 118 #define ARGEDEBUG(_sc, _m, ...)                                         \
 119         do {                                                            \
 120                 if ((_m) & (_sc)->arge_debug)                           \
 121                         device_printf((_sc)->arge_dev, __VA_ARGS__);    \
 122         } while (0)
 123 #else
 124 #define ARGEDEBUG(_sc, _m, ...)
 125 #endif
 126
 127 static int arge_attach(device_t);
 128 static int arge_detach(device_t);
 129 static void arge_flush_ddr(struct arge_softc *);
 130 static int arge_ifmedia_upd(struct ifnet *);
 131 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 132 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
 133 static void arge_init(void *);
 134 static void arge_init_locked(struct arge_softc *);
 135 static void arge_link_task(void *, int);
 136 static void arge_update_link_locked(struct arge_softc *sc);
 137 static void arge_set_pll(struct arge_softc *, int, int);
 138 static int arge_miibus_readreg(device_t, int, int);
 139 static void arge_miibus_statchg(device_t);
 140 static int arge_miibus_writereg(device_t, int, int, int);
 141 static int arge_probe(device_t);
 142 static void arge_reset_dma(struct arge_softc *);
 143 static int arge_resume(device_t);
 144 static int arge_rx_ring_init(struct arge_softc *);
 145 static void arge_rx_ring_free(struct arge_softc *sc);
 146 static int arge_tx_ring_init(struct arge_softc *);
 147 static void arge_tx_ring_free(struct arge_softc *);
 148 #ifdef DEVICE_POLLING
 149 static int arge_poll(struct ifnet *, enum poll_cmd, int);
 150 #endif
 151 static int arge_shutdown(device_t);
 152 static void arge_start(struct ifnet *);
 153 static void arge_start_locked(struct ifnet *);
 154 static void arge_stop(struct arge_softc *);
 155 static int arge_suspend(device_t);
 156
 157 static int arge_rx_locked(struct arge_softc *);
 158 static void arge_tx_locked(struct arge_softc *);
 159 static void arge_intr(void *);
 160 static int arge_intr_filter(void *);
 161 static void arge_tick(void *);
 162
 163 static void arge_hinted_child(device_t bus, const char *dname, int dunit);
 164
 165 /*
 166  * ifmedia callbacks for multiPHY MAC
 167  */
 168 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
 169 int arge_multiphy_mediachange(struct ifnet *);
 170
 171 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 172 static int arge_dma_alloc(struct arge_softc *);
 173 static void arge_dma_free(struct arge_softc *);
 174 static int arge_newbuf(struct arge_softc *, int);
 175 static __inline void arge_fixup_rx(struct mbuf *);
 176
 177 static device_method_t arge_methods[] = {
 178         /* Device interface */
 179         DEVMETHOD(device_probe,         arge_probe),
 180         DEVMETHOD(device_attach,        arge_attach),
 181         DEVMETHOD(device_detach,        arge_detach),
 182         DEVMETHOD(device_suspend,       arge_suspend),
 183         DEVMETHOD(device_resume,        arge_resume),
 184         DEVMETHOD(device_shutdown,      arge_shutdown),
 185
 186         /* MII interface */
 187         DEVMETHOD(miibus_readreg,       arge_miibus_readreg),
 188         DEVMETHOD(miibus_writereg,      arge_miibus_writereg),
 189         DEVMETHOD(miibus_statchg,       arge_miibus_statchg),
 190
 191         /* bus interface */
 192         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 193         DEVMETHOD(bus_hinted_child,     arge_hinted_child),
 194
 195         DEVMETHOD_END
 196 };
 197
 198 static driver_t arge_driver = {
 199         "arge",
 200         arge_methods,
 201         sizeof(struct arge_softc)
 202 };
 203
 204 static devclass_t arge_devclass;
 205
 206 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
 207 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
 208
 209 #if defined(ARGE_MDIO)
 210 static int argemdio_probe(device_t);
 211 static int argemdio_attach(device_t);
 212 static int argemdio_detach(device_t);
 213
 214 /*
 215  * Declare an additional, separate driver for accessing the MDIO bus.
 216  */
 217 static device_method_t argemdio_methods[] = {
 218         /* Device interface */
 219         DEVMETHOD(device_probe,         argemdio_probe),
 220         DEVMETHOD(device_attach,        argemdio_attach),
 221         DEVMETHOD(device_detach,        argemdio_detach),
 222
 223         /* bus interface */
 224         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 225
 226         /* MDIO access */
 227         DEVMETHOD(mdio_readreg,         arge_miibus_readreg),
 228         DEVMETHOD(mdio_writereg,        arge_miibus_writereg),
 229 };
 230
 231 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
 232     sizeof(struct arge_softc));
 233 static devclass_t argemdio_devclass;
 234
 235 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
 236 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
 237 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
 238 #endif
 239
 240 /*
 241  * RedBoot passes MAC address to entry point as environment
 242  * variable. platfrom_start parses it and stores in this variable
 243  */
 244 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
 245
 246 static struct mtx miibus_mtx;
 247
 248 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
 249
 250 /*
 251  * Flushes all
 252  */
 253 static void
 254 arge_flush_ddr(struct arge_softc *sc)
 255 {
 256
 257         ar71xx_device_flush_ddr_ge(sc->arge_mac_unit);
 258 }
 259
 260 static int
 261 arge_probe(device_t dev)
 262 {
 263
 264         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
 265         return (BUS_PROBE_NOWILDCARD);
 266 }
 267
 268 static void
 269 arge_attach_sysctl(device_t dev)
 270 {
 271         struct arge_softc *sc = device_get_softc(dev);
 272         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 273         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 274
 275 #ifdef  ARGE_DEBUG
 276         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 277                 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
 278                 "arge interface debugging flags");
 279 #endif
 280
 281         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 282                 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
 283                 "number of TX aligned packets");
 284
 285         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 286                 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
 287                 0, "number of TX unaligned packets");
 288
 289 #ifdef  ARGE_DEBUG
 290         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
 291             CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
 292         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
 293             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
 294         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
 295             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
 296 #endif
 297 }
 298
 299 static void
 300 arge_reset_mac(struct arge_softc *sc)
 301 {
 302         uint32_t reg;
 303         uint32_t reset_reg;
 304
 305         /* Step 1. Soft-reset MAC */
 306         ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
 307         DELAY(20);
 308
 309         /* Step 2. Punt the MAC core from the central reset register */
 310         /*
 311          * XXX TODO: migrate this (and other) chip specific stuff into
 312          * a chipdef method.
 313          */
 314         if (sc->arge_mac_unit == 0) {
 315                 reset_reg = RST_RESET_GE0_MAC;
 316         } else {
 317                 reset_reg = RST_RESET_GE1_MAC;
 318         }
 319
 320         /*
 321          * AR934x (and later) also needs the MDIO block reset.
 322          */
 323         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
 324            ar71xx_soc == AR71XX_SOC_AR9342 ||
 325            ar71xx_soc == AR71XX_SOC_AR9344) {
 326                 if (sc->arge_mac_unit == 0) {
 327                         reset_reg |= AR934X_RESET_GE0_MDIO;
 328                 } else {
 329                         reset_reg |= AR934X_RESET_GE1_MDIO;
 330                 }
 331         }
 332         ar71xx_device_stop(reset_reg);
 333         DELAY(100);
 334         ar71xx_device_start(reset_reg);
 335
 336         /* Step 3. Reconfigure MAC block */
 337         ARGE_WRITE(sc, AR71XX_MAC_CFG1,
 338                 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
 339                 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
 340
 341         reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
 342         reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
 343         ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
 344
 345         ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
 346 }
 347
 348 /*
 349  * These values map to the divisor values programmed into
 350  * AR71XX_MAC_MII_CFG.
 351  *
 352  * The index of each value corresponds to the divisor section
 353  * value in AR71XX_MAC_MII_CFG (ie, table[0] means '0' in
 354  * AR71XX_MAC_MII_CFG, table[1] means '1', etc.)
 355  */
 356 static const uint32_t ar71xx_mdio_div_table[] = {
 357         4, 4, 6, 8, 10, 14, 20, 28,
 358 };
 359
 360 static const uint32_t ar7240_mdio_div_table[] = {
 361         2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
 362 };
 363
 364 static const uint32_t ar933x_mdio_div_table[] = {
 365         4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
 366 };
 367
 368 /*
 369  * Lookup the divisor to use based on the given frequency.
 370  *
 371  * Returns the divisor to use, or -ve on error.
 372  */
 373 static int
 374 arge_mdio_get_divider(struct arge_softc *sc, unsigned long mdio_clock)
 375 {
 376         unsigned long ref_clock, t;
 377         const uint32_t *table;
 378         int ndivs;
 379         int i;
 380
 381         /*
 382          * This is the base MDIO frequency on the SoC.
 383          * The dividers .. well, divide. Duh.
 384          */
 385         ref_clock = ar71xx_mdio_freq();
 386
 387         /*
 388          * If either clock is undefined, just tell the
 389          * caller to fall through to the defaults.
 390          */
 391         if (ref_clock == 0 || mdio_clock == 0)
 392                 return (-EINVAL);
 393
 394         /*
 395          * Pick the correct table!
 396          */
 397         switch (ar71xx_soc) {
 398         case AR71XX_SOC_AR9330:
 399         case AR71XX_SOC_AR9331:
 400         case AR71XX_SOC_AR9341:
 401         case AR71XX_SOC_AR9342:
 402         case AR71XX_SOC_AR9344:
 403                 table = ar933x_mdio_div_table;
 404                 ndivs = nitems(ar933x_mdio_div_table);
 405                 break;
 406
 407         case AR71XX_SOC_AR7240:
 408         case AR71XX_SOC_AR7241:
 409         case AR71XX_SOC_AR7242:
 410                 table = ar7240_mdio_div_table;
 411                 ndivs = nitems(ar7240_mdio_div_table);
 412                 break;
 413
 414         default:
 415                 table = ar71xx_mdio_div_table;
 416                 ndivs = nitems(ar71xx_mdio_div_table);
 417         }
 418
 419         /*
 420          * Now, walk through the list and find the first divisor
 421          * that falls under the target MDIO frequency.
 422          *
 423          * The divisors go up, but the corresponding frequencies
 424          * are actually decreasing.
 425          */
 426         for (i = 0; i < ndivs; i++) {
 427                 t = ref_clock / table[i];
 428                 if (t <= mdio_clock) {
 429                         return (i);
 430                 }
 431         }
 432
 433         ARGEDEBUG(sc, ARGE_DBG_RESET,
 434             "No divider found; MDIO=%lu Hz; target=%lu Hz\n",
 435                 ref_clock, mdio_clock);
 436         return (-ENOENT);
 437 }
 438
 439 /*
 440  * Fetch the MDIO bus clock rate.
 441  *
 442  * For now, the default is DIV_28 for everything
 443  * bar AR934x, which will be DIV_58.
 444  *
 445  * It will definitely need updating to take into account
 446  * the MDIO bus core clock rate and the target clock
 447  * rate for the chip.
 448  */
 449 static uint32_t
 450 arge_fetch_mdiobus_clock_rate(struct arge_softc *sc)
 451 {
 452         int mdio_freq, div;
 453
 454         /*
 455          * Is the MDIO frequency defined? If so, find a divisor that
 456          * makes reasonable sense.  Don't overshoot the frequency.
 457          */
 458         if (resource_int_value(device_get_name(sc->arge_dev),
 459             device_get_unit(sc->arge_dev),
 460             "mdio_freq",
 461             &mdio_freq) == 0) {
 462                 sc->arge_mdiofreq = mdio_freq;
 463                 div = arge_mdio_get_divider(sc, sc->arge_mdiofreq);
 464                 if (bootverbose)
 465                         device_printf(sc->arge_dev,
 466                             "%s: mdio ref freq=%llu Hz, target freq=%llu Hz,"
 467                             " divisor index=%d\n",
 468                             __func__,
 469                             (unsigned long long) ar71xx_mdio_freq(),
 470                             (unsigned long long) mdio_freq,
 471                             div);
 472                 if (div >= 0)
 473                         return (div);
 474         }
 475
 476         /*
 477          * Default value(s).
 478          *
 479          * XXX obviously these need .. fixing.
 480          *
 481          * From Linux/OpenWRT:
 482          *
 483          * + 7240? DIV_6
 484          * + Builtin-switch port and not 934x? DIV_10
 485          * + Not built-in switch port and 934x? DIV_58
 486          * + .. else DIV_28.
 487          */
 488         switch (ar71xx_soc) {
 489         case AR71XX_SOC_AR9341:
 490         case AR71XX_SOC_AR9342:
 491         case AR71XX_SOC_AR9344:
 492                 return (MAC_MII_CFG_CLOCK_DIV_58);
 493                 break;
 494         default:
 495                 return (MAC_MII_CFG_CLOCK_DIV_28);
 496         }
 497 }
 498
 499 static void
 500 arge_reset_miibus(struct arge_softc *sc)
 501 {
 502         uint32_t mdio_div;
 503
 504         mdio_div = arge_fetch_mdiobus_clock_rate(sc);
 505
 506         /*
 507          * XXX AR934x and later; should we be also resetting the
 508          * MDIO block(s) using the reset register block?
 509          */
 510
 511         /* Reset MII bus; program in the default divisor */
 512         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_div);
 513         DELAY(100);
 514         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_div);
 515         DELAY(100);
 516 }
 517
 518 static void
 519 arge_fetch_pll_config(struct arge_softc *sc)
 520 {
 521         long int val;
 522
 523         if (resource_long_value(device_get_name(sc->arge_dev),
 524             device_get_unit(sc->arge_dev),
 525             "pll_10", &val) == 0) {
 526                 sc->arge_pllcfg.pll_10 = val;
 527                 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
 528                     __func__, (int) val);
 529         }
 530         if (resource_long_value(device_get_name(sc->arge_dev),
 531             device_get_unit(sc->arge_dev),
 532             "pll_100", &val) == 0) {
 533                 sc->arge_pllcfg.pll_100 = val;
 534                 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
 535                     __func__, (int) val);
 536         }
 537         if (resource_long_value(device_get_name(sc->arge_dev),
 538             device_get_unit(sc->arge_dev),
 539             "pll_1000", &val) == 0) {
 540                 sc->arge_pllcfg.pll_1000 = val;
 541                 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
 542                     __func__, (int) val);
 543         }
 544 }
 545
 546 static int
 547 arge_attach(device_t dev)
 548 {
 549         struct ifnet            *ifp;
 550         struct arge_softc       *sc;
 551         int                     error = 0, rid;
 552         uint32_t                rnd;
 553         int                     is_base_mac_empty, i;
 554         uint32_t                hint;
 555         long                    eeprom_mac_addr = 0;
 556         int                     miicfg = 0;
 557         int                     readascii = 0;
 558         int                     local_mac = 0;
 559
 560         sc = device_get_softc(dev);
 561         sc->arge_dev = dev;
 562         sc->arge_mac_unit = device_get_unit(dev);
 563
 564         /*
 565          * Some units (eg the TP-Link WR-1043ND) do not have a convenient
 566          * EEPROM location to read the ethernet MAC address from.
 567          * OpenWRT simply snaffles it from a fixed location.
 568          *
 569          * Since multiple units seem to use this feature, include
 570          * a method of setting the MAC address based on an flash location
 571          * in CPU address space.
 572          *
 573          * Some vendors have decided to store the mac address as a literal
 574          * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of
 575          * an array of numbers.  Expose a hint to turn on this conversion
 576          * feature via strtol()
 577          */
 578          if (resource_long_value(device_get_name(dev), device_get_unit(dev),
 579             "eeprommac", &eeprom_mac_addr) == 0) {
 580                 local_mac = 1;
 581                 int i;
 582                 const char *mac =
 583                     (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
 584                 device_printf(dev, "Overriding MAC from EEPROM\n");
 585                 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 586                         "readascii", &readascii) == 0) {
 587                         device_printf(dev, "Vendor stores MAC in ASCII format\n");
 588                         for (i = 0; i < 6; i++) {
 589                                 ar711_base_mac[i] = strtol(&(mac[i*3]), NULL, 16);
 590                         }
 591                 } else {
 592                         for (i = 0; i < 6; i++) {
 593                                 ar711_base_mac[i] = mac[i];
 594                         }
 595                 }
 596         }
 597
 598         KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
 599             ("if_arge: Only MAC0 and MAC1 supported"));
 600
 601         /*
 602          * Fetch the PLL configuration.
 603          */
 604         arge_fetch_pll_config(sc);
 605
 606         /*
 607          * Get the MII configuration, if applicable.
 608          */
 609         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 610             "miimode", &miicfg) == 0) {
 611                 /* XXX bounds check? */
 612                 device_printf(dev, "%s: overriding MII mode to '%s'\n",
 613                     __func__, arge_miicfg_str[miicfg]);
 614                 sc->arge_miicfg = miicfg;
 615         }
 616
 617         /*
 618          *  Get which PHY of 5 available we should use for this unit
 619          */
 620         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 621             "phymask", &sc->arge_phymask) != 0) {
 622                 /*
 623                  * Use port 4 (WAN) for GE0. For any other port use
 624                  * its PHY the same as its unit number
 625                  */
 626                 if (sc->arge_mac_unit == 0)
 627                         sc->arge_phymask = (1 << 4);
 628                 else
 629                         /* Use all phys up to 4 */
 630                         sc->arge_phymask = (1 << 4) - 1;
 631
 632                 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
 633         }
 634
 635         /*
 636          *  Get default media & duplex mode, by default its Base100T
 637          *  and full duplex
 638          */
 639         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 640             "media", &hint) != 0)
 641                 hint = 0;
 642
 643         if (hint == 1000)
 644                 sc->arge_media_type = IFM_1000_T;
 645         else
 646                 sc->arge_media_type = IFM_100_TX;
 647
 648         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 649             "fduplex", &hint) != 0)
 650                 hint = 1;
 651
 652         if (hint)
 653                 sc->arge_duplex_mode = IFM_FDX;
 654         else
 655                 sc->arge_duplex_mode = 0;
 656
 657         mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 658             MTX_DEF);
 659         callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
 660         TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
 661
 662         /* Map control/status registers. */
 663         sc->arge_rid = 0;
 664         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 665             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
 666
 667         if (sc->arge_res == NULL) {
 668                 device_printf(dev, "couldn't map memory\n");
 669                 error = ENXIO;
 670                 goto fail;
 671         }
 672
 673         /* Allocate interrupts */
 674         rid = 0;
 675         sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 676             RF_SHAREABLE | RF_ACTIVE);
 677
 678         if (sc->arge_irq == NULL) {
 679                 device_printf(dev, "couldn't map interrupt\n");
 680                 error = ENXIO;
 681                 goto fail;
 682         }
 683
 684         /* Allocate ifnet structure. */
 685         ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
 686
 687         if (ifp == NULL) {
 688                 device_printf(dev, "couldn't allocate ifnet structure\n");
 689                 error = ENOSPC;
 690                 goto fail;
 691         }
 692
 693         ifp->if_softc = sc;
 694         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 695         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 696         ifp->if_ioctl = arge_ioctl;
 697         ifp->if_start = arge_start;
 698         ifp->if_init = arge_init;
 699         sc->arge_if_flags = ifp->if_flags;
 700
 701         /* XXX: add real size */
 702         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 703         ifp->if_snd.ifq_maxlen = ifqmaxlen;
 704         IFQ_SET_READY(&ifp->if_snd);
 705
 706         /* Tell the upper layer(s) we support long frames. */
 707         ifp->if_capabilities |= IFCAP_VLAN_MTU;
 708
 709         ifp->if_capenable = ifp->if_capabilities;
 710 #ifdef DEVICE_POLLING
 711         ifp->if_capabilities |= IFCAP_POLLING;
 712 #endif
 713
 714         is_base_mac_empty = 1;
 715         for (i = 0; i < ETHER_ADDR_LEN; i++) {
 716                 sc->arge_eaddr[i] = ar711_base_mac[i] & 0xff;
 717                 if (sc->arge_eaddr[i] != 0)
 718                         is_base_mac_empty = 0;
 719         }
 720
 721         if (is_base_mac_empty) {
 722                 /*
 723                  * No MAC address configured. Generate the random one.
 724                  */
 725                 if  (bootverbose)
 726                         device_printf(dev,
 727                             "Generating random ethernet address.\n");
 728
 729                 rnd = arc4random();
 730                 sc->arge_eaddr[0] = 'b';
 731                 sc->arge_eaddr[1] = 's';
 732                 sc->arge_eaddr[2] = 'd';
 733                 sc->arge_eaddr[3] = (rnd >> 24) & 0xff;
 734                 sc->arge_eaddr[4] = (rnd >> 16) & 0xff;
 735                 sc->arge_eaddr[5] = (rnd >> 8) & 0xff;
 736         }
 737
 738         /*
 739          * This is a little hairy and stupid.
 740          *
 741          * For some older boards, the arge1 mac isn't pulled from anywhere.
 742          * It's just assumed the MAC is the base MAC + 1.
 743          *
 744          * For other boards, there's multiple MAC addresses stored in EEPROM.
 745          *
 746          * So, if we did read the eeprommac for this particular interface,
 747          * let's use the address as given.  Otherwise, just add the MAC unit
 748          * counter to it.
 749          *
 750          * XXX TODO: we really should handle MAC byte wraparound!
 751          */
 752         if (local_mac == 0 && sc->arge_mac_unit != 0)
 753                 sc->arge_eaddr[5] +=  sc->arge_mac_unit;
 754
 755         if (arge_dma_alloc(sc) != 0) {
 756                 error = ENXIO;
 757                 goto fail;
 758         }
 759
 760         /*
 761          * Don't do this for the MDIO bus case - it's already done
 762          * as part of the MDIO bus attachment.
 763          */
 764 #if !defined(ARGE_MDIO)
 765         /* Initialize the MAC block */
 766         arge_reset_mac(sc);
 767         arge_reset_miibus(sc);
 768 #endif
 769
 770         /* Configure MII mode, just for convienence */
 771         if (sc->arge_miicfg != 0)
 772                 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
 773
 774         /*
 775          * Set all Ethernet address registers to the same initial values
 776          * set all four addresses to 66-88-aa-cc-dd-ee
 777          */
 778         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
 779             | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
 780             | sc->arge_eaddr[5]);
 781         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
 782             | sc->arge_eaddr[1]);
 783
 784         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
 785             FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
 786
 787         switch (ar71xx_soc) {
 788                 case AR71XX_SOC_AR7240:
 789                 case AR71XX_SOC_AR7241:
 790                 case AR71XX_SOC_AR7242:
 791                 case AR71XX_SOC_AR9330:
 792                 case AR71XX_SOC_AR9331:
 793                 case AR71XX_SOC_AR9341:
 794                 case AR71XX_SOC_AR9342:
 795                 case AR71XX_SOC_AR9344:
 796                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
 797                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
 798                         break;
 799                 /* AR71xx, AR913x */
 800                 default:
 801                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
 802                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
 803         }
 804
 805         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
 806             FIFO_RX_FILTMATCH_DEFAULT);
 807
 808         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
 809             FIFO_RX_FILTMASK_DEFAULT);
 810
 811 #if defined(ARGE_MDIO)
 812         sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
 813 #endif
 814
 815         device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
 816             ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
 817             "null" : "set");
 818         for (i = 0; i < ARGE_NPHY; i++) {
 819                 if (((1 << i) & sc->arge_phymask) != 0) {
 820                         error = mii_attach(sc->arge_miiproxy != NULL ?
 821                             sc->arge_miiproxy : sc->arge_dev,
 822                             &sc->arge_miibus, sc->arge_ifp,
 823                             arge_ifmedia_upd, arge_ifmedia_sts,
 824                             BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
 825                         if (error != 0) {
 826                                 device_printf(sc->arge_dev, "unable to attach"
 827                                     " PHY %d: %d\n", i, error);
 828                                 goto fail;
 829                         }
 830                 }
 831         }
 832         if (sc->arge_miibus == NULL) {
 833                 /* no PHY, so use hard-coded values */
 834                 ifmedia_init(&sc->arge_ifmedia, 0,
 835                     arge_multiphy_mediachange,
 836                     arge_multiphy_mediastatus);
 837                 ifmedia_add(&sc->arge_ifmedia,
 838                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode,
 839                     0, NULL);
 840                 ifmedia_set(&sc->arge_ifmedia,
 841                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode);
 842                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
 843         }
 844
 845         /* Call MI attach routine. */
 846         ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
 847
 848         /* Hook interrupt last to avoid having to lock softc */
 849         error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
 850             arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
 851
 852         if (error) {
 853                 device_printf(sc->arge_dev, "couldn't set up irq\n");
 854                 ether_ifdetach(sc->arge_ifp);
 855                 goto fail;
 856         }
 857
 858         /* setup sysctl variables */
 859         arge_attach_sysctl(sc->arge_dev);
 860
 861 fail:
 862         if (error)
 863                 arge_detach(dev);
 864
 865         return (error);
 866 }
 867
 868 static int
 869 arge_detach(device_t dev)
 870 {
 871         struct arge_softc       *sc = device_get_softc(dev);
 872         struct ifnet            *ifp = sc->arge_ifp;
 873
 874         KASSERT(mtx_initialized(&sc->arge_mtx),
 875             ("arge mutex not initialized"));
 876
 877         /* These should only be active if attach succeeded */
 878         if (device_is_attached(dev)) {
 879                 ARGE_LOCK(sc);
 880                 sc->arge_detach = 1;
 881 #ifdef DEVICE_POLLING
 882                 if (ifp->if_capenable & IFCAP_POLLING)
 883                         ether_poll_deregister(ifp);
 884 #endif
 885
 886                 arge_stop(sc);
 887                 ARGE_UNLOCK(sc);
 888                 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
 889                 ether_ifdetach(ifp);
 890         }
 891
 892         if (sc->arge_miibus)
 893                 device_delete_child(dev, sc->arge_miibus);
 894
 895         if (sc->arge_miiproxy)
 896                 device_delete_child(dev, sc->arge_miiproxy);
 897
 898         bus_generic_detach(dev);
 899
 900         if (sc->arge_intrhand)
 901                 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
 902
 903         if (sc->arge_res)
 904                 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
 905                     sc->arge_res);
 906
 907         if (ifp)
 908                 if_free(ifp);
 909
 910         arge_dma_free(sc);
 911
 912         mtx_destroy(&sc->arge_mtx);
 913
 914         return (0);
 915
 916 }
 917
 918 static int
 919 arge_suspend(device_t dev)
 920 {
 921
 922         panic("%s", __func__);
 923         return 0;
 924 }
 925
 926 static int
 927 arge_resume(device_t dev)
 928 {
 929
 930         panic("%s", __func__);
 931         return 0;
 932 }
 933
 934 static int
 935 arge_shutdown(device_t dev)
 936 {
 937         struct arge_softc       *sc;
 938
 939         sc = device_get_softc(dev);
 940
 941         ARGE_LOCK(sc);
 942         arge_stop(sc);
 943         ARGE_UNLOCK(sc);
 944
 945         return (0);
 946 }
 947
 948 static void
 949 arge_hinted_child(device_t bus, const char *dname, int dunit)
 950 {
 951         BUS_ADD_CHILD(bus, 0, dname, dunit);
 952         device_printf(bus, "hinted child %s%d\n", dname, dunit);
 953 }
 954
 955 static int
 956 arge_miibus_readreg(device_t dev, int phy, int reg)
 957 {
 958         struct arge_softc * sc = device_get_softc(dev);
 959         int i, result;
 960         uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
 961             | (reg & MAC_MII_REG_MASK);
 962
 963         mtx_lock(&miibus_mtx);
 964         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
 965         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
 966         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
 967
 968         i = ARGE_MII_TIMEOUT;
 969         while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
 970             MAC_MII_INDICATOR_BUSY) && (i--))
 971                 DELAY(5);
 972
 973         if (i < 0) {
 974                 mtx_unlock(&miibus_mtx);
 975                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
 976                 /* XXX: return ERRNO istead? */
 977                 return (-1);
 978         }
 979
 980         result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
 981         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
 982         mtx_unlock(&miibus_mtx);
 983
 984         ARGEDEBUG(sc, ARGE_DBG_MII,
 985             "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
 986             __func__, phy, reg, addr, result);
 987
 988         return (result);
 989 }
 990
 991 static int
 992 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
 993 {
 994         struct arge_softc * sc = device_get_softc(dev);
 995         int i;
 996         uint32_t addr =
 997             (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
 998
 999         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
1000             phy, reg, data);
1001
1002         mtx_lock(&miibus_mtx);
1003         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
1004         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
1005
1006         i = ARGE_MII_TIMEOUT;
1007         while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
1008             MAC_MII_INDICATOR_BUSY) && (i--))
1009                 DELAY(5);
1010
1011         mtx_unlock(&miibus_mtx);
1012
1013         if (i < 0) {
1014                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
1015                 /* XXX: return ERRNO istead? */
1016                 return (-1);
1017         }
1018
1019         return (0);
1020 }
1021
1022 static void
1023 arge_miibus_statchg(device_t dev)
1024 {
1025         struct arge_softc       *sc;
1026
1027         sc = device_get_softc(dev);
1028         taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
1029 }
1030
1031 static void
1032 arge_link_task(void *arg, int pending)
1033 {
1034         struct arge_softc       *sc;
1035         sc = (struct arge_softc *)arg;
1036
1037         ARGE_LOCK(sc);
1038         arge_update_link_locked(sc);
1039         ARGE_UNLOCK(sc);
1040 }
1041
1042 static void
1043 arge_update_link_locked(struct arge_softc *sc)
1044 {
1045         struct mii_data         *mii;
1046         struct ifnet            *ifp;
1047         uint32_t                media, duplex;
1048
1049         mii = device_get_softc(sc->arge_miibus);
1050         ifp = sc->arge_ifp;
1051         if (mii == NULL || ifp == NULL ||
1052             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1053                 return;
1054         }
1055
1056         if (mii->mii_media_status & IFM_ACTIVE) {
1057
1058                 media = IFM_SUBTYPE(mii->mii_media_active);
1059                 if (media != IFM_NONE) {
1060                         sc->arge_link_status = 1;
1061                         duplex = mii->mii_media_active & IFM_GMASK;
1062                         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
1063                             __func__,
1064                             media,
1065                             duplex);
1066                         arge_set_pll(sc, media, duplex);
1067                 }
1068         } else {
1069                 sc->arge_link_status = 0;
1070         }
1071 }
1072
1073 static void
1074 arge_set_pll(struct arge_softc *sc, int media, int duplex)
1075 {
1076         uint32_t                cfg, ifcontrol, rx_filtmask;
1077         uint32_t                fifo_tx, pll;
1078         int if_speed;
1079
1080         ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
1081             duplex == IFM_FDX ? "full" : "half");
1082         cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
1083         cfg &= ~(MAC_CFG2_IFACE_MODE_1000
1084             | MAC_CFG2_IFACE_MODE_10_100
1085             | MAC_CFG2_FULL_DUPLEX);
1086
1087         if (duplex == IFM_FDX)
1088                 cfg |= MAC_CFG2_FULL_DUPLEX;
1089
1090         ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
1091         ifcontrol &= ~MAC_IFCONTROL_SPEED;
1092         rx_filtmask =
1093             ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
1094         rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
1095
1096         switch(media) {
1097         case IFM_10_T:
1098                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1099                 if_speed = 10;
1100                 break;
1101         case IFM_100_TX:
1102                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1103                 ifcontrol |= MAC_IFCONTROL_SPEED;
1104                 if_speed = 100;
1105                 break;
1106         case IFM_1000_T:
1107         case IFM_1000_SX:
1108                 cfg |= MAC_CFG2_IFACE_MODE_1000;
1109                 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
1110                 if_speed = 1000;
1111                 break;
1112         default:
1113                 if_speed = 100;
1114                 device_printf(sc->arge_dev,
1115                     "Unknown media %d\n", media);
1116         }
1117
1118         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
1119
1120         switch (ar71xx_soc) {
1121                 case AR71XX_SOC_AR7240:
1122                 case AR71XX_SOC_AR7241:
1123                 case AR71XX_SOC_AR7242:
1124                 case AR71XX_SOC_AR9330:
1125                 case AR71XX_SOC_AR9331:
1126                 case AR71XX_SOC_AR9341:
1127                 case AR71XX_SOC_AR9342:
1128                 case AR71XX_SOC_AR9344:
1129                         fifo_tx = 0x01f00140;
1130                         break;
1131                 case AR71XX_SOC_AR9130:
1132                 case AR71XX_SOC_AR9132:
1133                         fifo_tx = 0x00780fff;
1134                         break;
1135                 /* AR71xx */
1136                 default:
1137                         fifo_tx = 0x008001ff;
1138         }
1139
1140         ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
1141         ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
1142         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1143             rx_filtmask);
1144         ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
1145
1146         /* fetch PLL registers */
1147         pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
1148         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
1149
1150         /* Override if required by platform data */
1151         if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
1152                 pll = sc->arge_pllcfg.pll_10;
1153         else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
1154                 pll = sc->arge_pllcfg.pll_100;
1155         else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
1156                 pll = sc->arge_pllcfg.pll_1000;
1157         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
1158
1159         /* XXX ensure pll != 0 */
1160         ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
1161
1162         /* set MII registers */
1163         /*
1164          * This was introduced to match what the Linux ag71xx ethernet
1165          * driver does.  For the AR71xx case, it does set the port
1166          * MII speed.  However, if this is done, non-gigabit speeds
1167          * are not at all reliable when speaking via RGMII through
1168          * 'bridge' PHY port that's pretending to be a local PHY.
1169          *
1170          * Until that gets root caused, and until an AR71xx + normal
1171          * PHY board is tested, leave this disabled.
1172          */
1173 #if 0
1174         ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
1175 #endif
1176 }
1177
1178
1179 static void
1180 arge_reset_dma(struct arge_softc *sc)
1181 {
1182         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
1183         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
1184
1185         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
1186         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
1187
1188         /* Clear all possible RX interrupts */
1189         while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
1190                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1191
1192         /*
1193          * Clear all possible TX interrupts
1194          */
1195         while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
1196                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1197
1198         /*
1199          * Now Rx/Tx errors
1200          */
1201         ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
1202             DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
1203         ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
1204             DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
1205
1206         /*
1207          * Force a DDR flush so any pending data is properly
1208          * flushed to RAM before underlying buffers are freed.
1209          */
1210         arge_flush_ddr(sc);
1211 }
1212
1213
1214
1215 static void
1216 arge_init(void *xsc)
1217 {
1218         struct arge_softc        *sc = xsc;
1219
1220         ARGE_LOCK(sc);
1221         arge_init_locked(sc);
1222         ARGE_UNLOCK(sc);
1223 }
1224
1225 static void
1226 arge_init_locked(struct arge_softc *sc)
1227 {
1228         struct ifnet            *ifp = sc->arge_ifp;
1229         struct mii_data         *mii;
1230
1231         ARGE_LOCK_ASSERT(sc);
1232
1233         if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1234                 return;
1235
1236         /* Init circular RX list. */
1237         if (arge_rx_ring_init(sc) != 0) {
1238                 device_printf(sc->arge_dev,
1239                     "initialization failed: no memory for rx buffers\n");
1240                 arge_stop(sc);
1241                 return;
1242         }
1243
1244         /* Init tx descriptors. */
1245         arge_tx_ring_init(sc);
1246
1247         arge_reset_dma(sc);
1248
1249         if (sc->arge_miibus) {
1250                 mii = device_get_softc(sc->arge_miibus);
1251                 mii_mediachg(mii);
1252         }
1253         else {
1254                 /*
1255                  * Sun always shines over multiPHY interface
1256                  */
1257                 sc->arge_link_status = 1;
1258         }
1259
1260         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1261         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1262
1263         if (sc->arge_miibus) {
1264                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1265                 arge_update_link_locked(sc);
1266         }
1267
1268         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1269         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1270
1271         /* Start listening */
1272         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1273
1274         /* Enable interrupts */
1275         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1276 }
1277
1278 /*
1279  * Return whether the mbuf chain is correctly aligned
1280  * for the arge TX engine.
1281  *
1282  * The TX engine requires each fragment to be aligned to a
1283  * 4 byte boundary and the size of each fragment except
1284  * the last to be a multiple of 4 bytes.
1285  *
1286  * XXX TODO: I believe this is only a bug on the AR71xx and
1287  * AR913x MACs. The later MACs (AR724x and later) does not
1288  * need this workaround.
1289  */
1290 static int
1291 arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
1292 {
1293         struct mbuf *m;
1294
1295         for (m = m0; m != NULL; m = m->m_next) {
1296                 if((mtod(m, intptr_t) & 3) != 0)
1297                         return 0;
1298                 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
1299                         return 0;
1300         }
1301         return 1;
1302 }
1303
1304 /*
1305  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1306  * pointers to the fragment pointers.
1307  */
1308 static int
1309 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
1310 {
1311         struct arge_txdesc      *txd;
1312         struct arge_desc        *desc, *prev_desc;
1313         bus_dma_segment_t       txsegs[ARGE_MAXFRAGS];
1314         int                     error, i, nsegs, prod, prev_prod;
1315         struct mbuf             *m;
1316
1317         ARGE_LOCK_ASSERT(sc);
1318
1319         /*
1320          * Fix mbuf chain, all fragments should be 4 bytes aligned and
1321          * even 4 bytes
1322          *
1323          * XXX TODO: I believe this is only a bug on the AR71xx and
1324          * AR913x MACs. The later MACs (AR724x and later) does not
1325          * need this workaround.
1326          */
1327         m = *m_head;
1328         if (! arge_mbuf_chain_is_tx_aligned(m)) {
1329                 sc->stats.tx_pkts_unaligned++;
1330                 m = m_defrag(*m_head, M_NOWAIT);
1331                 if (m == NULL) {
1332                         *m_head = NULL;
1333                         return (ENOBUFS);
1334                 }
1335                 *m_head = m;
1336         } else
1337                 sc->stats.tx_pkts_aligned++;
1338
1339         prod = sc->arge_cdata.arge_tx_prod;
1340         txd = &sc->arge_cdata.arge_txdesc[prod];
1341         error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
1342             txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1343
1344         if (error == EFBIG) {
1345                 panic("EFBIG");
1346         } else if (error != 0)
1347                 return (error);
1348
1349         if (nsegs == 0) {
1350                 m_freem(*m_head);
1351                 *m_head = NULL;
1352                 return (EIO);
1353         }
1354
1355         /* Check number of available descriptors. */
1356         if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
1357                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1358                 return (ENOBUFS);
1359         }
1360
1361         txd->tx_m = *m_head;
1362         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1363             BUS_DMASYNC_PREWRITE);
1364
1365         /*
1366          * Make a list of descriptors for this packet. DMA controller will
1367          * walk through it while arge_link is not zero.
1368          */
1369         prev_prod = prod;
1370         desc = prev_desc = NULL;
1371         for (i = 0; i < nsegs; i++) {
1372                 desc = &sc->arge_rdata.arge_tx_ring[prod];
1373                 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
1374
1375                 if (txsegs[i].ds_addr & 3)
1376                         panic("TX packet address unaligned\n");
1377
1378                 desc->packet_addr = txsegs[i].ds_addr;
1379
1380                 /* link with previous descriptor */
1381                 if (prev_desc)
1382                         prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1383
1384                 sc->arge_cdata.arge_tx_cnt++;
1385                 prev_desc = desc;
1386                 ARGE_INC(prod, ARGE_TX_RING_COUNT);
1387         }
1388
1389         /* Update producer index. */
1390         sc->arge_cdata.arge_tx_prod = prod;
1391
1392         /* Sync descriptors. */
1393         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1394             sc->arge_cdata.arge_tx_ring_map,
1395             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1396
1397         /* Start transmitting */
1398         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
1399             __func__);
1400         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1401         return (0);
1402 }
1403
1404 static void
1405 arge_start(struct ifnet *ifp)
1406 {
1407         struct arge_softc        *sc;
1408
1409         sc = ifp->if_softc;
1410
1411         ARGE_LOCK(sc);
1412         arge_start_locked(ifp);
1413         ARGE_UNLOCK(sc);
1414 }
1415
1416 static void
1417 arge_start_locked(struct ifnet *ifp)
1418 {
1419         struct arge_softc       *sc;
1420         struct mbuf             *m_head;
1421         int                     enq = 0;
1422
1423         sc = ifp->if_softc;
1424
1425         ARGE_LOCK_ASSERT(sc);
1426
1427         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1428
1429         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1430             IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1431                 return;
1432
1433         /*
1434          * Before we go any further, check whether we're already full.
1435          * The below check errors out immediately if the ring is full
1436          * and never gets a chance to set this flag. Although it's
1437          * likely never needed, this at least avoids an unexpected
1438          * situation.
1439          */
1440         if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1441                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1442                 ARGEDEBUG(sc, ARGE_DBG_ERR,
1443                     "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1444                     __func__, sc->arge_cdata.arge_tx_cnt,
1445                     ARGE_TX_RING_COUNT - 2);
1446                 return;
1447         }
1448
1449         arge_flush_ddr(sc);
1450
1451         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1452             sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1453                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1454                 if (m_head == NULL)
1455                         break;
1456
1457
1458                 /*
1459                  * Pack the data into the transmit ring.
1460                  */
1461                 if (arge_encap(sc, &m_head)) {
1462                         if (m_head == NULL)
1463                                 break;
1464                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1465                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1466                         break;
1467                 }
1468
1469                 enq++;
1470                 /*
1471                  * If there's a BPF listener, bounce a copy of this frame
1472                  * to him.
1473                  */
1474                 ETHER_BPF_MTAP(ifp, m_head);
1475         }
1476         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
1477             __func__, enq);
1478 }
1479
1480 static void
1481 arge_stop(struct arge_softc *sc)
1482 {
1483         struct ifnet        *ifp;
1484
1485         ARGE_LOCK_ASSERT(sc);
1486
1487         ifp = sc->arge_ifp;
1488         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1489         if (sc->arge_miibus)
1490                 callout_stop(&sc->arge_stat_callout);
1491
1492         /* mask out interrupts */
1493         ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1494
1495         arge_reset_dma(sc);
1496
1497         /* Flush FIFO and free any existing mbufs */
1498         arge_flush_ddr(sc);
1499         arge_rx_ring_free(sc);
1500         arge_tx_ring_free(sc);
1501 }
1502
1503
1504 static int
1505 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1506 {
1507         struct arge_softc               *sc = ifp->if_softc;
1508         struct ifreq            *ifr = (struct ifreq *) data;
1509         struct mii_data         *mii;
1510         int                     error;
1511 #ifdef DEVICE_POLLING
1512         int                     mask;
1513 #endif
1514
1515         switch (command) {
1516         case SIOCSIFFLAGS:
1517                 ARGE_LOCK(sc);
1518                 if ((ifp->if_flags & IFF_UP) != 0) {
1519                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1520                                 if (((ifp->if_flags ^ sc->arge_if_flags)
1521                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1522                                         /* XXX: handle promisc & multi flags */
1523                                 }
1524
1525                         } else {
1526                                 if (!sc->arge_detach)
1527                                         arge_init_locked(sc);
1528                         }
1529                 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1530                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1531                         arge_stop(sc);
1532                 }
1533                 sc->arge_if_flags = ifp->if_flags;
1534                 ARGE_UNLOCK(sc);
1535                 error = 0;
1536                 break;
1537         case SIOCADDMULTI:
1538         case SIOCDELMULTI:
1539                 /* XXX: implement SIOCDELMULTI */
1540                 error = 0;
1541                 break;
1542         case SIOCGIFMEDIA:
1543         case SIOCSIFMEDIA:
1544                 if (sc->arge_miibus) {
1545                         mii = device_get_softc(sc->arge_miibus);
1546                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1547                             command);
1548                 }
1549                 else
1550                         error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
1551                             command);
1552                 break;
1553         case SIOCSIFCAP:
1554                 /* XXX: Check other capabilities */
1555 #ifdef DEVICE_POLLING
1556                 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1557                 if (mask & IFCAP_POLLING) {
1558                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
1559                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1560                                 error = ether_poll_register(arge_poll, ifp);
1561                                 if (error)
1562                                         return error;
1563                                 ARGE_LOCK(sc);
1564                                 ifp->if_capenable |= IFCAP_POLLING;
1565                                 ARGE_UNLOCK(sc);
1566                         } else {
1567                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1568                                 error = ether_poll_deregister(ifp);
1569                                 ARGE_LOCK(sc);
1570                                 ifp->if_capenable &= ~IFCAP_POLLING;
1571                                 ARGE_UNLOCK(sc);
1572                         }
1573                 }
1574                 error = 0;
1575                 break;
1576 #endif
1577         default:
1578                 error = ether_ioctl(ifp, command, data);
1579                 break;
1580         }
1581
1582         return (error);
1583 }
1584
1585 /*
1586  * Set media options.
1587  */
1588 static int
1589 arge_ifmedia_upd(struct ifnet *ifp)
1590 {
1591         struct arge_softc               *sc;
1592         struct mii_data         *mii;
1593         struct mii_softc        *miisc;
1594         int                     error;
1595
1596         sc = ifp->if_softc;
1597         ARGE_LOCK(sc);
1598         mii = device_get_softc(sc->arge_miibus);
1599         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1600                 PHY_RESET(miisc);
1601         error = mii_mediachg(mii);
1602         ARGE_UNLOCK(sc);
1603
1604         return (error);
1605 }
1606
1607 /*
1608  * Report current media status.
1609  */
1610 static void
1611 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1612 {
1613         struct arge_softc               *sc = ifp->if_softc;
1614         struct mii_data         *mii;
1615
1616         mii = device_get_softc(sc->arge_miibus);
1617         ARGE_LOCK(sc);
1618         mii_pollstat(mii);
1619         ifmr->ifm_active = mii->mii_media_active;
1620         ifmr->ifm_status = mii->mii_media_status;
1621         ARGE_UNLOCK(sc);
1622 }
1623
1624 struct arge_dmamap_arg {
1625         bus_addr_t      arge_busaddr;
1626 };
1627
1628 static void
1629 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1630 {
1631         struct arge_dmamap_arg  *ctx;
1632
1633         if (error != 0)
1634                 return;
1635         ctx = arg;
1636         ctx->arge_busaddr = segs[0].ds_addr;
1637 }
1638
1639 static int
1640 arge_dma_alloc(struct arge_softc *sc)
1641 {
1642         struct arge_dmamap_arg  ctx;
1643         struct arge_txdesc      *txd;
1644         struct arge_rxdesc      *rxd;
1645         int                     error, i;
1646
1647         /* Create parent DMA tag. */
1648         error = bus_dma_tag_create(
1649             bus_get_dma_tag(sc->arge_dev),      /* parent */
1650             1, 0,                       /* alignment, boundary */
1651             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1652             BUS_SPACE_MAXADDR,          /* highaddr */
1653             NULL, NULL,                 /* filter, filterarg */
1654             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1655             0,                          /* nsegments */
1656             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1657             0,                          /* flags */
1658             NULL, NULL,                 /* lockfunc, lockarg */
1659             &sc->arge_cdata.arge_parent_tag);
1660         if (error != 0) {
1661                 device_printf(sc->arge_dev,
1662                     "failed to create parent DMA tag\n");
1663                 goto fail;
1664         }
1665         /* Create tag for Tx ring. */
1666         error = bus_dma_tag_create(
1667             sc->arge_cdata.arge_parent_tag,     /* parent */
1668             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1669             BUS_SPACE_MAXADDR,          /* lowaddr */
1670             BUS_SPACE_MAXADDR,          /* highaddr */
1671             NULL, NULL,                 /* filter, filterarg */
1672             ARGE_TX_DMA_SIZE,           /* maxsize */
1673             1,                          /* nsegments */
1674             ARGE_TX_DMA_SIZE,           /* maxsegsize */
1675             0,                          /* flags */
1676             NULL, NULL,                 /* lockfunc, lockarg */
1677             &sc->arge_cdata.arge_tx_ring_tag);
1678         if (error != 0) {
1679                 device_printf(sc->arge_dev,
1680                     "failed to create Tx ring DMA tag\n");
1681                 goto fail;
1682         }
1683
1684         /* Create tag for Rx ring. */
1685         error = bus_dma_tag_create(
1686             sc->arge_cdata.arge_parent_tag,     /* parent */
1687             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1688             BUS_SPACE_MAXADDR,          /* lowaddr */
1689             BUS_SPACE_MAXADDR,          /* highaddr */
1690             NULL, NULL,                 /* filter, filterarg */
1691             ARGE_RX_DMA_SIZE,           /* maxsize */
1692             1,                          /* nsegments */
1693             ARGE_RX_DMA_SIZE,           /* maxsegsize */
1694             0,                          /* flags */
1695             NULL, NULL,                 /* lockfunc, lockarg */
1696             &sc->arge_cdata.arge_rx_ring_tag);
1697         if (error != 0) {
1698                 device_printf(sc->arge_dev,
1699                     "failed to create Rx ring DMA tag\n");
1700                 goto fail;
1701         }
1702
1703         /* Create tag for Tx buffers. */
1704         error = bus_dma_tag_create(
1705             sc->arge_cdata.arge_parent_tag,     /* parent */
1706             sizeof(uint32_t), 0,        /* alignment, boundary */
1707             BUS_SPACE_MAXADDR,          /* lowaddr */
1708             BUS_SPACE_MAXADDR,          /* highaddr */
1709             NULL, NULL,                 /* filter, filterarg */
1710             MCLBYTES * ARGE_MAXFRAGS,   /* maxsize */
1711             ARGE_MAXFRAGS,              /* nsegments */
1712             MCLBYTES,                   /* maxsegsize */
1713             0,                          /* flags */
1714             NULL, NULL,                 /* lockfunc, lockarg */
1715             &sc->arge_cdata.arge_tx_tag);
1716         if (error != 0) {
1717                 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1718                 goto fail;
1719         }
1720
1721         /* Create tag for Rx buffers. */
1722         error = bus_dma_tag_create(
1723             sc->arge_cdata.arge_parent_tag,     /* parent */
1724             ARGE_RX_ALIGN, 0,           /* alignment, boundary */
1725             BUS_SPACE_MAXADDR,          /* lowaddr */
1726             BUS_SPACE_MAXADDR,          /* highaddr */
1727             NULL, NULL,                 /* filter, filterarg */
1728             MCLBYTES,                   /* maxsize */
1729             ARGE_MAXFRAGS,              /* nsegments */
1730             MCLBYTES,                   /* maxsegsize */
1731             0,                          /* flags */
1732             NULL, NULL,                 /* lockfunc, lockarg */
1733             &sc->arge_cdata.arge_rx_tag);
1734         if (error != 0) {
1735                 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
1736                 goto fail;
1737         }
1738
1739         /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1740         error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
1741             (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
1742             BUS_DMA_COHERENT | BUS_DMA_ZERO,
1743             &sc->arge_cdata.arge_tx_ring_map);
1744         if (error != 0) {
1745                 device_printf(sc->arge_dev,
1746                     "failed to allocate DMA'able memory for Tx ring\n");
1747                 goto fail;
1748         }
1749
1750         ctx.arge_busaddr = 0;
1751         error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
1752             sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
1753             ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1754         if (error != 0 || ctx.arge_busaddr == 0) {
1755                 device_printf(sc->arge_dev,
1756                     "failed to load DMA'able memory for Tx ring\n");
1757                 goto fail;
1758         }
1759         sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
1760
1761         /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1762         error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
1763             (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
1764             BUS_DMA_COHERENT | BUS_DMA_ZERO,
1765             &sc->arge_cdata.arge_rx_ring_map);
1766         if (error != 0) {
1767                 device_printf(sc->arge_dev,
1768                     "failed to allocate DMA'able memory for Rx ring\n");
1769                 goto fail;
1770         }
1771
1772         ctx.arge_busaddr = 0;
1773         error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
1774             sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
1775             ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1776         if (error != 0 || ctx.arge_busaddr == 0) {
1777                 device_printf(sc->arge_dev,
1778                     "failed to load DMA'able memory for Rx ring\n");
1779                 goto fail;
1780         }
1781         sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
1782
1783         /* Create DMA maps for Tx buffers. */
1784         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1785                 txd = &sc->arge_cdata.arge_txdesc[i];
1786                 txd->tx_m = NULL;
1787                 txd->tx_dmamap = NULL;
1788                 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
1789                     &txd->tx_dmamap);
1790                 if (error != 0) {
1791                         device_printf(sc->arge_dev,
1792                             "failed to create Tx dmamap\n");
1793                         goto fail;
1794                 }
1795         }
1796         /* Create DMA maps for Rx buffers. */
1797         if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1798             &sc->arge_cdata.arge_rx_sparemap)) != 0) {
1799                 device_printf(sc->arge_dev,
1800                     "failed to create spare Rx dmamap\n");
1801                 goto fail;
1802         }
1803         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1804                 rxd = &sc->arge_cdata.arge_rxdesc[i];
1805                 rxd->rx_m = NULL;
1806                 rxd->rx_dmamap = NULL;
1807                 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1808                     &rxd->rx_dmamap);
1809                 if (error != 0) {
1810                         device_printf(sc->arge_dev,
1811                             "failed to create Rx dmamap\n");
1812                         goto fail;
1813                 }
1814         }
1815
1816 fail:
1817         return (error);
1818 }
1819
1820 static void
1821 arge_dma_free(struct arge_softc *sc)
1822 {
1823         struct arge_txdesc      *txd;
1824         struct arge_rxdesc      *rxd;
1825         int                     i;
1826
1827         /* Tx ring. */
1828         if (sc->arge_cdata.arge_tx_ring_tag) {
1829                 if (sc->arge_rdata.arge_tx_ring_paddr)
1830                         bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
1831                             sc->arge_cdata.arge_tx_ring_map);
1832                 if (sc->arge_rdata.arge_tx_ring)
1833                         bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
1834                             sc->arge_rdata.arge_tx_ring,
1835                             sc->arge_cdata.arge_tx_ring_map);
1836                 sc->arge_rdata.arge_tx_ring = NULL;
1837                 sc->arge_rdata.arge_tx_ring_paddr = 0;
1838                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
1839                 sc->arge_cdata.arge_tx_ring_tag = NULL;
1840         }
1841         /* Rx ring. */
1842         if (sc->arge_cdata.arge_rx_ring_tag) {
1843                 if (sc->arge_rdata.arge_rx_ring_paddr)
1844                         bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
1845                             sc->arge_cdata.arge_rx_ring_map);
1846                 if (sc->arge_rdata.arge_rx_ring)
1847                         bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
1848                             sc->arge_rdata.arge_rx_ring,
1849                             sc->arge_cdata.arge_rx_ring_map);
1850                 sc->arge_rdata.arge_rx_ring = NULL;
1851                 sc->arge_rdata.arge_rx_ring_paddr = 0;
1852                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
1853                 sc->arge_cdata.arge_rx_ring_tag = NULL;
1854         }
1855         /* Tx buffers. */
1856         if (sc->arge_cdata.arge_tx_tag) {
1857                 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1858                         txd = &sc->arge_cdata.arge_txdesc[i];
1859                         if (txd->tx_dmamap) {
1860                                 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
1861                                     txd->tx_dmamap);
1862                                 txd->tx_dmamap = NULL;
1863                         }
1864                 }
1865                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
1866                 sc->arge_cdata.arge_tx_tag = NULL;
1867         }
1868         /* Rx buffers. */
1869         if (sc->arge_cdata.arge_rx_tag) {
1870                 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1871                         rxd = &sc->arge_cdata.arge_rxdesc[i];
1872                         if (rxd->rx_dmamap) {
1873                                 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1874                                     rxd->rx_dmamap);
1875                                 rxd->rx_dmamap = NULL;
1876                         }
1877                 }
1878                 if (sc->arge_cdata.arge_rx_sparemap) {
1879                         bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1880                             sc->arge_cdata.arge_rx_sparemap);
1881                         sc->arge_cdata.arge_rx_sparemap = 0;
1882                 }
1883                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
1884                 sc->arge_cdata.arge_rx_tag = NULL;
1885         }
1886
1887         if (sc->arge_cdata.arge_parent_tag) {
1888                 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
1889                 sc->arge_cdata.arge_parent_tag = NULL;
1890         }
1891 }
1892
1893 /*
1894  * Initialize the transmit descriptors.
1895  */
1896 static int
1897 arge_tx_ring_init(struct arge_softc *sc)
1898 {
1899         struct arge_ring_data   *rd;
1900         struct arge_txdesc      *txd;
1901         bus_addr_t              addr;
1902         int                     i;
1903
1904         sc->arge_cdata.arge_tx_prod = 0;
1905         sc->arge_cdata.arge_tx_cons = 0;
1906         sc->arge_cdata.arge_tx_cnt = 0;
1907
1908         rd = &sc->arge_rdata;
1909         bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
1910         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1911                 if (i == ARGE_TX_RING_COUNT - 1)
1912                         addr = ARGE_TX_RING_ADDR(sc, 0);
1913                 else
1914                         addr = ARGE_TX_RING_ADDR(sc, i + 1);
1915                 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
1916                 rd->arge_tx_ring[i].next_desc = addr;
1917                 txd = &sc->arge_cdata.arge_txdesc[i];
1918                 txd->tx_m = NULL;
1919         }
1920
1921         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1922             sc->arge_cdata.arge_tx_ring_map,
1923             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1924
1925         return (0);
1926 }
1927
1928 /*
1929  * Free the Tx ring, unload any pending dma transaction and free the mbuf.
1930  */
1931 static void
1932 arge_tx_ring_free(struct arge_softc *sc)
1933 {
1934         struct arge_txdesc      *txd;
1935         int                     i;
1936
1937         /* Free the Tx buffers. */
1938         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1939                 txd = &sc->arge_cdata.arge_txdesc[i];
1940                 if (txd->tx_dmamap) {
1941                         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag,
1942                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1943                         bus_dmamap_unload(sc->arge_cdata.arge_tx_tag,
1944                             txd->tx_dmamap);
1945                 }
1946                 if (txd->tx_m)
1947                         m_freem(txd->tx_m);
1948                 txd->tx_m = NULL;
1949         }
1950 }
1951
1952 /*
1953  * Initialize the RX descriptors and allocate mbufs for them. Note that
1954  * we arrange the descriptors in a closed ring, so that the last descriptor
1955  * points back to the first.
1956  */
1957 static int
1958 arge_rx_ring_init(struct arge_softc *sc)
1959 {
1960         struct arge_ring_data   *rd;
1961         struct arge_rxdesc      *rxd;
1962         bus_addr_t              addr;
1963         int                     i;
1964
1965         sc->arge_cdata.arge_rx_cons = 0;
1966
1967         rd = &sc->arge_rdata;
1968         bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
1969         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1970                 rxd = &sc->arge_cdata.arge_rxdesc[i];
1971                 if (rxd->rx_m != NULL) {
1972                         device_printf(sc->arge_dev,
1973                             "%s: ring[%d] rx_m wasn't free?\n",
1974                             __func__,
1975                             i);
1976                 }
1977                 rxd->rx_m = NULL;
1978                 rxd->desc = &rd->arge_rx_ring[i];
1979                 if (i == ARGE_RX_RING_COUNT - 1)
1980                         addr = ARGE_RX_RING_ADDR(sc, 0);
1981                 else
1982                         addr = ARGE_RX_RING_ADDR(sc, i + 1);
1983                 rd->arge_rx_ring[i].next_desc = addr;
1984                 if (arge_newbuf(sc, i) != 0) {
1985                         return (ENOBUFS);
1986                 }
1987         }
1988
1989         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1990             sc->arge_cdata.arge_rx_ring_map,
1991             BUS_DMASYNC_PREWRITE);
1992
1993         return (0);
1994 }
1995
1996 /*
1997  * Free all the buffers in the RX ring.
1998  *
1999  * TODO: ensure that DMA is disabled and no pending DMA
2000  * is lurking in the FIFO.
2001  */
2002 static void
2003 arge_rx_ring_free(struct arge_softc *sc)
2004 {
2005         int i;
2006         struct arge_rxdesc      *rxd;
2007
2008         ARGE_LOCK_ASSERT(sc);
2009
2010         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
2011                 rxd = &sc->arge_cdata.arge_rxdesc[i];
2012                 /* Unmap the mbuf */
2013                 if (rxd->rx_m != NULL) {
2014                         bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
2015                             rxd->rx_dmamap);
2016                         m_free(rxd->rx_m);
2017                         rxd->rx_m = NULL;
2018                 }
2019         }
2020 }
2021
2022 /*
2023  * Initialize an RX descriptor and attach an MBUF cluster.
2024  */
2025 static int
2026 arge_newbuf(struct arge_softc *sc, int idx)
2027 {
2028         struct arge_desc                *desc;
2029         struct arge_rxdesc      *rxd;
2030         struct mbuf             *m;
2031         bus_dma_segment_t       segs[1];
2032         bus_dmamap_t            map;
2033         int                     nsegs;
2034
2035         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2036         if (m == NULL)
2037                 return (ENOBUFS);
2038         m->m_len = m->m_pkthdr.len = MCLBYTES;
2039         m_adj(m, sizeof(uint64_t));
2040
2041         if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2042             sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2043                 m_freem(m);
2044                 return (ENOBUFS);
2045         }
2046         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2047
2048         rxd = &sc->arge_cdata.arge_rxdesc[idx];
2049         if (rxd->rx_m != NULL) {
2050                 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2051         }
2052         map = rxd->rx_dmamap;
2053         rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2054         sc->arge_cdata.arge_rx_sparemap = map;
2055         rxd->rx_m = m;
2056         desc = rxd->desc;
2057         if (segs[0].ds_addr & 3)
2058                 panic("RX packet address unaligned");
2059         desc->packet_addr = segs[0].ds_addr;
2060         desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2061
2062         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2063             sc->arge_cdata.arge_rx_ring_map,
2064             BUS_DMASYNC_PREWRITE);
2065
2066         return (0);
2067 }
2068
2069 static __inline void
2070 arge_fixup_rx(struct mbuf *m)
2071 {
2072         int             i;
2073         uint16_t        *src, *dst;
2074
2075         src = mtod(m, uint16_t *);
2076         dst = src - 1;
2077
2078         for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
2079                 *dst++ = *src++;
2080         }
2081
2082         if (m->m_len % sizeof(uint16_t))
2083                 *(uint8_t *)dst = *(uint8_t *)src;
2084
2085         m->m_data -= ETHER_ALIGN;
2086 }
2087
2088 #ifdef DEVICE_POLLING
2089 static int
2090 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2091 {
2092         struct arge_softc *sc = ifp->if_softc;
2093         int rx_npkts = 0;
2094
2095         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2096                 ARGE_LOCK(sc);
2097                 arge_tx_locked(sc);
2098                 rx_npkts = arge_rx_locked(sc);
2099                 ARGE_UNLOCK(sc);
2100         }
2101
2102         return (rx_npkts);
2103 }
2104 #endif /* DEVICE_POLLING */
2105
2106
2107 static void
2108 arge_tx_locked(struct arge_softc *sc)
2109 {
2110         struct arge_txdesc      *txd;
2111         struct arge_desc        *cur_tx;
2112         struct ifnet            *ifp;
2113         uint32_t                ctrl;
2114         int                     cons, prod;
2115
2116         ARGE_LOCK_ASSERT(sc);
2117
2118         cons = sc->arge_cdata.arge_tx_cons;
2119         prod = sc->arge_cdata.arge_tx_prod;
2120
2121         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
2122             prod);
2123
2124         if (cons == prod)
2125                 return;
2126
2127         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2128             sc->arge_cdata.arge_tx_ring_map,
2129             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2130
2131         ifp = sc->arge_ifp;
2132         /*
2133          * Go through our tx list and free mbufs for those
2134          * frames that have been transmitted.
2135          */
2136         for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
2137                 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
2138                 ctrl = cur_tx->packet_ctrl;
2139                 /* Check if descriptor has "finished" flag */
2140                 if ((ctrl & ARGE_DESC_EMPTY) == 0)
2141                         break;
2142
2143                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
2144
2145                 sc->arge_cdata.arge_tx_cnt--;
2146                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2147
2148                 txd = &sc->arge_cdata.arge_txdesc[cons];
2149
2150                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2151
2152                 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
2153                     BUS_DMASYNC_POSTWRITE);
2154                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
2155
2156                 /* Free only if it's first descriptor in list */
2157                 if (txd->tx_m)
2158                         m_freem(txd->tx_m);
2159                 txd->tx_m = NULL;
2160
2161                 /* reset descriptor */
2162                 cur_tx->packet_addr = 0;
2163         }
2164
2165         sc->arge_cdata.arge_tx_cons = cons;
2166
2167         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2168             sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
2169 }
2170
2171
2172 static int
2173 arge_rx_locked(struct arge_softc *sc)
2174 {
2175         struct arge_rxdesc      *rxd;
2176         struct ifnet            *ifp = sc->arge_ifp;
2177         int                     cons, prog, packet_len, i;
2178         struct arge_desc        *cur_rx;
2179         struct mbuf             *m;
2180         int                     rx_npkts = 0;
2181
2182         ARGE_LOCK_ASSERT(sc);
2183
2184         cons = sc->arge_cdata.arge_rx_cons;
2185
2186         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2187             sc->arge_cdata.arge_rx_ring_map,
2188             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2189
2190         for (prog = 0; prog < ARGE_RX_RING_COUNT;
2191             ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
2192                 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
2193                 rxd = &sc->arge_cdata.arge_rxdesc[cons];
2194                 m = rxd->rx_m;
2195
2196                 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
2197                        break;
2198
2199                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
2200
2201                 prog++;
2202
2203                 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
2204                 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
2205                     BUS_DMASYNC_POSTREAD);
2206                 m = rxd->rx_m;
2207
2208                 arge_fixup_rx(m);
2209                 m->m_pkthdr.rcvif = ifp;
2210                 /* Skip 4 bytes of CRC */
2211                 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
2212                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2213                 rx_npkts++;
2214
2215                 ARGE_UNLOCK(sc);
2216                 (*ifp->if_input)(ifp, m);
2217                 ARGE_LOCK(sc);
2218                 cur_rx->packet_addr = 0;
2219         }
2220
2221         if (prog > 0) {
2222
2223                 i = sc->arge_cdata.arge_rx_cons;
2224                 for (; prog > 0 ; prog--) {
2225                         if (arge_newbuf(sc, i) != 0) {
2226                                 device_printf(sc->arge_dev,
2227                                     "Failed to allocate buffer\n");
2228                                 break;
2229                         }
2230                         ARGE_INC(i, ARGE_RX_RING_COUNT);
2231                 }
2232
2233                 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2234                     sc->arge_cdata.arge_rx_ring_map,
2235                     BUS_DMASYNC_PREWRITE);
2236
2237                 sc->arge_cdata.arge_rx_cons = cons;
2238         }
2239
2240         return (rx_npkts);
2241 }
2242
2243 static int
2244 arge_intr_filter(void *arg)
2245 {
2246         struct arge_softc       *sc = arg;
2247         uint32_t                status, ints;
2248
2249         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2250         ints = ARGE_READ(sc, AR71XX_DMA_INTR);
2251
2252         ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
2253             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2254             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2255         ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2256             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2257             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2258
2259         if (status & DMA_INTR_ALL) {
2260                 sc->arge_intr_status |= status;
2261                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2262                 return (FILTER_SCHEDULE_THREAD);
2263         }
2264
2265         sc->arge_intr_status = 0;
2266         return (FILTER_STRAY);
2267 }
2268
2269 static void
2270 arge_intr(void *arg)
2271 {
2272         struct arge_softc       *sc = arg;
2273         uint32_t                status;
2274         struct ifnet            *ifp = sc->arge_ifp;
2275
2276         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2277         status |= sc->arge_intr_status;
2278
2279         ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2280             "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2281             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2282
2283         /*
2284          * Is it our interrupt at all?
2285          */
2286         if (status == 0)
2287                 return;
2288
2289         if (status & DMA_INTR_RX_BUS_ERROR) {
2290                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2291                 device_printf(sc->arge_dev, "RX bus error");
2292                 return;
2293         }
2294
2295         if (status & DMA_INTR_TX_BUS_ERROR) {
2296                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2297                 device_printf(sc->arge_dev, "TX bus error");
2298                 return;
2299         }
2300
2301         ARGE_LOCK(sc);
2302
2303         if (status & DMA_INTR_RX_PKT_RCVD)
2304                 arge_rx_locked(sc);
2305
2306         /*
2307          * RX overrun disables the receiver.
2308          * Clear indication and re-enable rx.
2309          */
2310         if ( status & DMA_INTR_RX_OVERFLOW) {
2311                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2312                 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2313                 sc->stats.rx_overflow++;
2314         }
2315
2316         if (status & DMA_INTR_TX_PKT_SENT)
2317                 arge_tx_locked(sc);
2318         /*
2319          * Underrun turns off TX. Clear underrun indication.
2320          * If there's anything left in the ring, reactivate the tx.
2321          */
2322         if (status & DMA_INTR_TX_UNDERRUN) {
2323                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2324                 sc->stats.tx_underflow++;
2325                 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
2326                     __func__, sc->arge_cdata.arge_tx_cnt);
2327                 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
2328                         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2329                             DMA_TX_CONTROL_EN);
2330                 }
2331         }
2332
2333         /*
2334          * If we've finished TXing and there's space for more packets
2335          * to be queued for TX, do so. Otherwise we may end up in a
2336          * situation where the interface send queue was filled
2337          * whilst the hardware queue was full, then the hardware
2338          * queue was drained by the interface send queue wasn't,
2339          * and thus if_start() is never called to kick-start
2340          * the send process (and all subsequent packets are simply
2341          * discarded.
2342          *
2343          * XXX TODO: make sure that the hardware deals nicely
2344          * with the possibility of the queue being enabled above
2345          * after a TX underrun, then having the hardware queue added
2346          * to below.
2347          */
2348         if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
2349             (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2350                 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2351                         arge_start_locked(ifp);
2352         }
2353
2354         /*
2355          * We handled all bits, clear status
2356          */
2357         sc->arge_intr_status = 0;
2358         ARGE_UNLOCK(sc);
2359         /*
2360          * re-enable all interrupts
2361          */
2362         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2363 }
2364
2365
2366 static void
2367 arge_tick(void *xsc)
2368 {
2369         struct arge_softc       *sc = xsc;
2370         struct mii_data         *mii;
2371
2372         ARGE_LOCK_ASSERT(sc);
2373
2374         if (sc->arge_miibus) {
2375                 mii = device_get_softc(sc->arge_miibus);
2376                 mii_tick(mii);
2377                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
2378         }
2379 }
2380
2381 int
2382 arge_multiphy_mediachange(struct ifnet *ifp)
2383 {
2384         struct arge_softc *sc = ifp->if_softc;
2385         struct ifmedia *ifm = &sc->arge_ifmedia;
2386         struct ifmedia_entry *ife = ifm->ifm_cur;
2387
2388         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2389                 return (EINVAL);
2390
2391         if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
2392                 device_printf(sc->arge_dev,
2393                     "AUTO is not supported for multiphy MAC");
2394                 return (EINVAL);
2395         }
2396
2397         /*
2398          * Ignore everything
2399          */
2400         return (0);
2401 }
2402
2403 void
2404 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2405 {
2406         struct arge_softc *sc = ifp->if_softc;
2407
2408         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2409         ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
2410             sc->arge_duplex_mode;
2411 }
2412
2413 #if defined(ARGE_MDIO)
2414 static int
2415 argemdio_probe(device_t dev)
2416 {
2417         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
2418         return (0);
2419 }
2420
2421 static int
2422 argemdio_attach(device_t dev)
2423 {
2424         struct arge_softc       *sc;
2425         int                     error = 0;
2426
2427         sc = device_get_softc(dev);
2428         sc->arge_dev = dev;
2429         sc->arge_mac_unit = device_get_unit(dev);
2430         sc->arge_rid = 0;
2431         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2432             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
2433         if (sc->arge_res == NULL) {
2434                 device_printf(dev, "couldn't map memory\n");
2435                 error = ENXIO;
2436                 goto fail;
2437         }
2438
2439         /* Reset MAC - required for AR71xx MDIO to successfully occur */
2440         arge_reset_mac(sc);
2441         /* Reset MII bus */
2442         arge_reset_miibus(sc);
2443
2444         bus_generic_probe(dev);
2445         bus_enumerate_hinted_children(dev);
2446         error = bus_generic_attach(dev);
2447 fail:
2448         return (error);
2449 }
2450
2451 static int
2452 argemdio_detach(device_t dev)
2453 {
2454         return (0);
2455 }
2456
2457 #endif