sys/mips/atheros/if_arge.c

   1 /*-
   2  * Copyright (c) 2009, Oleksandr Tymoshenko
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 /*
  32  * AR71XX gigabit ethernet driver
  33  */
  34 #ifdef HAVE_KERNEL_OPTION_HEADERS
  35 #include "opt_device_polling.h"
  36 #endif
  37
  38 #include "opt_arge.h"
  39
  40 #include <sys/param.h>
  41 #include <sys/endian.h>
  42 #include <sys/systm.h>
  43 #include <sys/sockio.h>
  44 #include <sys/lock.h>
  45 #include <sys/mbuf.h>
  46 #include <sys/malloc.h>
  47 #include <sys/mutex.h>
  48 #include <sys/kernel.h>
  49 #include <sys/module.h>
  50 #include <sys/socket.h>
  51 #include <sys/taskqueue.h>
  52 #include <sys/sysctl.h>
  53
  54 #include <net/if.h>
  55 #include <net/if_var.h>
  56 #include <net/if_media.h>
  57 #include <net/ethernet.h>
  58 #include <net/if_types.h>
  59
  60 #include <net/bpf.h>
  61
  62 #include <machine/bus.h>
  63 #include <machine/cache.h>
  64 #include <machine/resource.h>
  65 #include <vm/vm_param.h>
  66 #include <vm/vm.h>
  67 #include <vm/pmap.h>
  68 #include <machine/pmap.h>
  69 #include <sys/bus.h>
  70 #include <sys/rman.h>
  71
  72 #include <dev/mii/mii.h>
  73 #include <dev/mii/miivar.h>
  74
  75 #include <dev/pci/pcireg.h>
  76 #include <dev/pci/pcivar.h>
  77
  78 #include "opt_arge.h"
  79
  80 #if defined(ARGE_MDIO)
  81 #include <dev/etherswitch/mdio.h>
  82 #include <dev/etherswitch/miiproxy.h>
  83 #include "mdio_if.h"
  84 #endif
  85
  86
  87 MODULE_DEPEND(arge, ether, 1, 1, 1);
  88 MODULE_DEPEND(arge, miibus, 1, 1, 1);
  89 MODULE_VERSION(arge, 1);
  90
  91 #include "miibus_if.h"
  92
  93 #include <mips/atheros/ar71xxreg.h>
  94 #include <mips/atheros/ar934xreg.h>     /* XXX tsk! */
  95 #include <mips/atheros/if_argevar.h>
  96 #include <mips/atheros/ar71xx_setup.h>
  97 #include <mips/atheros/ar71xx_cpudef.h>
  98
  99 typedef enum {
 100         ARGE_DBG_MII    =       0x00000001,
 101         ARGE_DBG_INTR   =       0x00000002,
 102         ARGE_DBG_TX     =       0x00000004,
 103         ARGE_DBG_RX     =       0x00000008,
 104         ARGE_DBG_ERR    =       0x00000010,
 105         ARGE_DBG_RESET  =       0x00000020,
 106         ARGE_DBG_PLL    =       0x00000040,
 107 } arge_debug_flags;
 108
 109 static const char * arge_miicfg_str[] = {
 110         "NONE",
 111         "GMII",
 112         "MII",
 113         "RGMII",
 114         "RMII"
 115 };
 116
 117 #ifdef ARGE_DEBUG
 118 #define ARGEDEBUG(_sc, _m, ...)                                         \
 119         do {                                                            \
 120                 if ((_m) & (_sc)->arge_debug)                           \
 121                         device_printf((_sc)->arge_dev, __VA_ARGS__);    \
 122         } while (0)
 123 #else
 124 #define ARGEDEBUG(_sc, _m, ...)
 125 #endif
 126
 127 static int arge_attach(device_t);
 128 static int arge_detach(device_t);
 129 static void arge_flush_ddr(struct arge_softc *);
 130 static int arge_ifmedia_upd(struct ifnet *);
 131 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 132 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
 133 static void arge_init(void *);
 134 static void arge_init_locked(struct arge_softc *);
 135 static void arge_link_task(void *, int);
 136 static void arge_update_link_locked(struct arge_softc *sc);
 137 static void arge_set_pll(struct arge_softc *, int, int);
 138 static int arge_miibus_readreg(device_t, int, int);
 139 static void arge_miibus_statchg(device_t);
 140 static int arge_miibus_writereg(device_t, int, int, int);
 141 static int arge_probe(device_t);
 142 static void arge_reset_dma(struct arge_softc *);
 143 static int arge_resume(device_t);
 144 static int arge_rx_ring_init(struct arge_softc *);
 145 static void arge_rx_ring_free(struct arge_softc *sc);
 146 static int arge_tx_ring_init(struct arge_softc *);
 147 static void arge_tx_ring_free(struct arge_softc *);
 148 #ifdef DEVICE_POLLING
 149 static int arge_poll(struct ifnet *, enum poll_cmd, int);
 150 #endif
 151 static int arge_shutdown(device_t);
 152 static void arge_start(struct ifnet *);
 153 static void arge_start_locked(struct ifnet *);
 154 static void arge_stop(struct arge_softc *);
 155 static int arge_suspend(device_t);
 156
 157 static int arge_rx_locked(struct arge_softc *);
 158 static void arge_tx_locked(struct arge_softc *);
 159 static void arge_intr(void *);
 160 static int arge_intr_filter(void *);
 161 static void arge_tick(void *);
 162
 163 static void arge_hinted_child(device_t bus, const char *dname, int dunit);
 164
 165 /*
 166  * ifmedia callbacks for multiPHY MAC
 167  */
 168 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
 169 int arge_multiphy_mediachange(struct ifnet *);
 170
 171 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 172 static int arge_dma_alloc(struct arge_softc *);
 173 static void arge_dma_free(struct arge_softc *);
 174 static int arge_newbuf(struct arge_softc *, int);
 175 static __inline void arge_fixup_rx(struct mbuf *);
 176
 177 static device_method_t arge_methods[] = {
 178         /* Device interface */
 179         DEVMETHOD(device_probe,         arge_probe),
 180         DEVMETHOD(device_attach,        arge_attach),
 181         DEVMETHOD(device_detach,        arge_detach),
 182         DEVMETHOD(device_suspend,       arge_suspend),
 183         DEVMETHOD(device_resume,        arge_resume),
 184         DEVMETHOD(device_shutdown,      arge_shutdown),
 185
 186         /* MII interface */
 187         DEVMETHOD(miibus_readreg,       arge_miibus_readreg),
 188         DEVMETHOD(miibus_writereg,      arge_miibus_writereg),
 189         DEVMETHOD(miibus_statchg,       arge_miibus_statchg),
 190
 191         /* bus interface */
 192         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 193         DEVMETHOD(bus_hinted_child,     arge_hinted_child),
 194
 195         DEVMETHOD_END
 196 };
 197
 198 static driver_t arge_driver = {
 199         "arge",
 200         arge_methods,
 201         sizeof(struct arge_softc)
 202 };
 203
 204 static devclass_t arge_devclass;
 205
 206 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
 207 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
 208
 209 #if defined(ARGE_MDIO)
 210 static int argemdio_probe(device_t);
 211 static int argemdio_attach(device_t);
 212 static int argemdio_detach(device_t);
 213
 214 /*
 215  * Declare an additional, separate driver for accessing the MDIO bus.
 216  */
 217 static device_method_t argemdio_methods[] = {
 218         /* Device interface */
 219         DEVMETHOD(device_probe,         argemdio_probe),
 220         DEVMETHOD(device_attach,        argemdio_attach),
 221         DEVMETHOD(device_detach,        argemdio_detach),
 222
 223         /* bus interface */
 224         DEVMETHOD(bus_add_child,        device_add_child_ordered),
 225
 226         /* MDIO access */
 227         DEVMETHOD(mdio_readreg,         arge_miibus_readreg),
 228         DEVMETHOD(mdio_writereg,        arge_miibus_writereg),
 229 };
 230
 231 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods,
 232     sizeof(struct arge_softc));
 233 static devclass_t argemdio_devclass;
 234
 235 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0);
 236 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0);
 237 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0);
 238 #endif
 239
 240 /*
 241  * RedBoot passes MAC address to entry point as environment
 242  * variable. platfrom_start parses it and stores in this variable
 243  */
 244 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
 245
 246 static struct mtx miibus_mtx;
 247
 248 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
 249
 250 /*
 251  * Flushes all
 252  */
 253 static void
 254 arge_flush_ddr(struct arge_softc *sc)
 255 {
 256
 257         ar71xx_device_flush_ddr_ge(sc->arge_mac_unit);
 258 }
 259
 260 static int
 261 arge_probe(device_t dev)
 262 {
 263
 264         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
 265         return (BUS_PROBE_NOWILDCARD);
 266 }
 267
 268 static void
 269 arge_attach_sysctl(device_t dev)
 270 {
 271         struct arge_softc *sc = device_get_softc(dev);
 272         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 273         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 274
 275 #ifdef  ARGE_DEBUG
 276         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 277                 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
 278                 "arge interface debugging flags");
 279 #endif
 280
 281         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 282                 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
 283                 "number of TX aligned packets");
 284
 285         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 286                 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
 287                 0, "number of TX unaligned packets");
 288
 289 #ifdef  ARGE_DEBUG
 290         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
 291             CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
 292         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
 293             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
 294         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
 295             CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
 296 #endif
 297 }
 298
 299 static void
 300 arge_reset_mac(struct arge_softc *sc)
 301 {
 302         uint32_t reg;
 303         uint32_t reset_reg;
 304
 305         /* Step 1. Soft-reset MAC */
 306         ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
 307         DELAY(20);
 308
 309         /* Step 2. Punt the MAC core from the central reset register */
 310         /*
 311          * XXX TODO: migrate this (and other) chip specific stuff into
 312          * a chipdef method.
 313          */
 314         if (sc->arge_mac_unit == 0) {
 315                 reset_reg = RST_RESET_GE0_MAC;
 316         } else {
 317                 reset_reg = RST_RESET_GE1_MAC;
 318         }
 319
 320         /*
 321          * AR934x (and later) also needs the MDIO block reset.
 322          */
 323         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
 324            ar71xx_soc == AR71XX_SOC_AR9342 ||
 325            ar71xx_soc == AR71XX_SOC_AR9344) {
 326                 if (sc->arge_mac_unit == 0) {
 327                         reset_reg |= AR934X_RESET_GE0_MDIO;
 328                 } else {
 329                         reset_reg |= AR934X_RESET_GE1_MDIO;
 330                 }
 331         }
 332         ar71xx_device_stop(reset_reg);
 333         DELAY(100);
 334         ar71xx_device_start(reset_reg);
 335
 336         /* Step 3. Reconfigure MAC block */
 337         ARGE_WRITE(sc, AR71XX_MAC_CFG1,
 338                 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
 339                 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
 340
 341         reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
 342         reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
 343         ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
 344
 345         ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
 346 }
 347
 348 /*
 349  * These values map to the divisor values programmed into
 350  * AR71XX_MAC_MII_CFG.
 351  *
 352  * The index of each value corresponds to the divisor section
 353  * value in AR71XX_MAC_MII_CFG (ie, table[0] means '0' in
 354  * AR71XX_MAC_MII_CFG, table[1] means '1', etc.)
 355  */
 356 static const uint32_t ar71xx_mdio_div_table[] = {
 357         4, 4, 6, 8, 10, 14, 20, 28,
 358 };
 359
 360 static const uint32_t ar7240_mdio_div_table[] = {
 361         2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
 362 };
 363
 364 static const uint32_t ar933x_mdio_div_table[] = {
 365         4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
 366 };
 367
 368 /*
 369  * Lookup the divisor to use based on the given frequency.
 370  *
 371  * Returns the divisor to use, or -ve on error.
 372  */
 373 static int
 374 arge_mdio_get_divider(struct arge_softc *sc, unsigned long mdio_clock)
 375 {
 376         unsigned long ref_clock, t;
 377         const uint32_t *table;
 378         int ndivs;
 379         int i;
 380
 381         /*
 382          * This is the base MDIO frequency on the SoC.
 383          * The dividers .. well, divide. Duh.
 384          */
 385         ref_clock = ar71xx_mdio_freq();
 386
 387         /*
 388          * If either clock is undefined, just tell the
 389          * caller to fall through to the defaults.
 390          */
 391         if (ref_clock == 0 || mdio_clock == 0)
 392                 return (-EINVAL);
 393
 394         /*
 395          * Pick the correct table!
 396          */
 397         switch (ar71xx_soc) {
 398         case AR71XX_SOC_AR9330:
 399         case AR71XX_SOC_AR9331:
 400         case AR71XX_SOC_AR9341:
 401         case AR71XX_SOC_AR9342:
 402         case AR71XX_SOC_AR9344:
 403                 table = ar933x_mdio_div_table;
 404                 ndivs = nitems(ar933x_mdio_div_table);
 405                 break;
 406
 407         case AR71XX_SOC_AR7240:
 408         case AR71XX_SOC_AR7241:
 409         case AR71XX_SOC_AR7242:
 410                 table = ar7240_mdio_div_table;
 411                 ndivs = nitems(ar7240_mdio_div_table);
 412                 break;
 413
 414         default:
 415                 table = ar71xx_mdio_div_table;
 416                 ndivs = nitems(ar71xx_mdio_div_table);
 417         }
 418
 419         /*
 420          * Now, walk through the list and find the first divisor
 421          * that falls under the target MDIO frequency.
 422          *
 423          * The divisors go up, but the corresponding frequencies
 424          * are actually decreasing.
 425          */
 426         for (i = 0; i < ndivs; i++) {
 427                 t = ref_clock / table[i];
 428                 if (t <= mdio_clock) {
 429                         return (i);
 430                 }
 431         }
 432
 433         ARGEDEBUG(sc, ARGE_DBG_RESET,
 434             "No divider found; MDIO=%lu Hz; target=%lu Hz\n",
 435                 ref_clock, mdio_clock);
 436         return (-ENOENT);
 437 }
 438
 439 /*
 440  * Fetch the MDIO bus clock rate.
 441  *
 442  * For now, the default is DIV_28 for everything
 443  * bar AR934x, which will be DIV_58.
 444  *
 445  * It will definitely need updating to take into account
 446  * the MDIO bus core clock rate and the target clock
 447  * rate for the chip.
 448  */
 449 static uint32_t
 450 arge_fetch_mdiobus_clock_rate(struct arge_softc *sc)
 451 {
 452         int mdio_freq, div;
 453
 454         /*
 455          * Is the MDIO frequency defined? If so, find a divisor that
 456          * makes reasonable sense.  Don't overshoot the frequency.
 457          */
 458         if (resource_int_value(device_get_name(sc->arge_dev),
 459             device_get_unit(sc->arge_dev),
 460             "mdio_freq",
 461             &mdio_freq) == 0) {
 462                 sc->arge_mdiofreq = mdio_freq;
 463                 div = arge_mdio_get_divider(sc, sc->arge_mdiofreq);
 464                 if (bootverbose)
 465                         device_printf(sc->arge_dev,
 466                             "%s: mdio ref freq=%llu Hz, target freq=%llu Hz,"
 467                             " divisor index=%d\n",
 468                             __func__,
 469                             (unsigned long long) ar71xx_mdio_freq(),
 470                             (unsigned long long) mdio_freq,
 471                             div);
 472                 if (div >= 0)
 473                         return (div);
 474         }
 475
 476         /*
 477          * Default value(s).
 478          *
 479          * XXX obviously these need .. fixing.
 480          *
 481          * From Linux/OpenWRT:
 482          *
 483          * + 7240? DIV_6
 484          * + Builtin-switch port and not 934x? DIV_10
 485          * + Not built-in switch port and 934x? DIV_58
 486          * + .. else DIV_28.
 487          */
 488         switch (ar71xx_soc) {
 489         case AR71XX_SOC_AR9341:
 490         case AR71XX_SOC_AR9342:
 491         case AR71XX_SOC_AR9344:
 492                 return (MAC_MII_CFG_CLOCK_DIV_58);
 493                 break;
 494         default:
 495                 return (MAC_MII_CFG_CLOCK_DIV_28);
 496         }
 497 }
 498
 499 static void
 500 arge_reset_miibus(struct arge_softc *sc)
 501 {
 502         uint32_t mdio_div;
 503
 504         mdio_div = arge_fetch_mdiobus_clock_rate(sc);
 505
 506         /*
 507          * XXX AR934x and later; should we be also resetting the
 508          * MDIO block(s) using the reset register block?
 509          */
 510
 511         /* Reset MII bus; program in the default divisor */
 512         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_div);
 513         DELAY(100);
 514         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_div);
 515         DELAY(100);
 516 }
 517
 518 static void
 519 arge_fetch_pll_config(struct arge_softc *sc)
 520 {
 521         long int val;
 522
 523         if (resource_long_value(device_get_name(sc->arge_dev),
 524             device_get_unit(sc->arge_dev),
 525             "pll_10", &val) == 0) {
 526                 sc->arge_pllcfg.pll_10 = val;
 527                 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n",
 528                     __func__, (int) val);
 529         }
 530         if (resource_long_value(device_get_name(sc->arge_dev),
 531             device_get_unit(sc->arge_dev),
 532             "pll_100", &val) == 0) {
 533                 sc->arge_pllcfg.pll_100 = val;
 534                 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n",
 535                     __func__, (int) val);
 536         }
 537         if (resource_long_value(device_get_name(sc->arge_dev),
 538             device_get_unit(sc->arge_dev),
 539             "pll_1000", &val) == 0) {
 540                 sc->arge_pllcfg.pll_1000 = val;
 541                 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n",
 542                     __func__, (int) val);
 543         }
 544 }
 545
 546 static int
 547 arge_attach(device_t dev)
 548 {
 549         struct ifnet            *ifp;
 550         struct arge_softc       *sc;
 551         int                     error = 0, rid;
 552         uint32_t                rnd;
 553         int                     is_base_mac_empty, i;
 554         uint32_t                hint;
 555         long                    eeprom_mac_addr = 0;
 556         int                     miicfg = 0;
 557         int                     readascii = 0;
 558
 559         sc = device_get_softc(dev);
 560         sc->arge_dev = dev;
 561         sc->arge_mac_unit = device_get_unit(dev);
 562
 563         /*
 564          * Some units (eg the TP-Link WR-1043ND) do not have a convenient
 565          * EEPROM location to read the ethernet MAC address from.
 566          * OpenWRT simply snaffles it from a fixed location.
 567          *
 568          * Since multiple units seem to use this feature, include
 569          * a method of setting the MAC address based on an flash location
 570          * in CPU address space.
 571          *
 572          * Some vendors have decided to store the mac address as a literal
 573          * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of
 574          * an array of numbers.  Expose a hint to turn on this conversion
 575          * feature via strtol()
 576          */
 577          if (resource_long_value(device_get_name(dev), device_get_unit(dev),
 578             "eeprommac", &eeprom_mac_addr) == 0) {
 579                 int i;
 580                 const char *mac =
 581                     (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
 582                 device_printf(dev, "Overriding MAC from EEPROM\n");
 583                 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 584                         "readascii", &readascii) == 0) {
 585                         device_printf(dev, "Vendor stores MAC in ASCII format\n");
 586                         for (i = 0; i < 6; i++) {
 587                                 ar711_base_mac[i] = strtol(&(mac[i*3]), NULL, 16);
 588                         }
 589                 } else {
 590                         for (i = 0; i < 6; i++) {
 591                                 ar711_base_mac[i] = mac[i];
 592                         }
 593                 }
 594         }
 595
 596         KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
 597             ("if_arge: Only MAC0 and MAC1 supported"));
 598
 599         /*
 600          * Fetch the PLL configuration.
 601          */
 602         arge_fetch_pll_config(sc);
 603
 604         /*
 605          * Get the MII configuration, if applicable.
 606          */
 607         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 608             "miimode", &miicfg) == 0) {
 609                 /* XXX bounds check? */
 610                 device_printf(dev, "%s: overriding MII mode to '%s'\n",
 611                     __func__, arge_miicfg_str[miicfg]);
 612                 sc->arge_miicfg = miicfg;
 613         }
 614
 615         /*
 616          *  Get which PHY of 5 available we should use for this unit
 617          */
 618         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 619             "phymask", &sc->arge_phymask) != 0) {
 620                 /*
 621                  * Use port 4 (WAN) for GE0. For any other port use
 622                  * its PHY the same as its unit number
 623                  */
 624                 if (sc->arge_mac_unit == 0)
 625                         sc->arge_phymask = (1 << 4);
 626                 else
 627                         /* Use all phys up to 4 */
 628                         sc->arge_phymask = (1 << 4) - 1;
 629
 630                 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask);
 631         }
 632
 633         /*
 634          *  Get default media & duplex mode, by default its Base100T
 635          *  and full duplex
 636          */
 637         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 638             "media", &hint) != 0)
 639                 hint = 0;
 640
 641         if (hint == 1000)
 642                 sc->arge_media_type = IFM_1000_T;
 643         else
 644                 sc->arge_media_type = IFM_100_TX;
 645
 646         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 647             "fduplex", &hint) != 0)
 648                 hint = 1;
 649
 650         if (hint)
 651                 sc->arge_duplex_mode = IFM_FDX;
 652         else
 653                 sc->arge_duplex_mode = 0;
 654
 655         mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 656             MTX_DEF);
 657         callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
 658         TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
 659
 660         /* Map control/status registers. */
 661         sc->arge_rid = 0;
 662         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 663             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
 664
 665         if (sc->arge_res == NULL) {
 666                 device_printf(dev, "couldn't map memory\n");
 667                 error = ENXIO;
 668                 goto fail;
 669         }
 670
 671         /* Allocate interrupts */
 672         rid = 0;
 673         sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 674             RF_SHAREABLE | RF_ACTIVE);
 675
 676         if (sc->arge_irq == NULL) {
 677                 device_printf(dev, "couldn't map interrupt\n");
 678                 error = ENXIO;
 679                 goto fail;
 680         }
 681
 682         /* Allocate ifnet structure. */
 683         ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
 684
 685         if (ifp == NULL) {
 686                 device_printf(dev, "couldn't allocate ifnet structure\n");
 687                 error = ENOSPC;
 688                 goto fail;
 689         }
 690
 691         ifp->if_softc = sc;
 692         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 693         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 694         ifp->if_ioctl = arge_ioctl;
 695         ifp->if_start = arge_start;
 696         ifp->if_init = arge_init;
 697         sc->arge_if_flags = ifp->if_flags;
 698
 699         /* XXX: add real size */
 700         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 701         ifp->if_snd.ifq_maxlen = ifqmaxlen;
 702         IFQ_SET_READY(&ifp->if_snd);
 703
 704         ifp->if_capenable = ifp->if_capabilities;
 705 #ifdef DEVICE_POLLING
 706         ifp->if_capabilities |= IFCAP_POLLING;
 707 #endif
 708
 709         is_base_mac_empty = 1;
 710         for (i = 0; i < ETHER_ADDR_LEN; i++) {
 711                 sc->arge_eaddr[i] = ar711_base_mac[i] & 0xff;
 712                 if (sc->arge_eaddr[i] != 0)
 713                         is_base_mac_empty = 0;
 714         }
 715
 716         if (is_base_mac_empty) {
 717                 /*
 718                  * No MAC address configured. Generate the random one.
 719                  */
 720                 if  (bootverbose)
 721                         device_printf(dev,
 722                             "Generating random ethernet address.\n");
 723
 724                 rnd = arc4random();
 725                 sc->arge_eaddr[0] = 'b';
 726                 sc->arge_eaddr[1] = 's';
 727                 sc->arge_eaddr[2] = 'd';
 728                 sc->arge_eaddr[3] = (rnd >> 24) & 0xff;
 729                 sc->arge_eaddr[4] = (rnd >> 16) & 0xff;
 730                 sc->arge_eaddr[5] = (rnd >> 8) & 0xff;
 731         }
 732         if (sc->arge_mac_unit != 0)
 733                 sc->arge_eaddr[5] +=  sc->arge_mac_unit;
 734
 735         if (arge_dma_alloc(sc) != 0) {
 736                 error = ENXIO;
 737                 goto fail;
 738         }
 739
 740         /*
 741          * Don't do this for the MDIO bus case - it's already done
 742          * as part of the MDIO bus attachment.
 743          */
 744 #if !defined(ARGE_MDIO)
 745         /* Initialize the MAC block */
 746         arge_reset_mac(sc);
 747         arge_reset_miibus(sc);
 748 #endif
 749
 750         /* Configure MII mode, just for convienence */
 751         if (sc->arge_miicfg != 0)
 752                 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg);
 753
 754         /*
 755          * Set all Ethernet address registers to the same initial values
 756          * set all four addresses to 66-88-aa-cc-dd-ee
 757          */
 758         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24)
 759             | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
 760             | sc->arge_eaddr[5]);
 761         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
 762             | sc->arge_eaddr[1]);
 763
 764         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
 765             FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
 766
 767         switch (ar71xx_soc) {
 768                 case AR71XX_SOC_AR7240:
 769                 case AR71XX_SOC_AR7241:
 770                 case AR71XX_SOC_AR7242:
 771                 case AR71XX_SOC_AR9330:
 772                 case AR71XX_SOC_AR9331:
 773                 case AR71XX_SOC_AR9341:
 774                 case AR71XX_SOC_AR9342:
 775                 case AR71XX_SOC_AR9344:
 776                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
 777                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
 778                         break;
 779                 /* AR71xx, AR913x */
 780                 default:
 781                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
 782                         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
 783         }
 784
 785         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
 786             FIFO_RX_FILTMATCH_DEFAULT);
 787
 788         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
 789             FIFO_RX_FILTMASK_DEFAULT);
 790
 791 #if defined(ARGE_MDIO)
 792         sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev);
 793 #endif
 794
 795         device_printf(sc->arge_dev, "finishing attachment, phymask %04x"
 796             ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ?
 797             "null" : "set");
 798         for (i = 0; i < ARGE_NPHY; i++) {
 799                 if (((1 << i) & sc->arge_phymask) != 0) {
 800                         error = mii_attach(sc->arge_miiproxy != NULL ?
 801                             sc->arge_miiproxy : sc->arge_dev,
 802                             &sc->arge_miibus, sc->arge_ifp,
 803                             arge_ifmedia_upd, arge_ifmedia_sts,
 804                             BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0);
 805                         if (error != 0) {
 806                                 device_printf(sc->arge_dev, "unable to attach"
 807                                     " PHY %d: %d\n", i, error);
 808                                 goto fail;
 809                         }
 810                 }
 811         }
 812         if (sc->arge_miibus == NULL) {
 813                 /* no PHY, so use hard-coded values */
 814                 ifmedia_init(&sc->arge_ifmedia, 0,
 815                     arge_multiphy_mediachange,
 816                     arge_multiphy_mediastatus);
 817                 ifmedia_add(&sc->arge_ifmedia,
 818                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode,
 819                     0, NULL);
 820                 ifmedia_set(&sc->arge_ifmedia,
 821                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode);
 822                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
 823         }
 824
 825         /* Call MI attach routine. */
 826         ether_ifattach(sc->arge_ifp, sc->arge_eaddr);
 827
 828         /* Hook interrupt last to avoid having to lock softc */
 829         error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
 830             arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
 831
 832         if (error) {
 833                 device_printf(sc->arge_dev, "couldn't set up irq\n");
 834                 ether_ifdetach(sc->arge_ifp);
 835                 goto fail;
 836         }
 837
 838         /* setup sysctl variables */
 839         arge_attach_sysctl(sc->arge_dev);
 840
 841 fail:
 842         if (error)
 843                 arge_detach(dev);
 844
 845         return (error);
 846 }
 847
 848 static int
 849 arge_detach(device_t dev)
 850 {
 851         struct arge_softc       *sc = device_get_softc(dev);
 852         struct ifnet            *ifp = sc->arge_ifp;
 853
 854         KASSERT(mtx_initialized(&sc->arge_mtx),
 855             ("arge mutex not initialized"));
 856
 857         /* These should only be active if attach succeeded */
 858         if (device_is_attached(dev)) {
 859                 ARGE_LOCK(sc);
 860                 sc->arge_detach = 1;
 861 #ifdef DEVICE_POLLING
 862                 if (ifp->if_capenable & IFCAP_POLLING)
 863                         ether_poll_deregister(ifp);
 864 #endif
 865
 866                 arge_stop(sc);
 867                 ARGE_UNLOCK(sc);
 868                 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
 869                 ether_ifdetach(ifp);
 870         }
 871
 872         if (sc->arge_miibus)
 873                 device_delete_child(dev, sc->arge_miibus);
 874
 875         if (sc->arge_miiproxy)
 876                 device_delete_child(dev, sc->arge_miiproxy);
 877
 878         bus_generic_detach(dev);
 879
 880         if (sc->arge_intrhand)
 881                 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
 882
 883         if (sc->arge_res)
 884                 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
 885                     sc->arge_res);
 886
 887         if (ifp)
 888                 if_free(ifp);
 889
 890         arge_dma_free(sc);
 891
 892         mtx_destroy(&sc->arge_mtx);
 893
 894         return (0);
 895
 896 }
 897
 898 static int
 899 arge_suspend(device_t dev)
 900 {
 901
 902         panic("%s", __func__);
 903         return 0;
 904 }
 905
 906 static int
 907 arge_resume(device_t dev)
 908 {
 909
 910         panic("%s", __func__);
 911         return 0;
 912 }
 913
 914 static int
 915 arge_shutdown(device_t dev)
 916 {
 917         struct arge_softc       *sc;
 918
 919         sc = device_get_softc(dev);
 920
 921         ARGE_LOCK(sc);
 922         arge_stop(sc);
 923         ARGE_UNLOCK(sc);
 924
 925         return (0);
 926 }
 927
 928 static void
 929 arge_hinted_child(device_t bus, const char *dname, int dunit)
 930 {
 931         BUS_ADD_CHILD(bus, 0, dname, dunit);
 932         device_printf(bus, "hinted child %s%d\n", dname, dunit);
 933 }
 934
 935 static int
 936 arge_miibus_readreg(device_t dev, int phy, int reg)
 937 {
 938         struct arge_softc * sc = device_get_softc(dev);
 939         int i, result;
 940         uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
 941             | (reg & MAC_MII_REG_MASK);
 942
 943         mtx_lock(&miibus_mtx);
 944         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
 945         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
 946         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
 947
 948         i = ARGE_MII_TIMEOUT;
 949         while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
 950             MAC_MII_INDICATOR_BUSY) && (i--))
 951                 DELAY(5);
 952
 953         if (i < 0) {
 954                 mtx_unlock(&miibus_mtx);
 955                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
 956                 /* XXX: return ERRNO istead? */
 957                 return (-1);
 958         }
 959
 960         result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
 961         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
 962         mtx_unlock(&miibus_mtx);
 963
 964         ARGEDEBUG(sc, ARGE_DBG_MII,
 965             "%s: phy=%d, reg=%02x, value[%08x]=%04x\n",
 966             __func__, phy, reg, addr, result);
 967
 968         return (result);
 969 }
 970
 971 static int
 972 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
 973 {
 974         struct arge_softc * sc = device_get_softc(dev);
 975         int i;
 976         uint32_t addr =
 977             (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
 978
 979         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
 980             phy, reg, data);
 981
 982         mtx_lock(&miibus_mtx);
 983         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
 984         ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
 985
 986         i = ARGE_MII_TIMEOUT;
 987         while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) &
 988             MAC_MII_INDICATOR_BUSY) && (i--))
 989                 DELAY(5);
 990
 991         mtx_unlock(&miibus_mtx);
 992
 993         if (i < 0) {
 994                 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
 995                 /* XXX: return ERRNO istead? */
 996                 return (-1);
 997         }
 998
 999         return (0);
1000 }
1001
1002 static void
1003 arge_miibus_statchg(device_t dev)
1004 {
1005         struct arge_softc       *sc;
1006
1007         sc = device_get_softc(dev);
1008         taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
1009 }
1010
1011 static void
1012 arge_link_task(void *arg, int pending)
1013 {
1014         struct arge_softc       *sc;
1015         sc = (struct arge_softc *)arg;
1016
1017         ARGE_LOCK(sc);
1018         arge_update_link_locked(sc);
1019         ARGE_UNLOCK(sc);
1020 }
1021
1022 static void
1023 arge_update_link_locked(struct arge_softc *sc)
1024 {
1025         struct mii_data         *mii;
1026         struct ifnet            *ifp;
1027         uint32_t                media, duplex;
1028
1029         mii = device_get_softc(sc->arge_miibus);
1030         ifp = sc->arge_ifp;
1031         if (mii == NULL || ifp == NULL ||
1032             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1033                 return;
1034         }
1035
1036         if (mii->mii_media_status & IFM_ACTIVE) {
1037
1038                 media = IFM_SUBTYPE(mii->mii_media_active);
1039                 if (media != IFM_NONE) {
1040                         sc->arge_link_status = 1;
1041                         duplex = mii->mii_media_active & IFM_GMASK;
1042                         ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
1043                             __func__,
1044                             media,
1045                             duplex);
1046                         arge_set_pll(sc, media, duplex);
1047                 }
1048         } else {
1049                 sc->arge_link_status = 0;
1050         }
1051 }
1052
1053 static void
1054 arge_set_pll(struct arge_softc *sc, int media, int duplex)
1055 {
1056         uint32_t                cfg, ifcontrol, rx_filtmask;
1057         uint32_t                fifo_tx, pll;
1058         int if_speed;
1059
1060         ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media,
1061             duplex == IFM_FDX ? "full" : "half");
1062         cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
1063         cfg &= ~(MAC_CFG2_IFACE_MODE_1000
1064             | MAC_CFG2_IFACE_MODE_10_100
1065             | MAC_CFG2_FULL_DUPLEX);
1066
1067         if (duplex == IFM_FDX)
1068                 cfg |= MAC_CFG2_FULL_DUPLEX;
1069
1070         ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
1071         ifcontrol &= ~MAC_IFCONTROL_SPEED;
1072         rx_filtmask =
1073             ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
1074         rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
1075
1076         switch(media) {
1077         case IFM_10_T:
1078                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1079                 if_speed = 10;
1080                 break;
1081         case IFM_100_TX:
1082                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
1083                 ifcontrol |= MAC_IFCONTROL_SPEED;
1084                 if_speed = 100;
1085                 break;
1086         case IFM_1000_T:
1087         case IFM_1000_SX:
1088                 cfg |= MAC_CFG2_IFACE_MODE_1000;
1089                 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
1090                 if_speed = 1000;
1091                 break;
1092         default:
1093                 if_speed = 100;
1094                 device_printf(sc->arge_dev,
1095                     "Unknown media %d\n", media);
1096         }
1097
1098         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed);
1099
1100         switch (ar71xx_soc) {
1101                 case AR71XX_SOC_AR7240:
1102                 case AR71XX_SOC_AR7241:
1103                 case AR71XX_SOC_AR7242:
1104                 case AR71XX_SOC_AR9330:
1105                 case AR71XX_SOC_AR9331:
1106                 case AR71XX_SOC_AR9341:
1107                 case AR71XX_SOC_AR9342:
1108                 case AR71XX_SOC_AR9344:
1109                         fifo_tx = 0x01f00140;
1110                         break;
1111                 case AR71XX_SOC_AR9130:
1112                 case AR71XX_SOC_AR9132:
1113                         fifo_tx = 0x00780fff;
1114                         break;
1115                 /* AR71xx */
1116                 default:
1117                         fifo_tx = 0x008001ff;
1118         }
1119
1120         ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
1121         ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
1122         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
1123             rx_filtmask);
1124         ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
1125
1126         /* fetch PLL registers */
1127         pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
1128         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll);
1129
1130         /* Override if required by platform data */
1131         if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0)
1132                 pll = sc->arge_pllcfg.pll_10;
1133         else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0)
1134                 pll = sc->arge_pllcfg.pll_100;
1135         else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0)
1136                 pll = sc->arge_pllcfg.pll_1000;
1137         ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll);
1138
1139         /* XXX ensure pll != 0 */
1140         ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
1141
1142         /* set MII registers */
1143         /*
1144          * This was introduced to match what the Linux ag71xx ethernet
1145          * driver does.  For the AR71xx case, it does set the port
1146          * MII speed.  However, if this is done, non-gigabit speeds
1147          * are not at all reliable when speaking via RGMII through
1148          * 'bridge' PHY port that's pretending to be a local PHY.
1149          *
1150          * Until that gets root caused, and until an AR71xx + normal
1151          * PHY board is tested, leave this disabled.
1152          */
1153 #if 0
1154         ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
1155 #endif
1156 }
1157
1158
1159 static void
1160 arge_reset_dma(struct arge_softc *sc)
1161 {
1162         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
1163         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
1164
1165         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
1166         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
1167
1168         /* Clear all possible RX interrupts */
1169         while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
1170                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1171
1172         /*
1173          * Clear all possible TX interrupts
1174          */
1175         while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
1176                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1177
1178         /*
1179          * Now Rx/Tx errors
1180          */
1181         ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
1182             DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
1183         ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
1184             DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
1185
1186         /*
1187          * Force a DDR flush so any pending data is properly
1188          * flushed to RAM before underlying buffers are freed.
1189          */
1190         arge_flush_ddr(sc);
1191 }
1192
1193
1194
1195 static void
1196 arge_init(void *xsc)
1197 {
1198         struct arge_softc        *sc = xsc;
1199
1200         ARGE_LOCK(sc);
1201         arge_init_locked(sc);
1202         ARGE_UNLOCK(sc);
1203 }
1204
1205 static void
1206 arge_init_locked(struct arge_softc *sc)
1207 {
1208         struct ifnet            *ifp = sc->arge_ifp;
1209         struct mii_data         *mii;
1210
1211         ARGE_LOCK_ASSERT(sc);
1212
1213         if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1214                 return;
1215
1216         /* Init circular RX list. */
1217         if (arge_rx_ring_init(sc) != 0) {
1218                 device_printf(sc->arge_dev,
1219                     "initialization failed: no memory for rx buffers\n");
1220                 arge_stop(sc);
1221                 return;
1222         }
1223
1224         /* Init tx descriptors. */
1225         arge_tx_ring_init(sc);
1226
1227         arge_reset_dma(sc);
1228
1229         if (sc->arge_miibus) {
1230                 mii = device_get_softc(sc->arge_miibus);
1231                 mii_mediachg(mii);
1232         }
1233         else {
1234                 /*
1235                  * Sun always shines over multiPHY interface
1236                  */
1237                 sc->arge_link_status = 1;
1238         }
1239
1240         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1241         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1242
1243         if (sc->arge_miibus) {
1244                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1245                 arge_update_link_locked(sc);
1246         }
1247
1248         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
1249         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
1250
1251         /* Start listening */
1252         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1253
1254         /* Enable interrupts */
1255         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1256 }
1257
1258 /*
1259  * Return whether the mbuf chain is correctly aligned
1260  * for the arge TX engine.
1261  *
1262  * The TX engine requires each fragment to be aligned to a
1263  * 4 byte boundary and the size of each fragment except
1264  * the last to be a multiple of 4 bytes.
1265  *
1266  * XXX TODO: I believe this is only a bug on the AR71xx and
1267  * AR913x MACs. The later MACs (AR724x and later) does not
1268  * need this workaround.
1269  */
1270 static int
1271 arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
1272 {
1273         struct mbuf *m;
1274
1275         for (m = m0; m != NULL; m = m->m_next) {
1276                 if((mtod(m, intptr_t) & 3) != 0)
1277                         return 0;
1278                 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
1279                         return 0;
1280         }
1281         return 1;
1282 }
1283
1284 /*
1285  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1286  * pointers to the fragment pointers.
1287  */
1288 static int
1289 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
1290 {
1291         struct arge_txdesc      *txd;
1292         struct arge_desc        *desc, *prev_desc;
1293         bus_dma_segment_t       txsegs[ARGE_MAXFRAGS];
1294         int                     error, i, nsegs, prod, prev_prod;
1295         struct mbuf             *m;
1296
1297         ARGE_LOCK_ASSERT(sc);
1298
1299         /*
1300          * Fix mbuf chain, all fragments should be 4 bytes aligned and
1301          * even 4 bytes
1302          *
1303          * XXX TODO: I believe this is only a bug on the AR71xx and
1304          * AR913x MACs. The later MACs (AR724x and later) does not
1305          * need this workaround.
1306          */
1307         m = *m_head;
1308         if (! arge_mbuf_chain_is_tx_aligned(m)) {
1309                 sc->stats.tx_pkts_unaligned++;
1310                 m = m_defrag(*m_head, M_NOWAIT);
1311                 if (m == NULL) {
1312                         *m_head = NULL;
1313                         return (ENOBUFS);
1314                 }
1315                 *m_head = m;
1316         } else
1317                 sc->stats.tx_pkts_aligned++;
1318
1319         prod = sc->arge_cdata.arge_tx_prod;
1320         txd = &sc->arge_cdata.arge_txdesc[prod];
1321         error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
1322             txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1323
1324         if (error == EFBIG) {
1325                 panic("EFBIG");
1326         } else if (error != 0)
1327                 return (error);
1328
1329         if (nsegs == 0) {
1330                 m_freem(*m_head);
1331                 *m_head = NULL;
1332                 return (EIO);
1333         }
1334
1335         /* Check number of available descriptors. */
1336         if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
1337                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1338                 return (ENOBUFS);
1339         }
1340
1341         txd->tx_m = *m_head;
1342         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1343             BUS_DMASYNC_PREWRITE);
1344
1345         /*
1346          * Make a list of descriptors for this packet. DMA controller will
1347          * walk through it while arge_link is not zero.
1348          */
1349         prev_prod = prod;
1350         desc = prev_desc = NULL;
1351         for (i = 0; i < nsegs; i++) {
1352                 desc = &sc->arge_rdata.arge_tx_ring[prod];
1353                 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
1354
1355                 if (txsegs[i].ds_addr & 3)
1356                         panic("TX packet address unaligned\n");
1357
1358                 desc->packet_addr = txsegs[i].ds_addr;
1359
1360                 /* link with previous descriptor */
1361                 if (prev_desc)
1362                         prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1363
1364                 sc->arge_cdata.arge_tx_cnt++;
1365                 prev_desc = desc;
1366                 ARGE_INC(prod, ARGE_TX_RING_COUNT);
1367         }
1368
1369         /* Update producer index. */
1370         sc->arge_cdata.arge_tx_prod = prod;
1371
1372         /* Sync descriptors. */
1373         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1374             sc->arge_cdata.arge_tx_ring_map,
1375             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1376
1377         /* Start transmitting */
1378         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
1379             __func__);
1380         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
1381         return (0);
1382 }
1383
1384 static void
1385 arge_start(struct ifnet *ifp)
1386 {
1387         struct arge_softc        *sc;
1388
1389         sc = ifp->if_softc;
1390
1391         ARGE_LOCK(sc);
1392         arge_start_locked(ifp);
1393         ARGE_UNLOCK(sc);
1394 }
1395
1396 static void
1397 arge_start_locked(struct ifnet *ifp)
1398 {
1399         struct arge_softc       *sc;
1400         struct mbuf             *m_head;
1401         int                     enq = 0;
1402
1403         sc = ifp->if_softc;
1404
1405         ARGE_LOCK_ASSERT(sc);
1406
1407         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1408
1409         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1410             IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1411                 return;
1412
1413         /*
1414          * Before we go any further, check whether we're already full.
1415          * The below check errors out immediately if the ring is full
1416          * and never gets a chance to set this flag. Although it's
1417          * likely never needed, this at least avoids an unexpected
1418          * situation.
1419          */
1420         if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1421                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1422                 ARGEDEBUG(sc, ARGE_DBG_ERR,
1423                     "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1424                     __func__, sc->arge_cdata.arge_tx_cnt,
1425                     ARGE_TX_RING_COUNT - 2);
1426                 return;
1427         }
1428
1429         arge_flush_ddr(sc);
1430
1431         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1432             sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1433                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1434                 if (m_head == NULL)
1435                         break;
1436
1437
1438                 /*
1439                  * Pack the data into the transmit ring.
1440                  */
1441                 if (arge_encap(sc, &m_head)) {
1442                         if (m_head == NULL)
1443                                 break;
1444                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1445                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1446                         break;
1447                 }
1448
1449                 enq++;
1450                 /*
1451                  * If there's a BPF listener, bounce a copy of this frame
1452                  * to him.
1453                  */
1454                 ETHER_BPF_MTAP(ifp, m_head);
1455         }
1456         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n",
1457             __func__, enq);
1458 }
1459
1460 static void
1461 arge_stop(struct arge_softc *sc)
1462 {
1463         struct ifnet        *ifp;
1464
1465         ARGE_LOCK_ASSERT(sc);
1466
1467         ifp = sc->arge_ifp;
1468         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1469         if (sc->arge_miibus)
1470                 callout_stop(&sc->arge_stat_callout);
1471
1472         /* mask out interrupts */
1473         ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1474
1475         arge_reset_dma(sc);
1476
1477         /* Flush FIFO and free any existing mbufs */
1478         arge_flush_ddr(sc);
1479         arge_rx_ring_free(sc);
1480         arge_tx_ring_free(sc);
1481 }
1482
1483
1484 static int
1485 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1486 {
1487         struct arge_softc               *sc = ifp->if_softc;
1488         struct ifreq            *ifr = (struct ifreq *) data;
1489         struct mii_data         *mii;
1490         int                     error;
1491 #ifdef DEVICE_POLLING
1492         int                     mask;
1493 #endif
1494
1495         switch (command) {
1496         case SIOCSIFFLAGS:
1497                 ARGE_LOCK(sc);
1498                 if ((ifp->if_flags & IFF_UP) != 0) {
1499                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1500                                 if (((ifp->if_flags ^ sc->arge_if_flags)
1501                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1502                                         /* XXX: handle promisc & multi flags */
1503                                 }
1504
1505                         } else {
1506                                 if (!sc->arge_detach)
1507                                         arge_init_locked(sc);
1508                         }
1509                 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1510                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1511                         arge_stop(sc);
1512                 }
1513                 sc->arge_if_flags = ifp->if_flags;
1514                 ARGE_UNLOCK(sc);
1515                 error = 0;
1516                 break;
1517         case SIOCADDMULTI:
1518         case SIOCDELMULTI:
1519                 /* XXX: implement SIOCDELMULTI */
1520                 error = 0;
1521                 break;
1522         case SIOCGIFMEDIA:
1523         case SIOCSIFMEDIA:
1524                 if (sc->arge_miibus) {
1525                         mii = device_get_softc(sc->arge_miibus);
1526                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1527                             command);
1528                 }
1529                 else
1530                         error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia,
1531                             command);
1532                 break;
1533         case SIOCSIFCAP:
1534                 /* XXX: Check other capabilities */
1535 #ifdef DEVICE_POLLING
1536                 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1537                 if (mask & IFCAP_POLLING) {
1538                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
1539                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1540                                 error = ether_poll_register(arge_poll, ifp);
1541                                 if (error)
1542                                         return error;
1543                                 ARGE_LOCK(sc);
1544                                 ifp->if_capenable |= IFCAP_POLLING;
1545                                 ARGE_UNLOCK(sc);
1546                         } else {
1547                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1548                                 error = ether_poll_deregister(ifp);
1549                                 ARGE_LOCK(sc);
1550                                 ifp->if_capenable &= ~IFCAP_POLLING;
1551                                 ARGE_UNLOCK(sc);
1552                         }
1553                 }
1554                 error = 0;
1555                 break;
1556 #endif
1557         default:
1558                 error = ether_ioctl(ifp, command, data);
1559                 break;
1560         }
1561
1562         return (error);
1563 }
1564
1565 /*
1566  * Set media options.
1567  */
1568 static int
1569 arge_ifmedia_upd(struct ifnet *ifp)
1570 {
1571         struct arge_softc               *sc;
1572         struct mii_data         *mii;
1573         struct mii_softc        *miisc;
1574         int                     error;
1575
1576         sc = ifp->if_softc;
1577         ARGE_LOCK(sc);
1578         mii = device_get_softc(sc->arge_miibus);
1579         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1580                 PHY_RESET(miisc);
1581         error = mii_mediachg(mii);
1582         ARGE_UNLOCK(sc);
1583
1584         return (error);
1585 }
1586
1587 /*
1588  * Report current media status.
1589  */
1590 static void
1591 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1592 {
1593         struct arge_softc               *sc = ifp->if_softc;
1594         struct mii_data         *mii;
1595
1596         mii = device_get_softc(sc->arge_miibus);
1597         ARGE_LOCK(sc);
1598         mii_pollstat(mii);
1599         ifmr->ifm_active = mii->mii_media_active;
1600         ifmr->ifm_status = mii->mii_media_status;
1601         ARGE_UNLOCK(sc);
1602 }
1603
1604 struct arge_dmamap_arg {
1605         bus_addr_t      arge_busaddr;
1606 };
1607
1608 static void
1609 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1610 {
1611         struct arge_dmamap_arg  *ctx;
1612
1613         if (error != 0)
1614                 return;
1615         ctx = arg;
1616         ctx->arge_busaddr = segs[0].ds_addr;
1617 }
1618
1619 static int
1620 arge_dma_alloc(struct arge_softc *sc)
1621 {
1622         struct arge_dmamap_arg  ctx;
1623         struct arge_txdesc      *txd;
1624         struct arge_rxdesc      *rxd;
1625         int                     error, i;
1626
1627         /* Create parent DMA tag. */
1628         error = bus_dma_tag_create(
1629             bus_get_dma_tag(sc->arge_dev),      /* parent */
1630             1, 0,                       /* alignment, boundary */
1631             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1632             BUS_SPACE_MAXADDR,          /* highaddr */
1633             NULL, NULL,                 /* filter, filterarg */
1634             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1635             0,                          /* nsegments */
1636             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1637             0,                          /* flags */
1638             NULL, NULL,                 /* lockfunc, lockarg */
1639             &sc->arge_cdata.arge_parent_tag);
1640         if (error != 0) {
1641                 device_printf(sc->arge_dev,
1642                     "failed to create parent DMA tag\n");
1643                 goto fail;
1644         }
1645         /* Create tag for Tx ring. */
1646         error = bus_dma_tag_create(
1647             sc->arge_cdata.arge_parent_tag,     /* parent */
1648             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1649             BUS_SPACE_MAXADDR,          /* lowaddr */
1650             BUS_SPACE_MAXADDR,          /* highaddr */
1651             NULL, NULL,                 /* filter, filterarg */
1652             ARGE_TX_DMA_SIZE,           /* maxsize */
1653             1,                          /* nsegments */
1654             ARGE_TX_DMA_SIZE,           /* maxsegsize */
1655             0,                          /* flags */
1656             NULL, NULL,                 /* lockfunc, lockarg */
1657             &sc->arge_cdata.arge_tx_ring_tag);
1658         if (error != 0) {
1659                 device_printf(sc->arge_dev,
1660                     "failed to create Tx ring DMA tag\n");
1661                 goto fail;
1662         }
1663
1664         /* Create tag for Rx ring. */
1665         error = bus_dma_tag_create(
1666             sc->arge_cdata.arge_parent_tag,     /* parent */
1667             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
1668             BUS_SPACE_MAXADDR,          /* lowaddr */
1669             BUS_SPACE_MAXADDR,          /* highaddr */
1670             NULL, NULL,                 /* filter, filterarg */
1671             ARGE_RX_DMA_SIZE,           /* maxsize */
1672             1,                          /* nsegments */
1673             ARGE_RX_DMA_SIZE,           /* maxsegsize */
1674             0,                          /* flags */
1675             NULL, NULL,                 /* lockfunc, lockarg */
1676             &sc->arge_cdata.arge_rx_ring_tag);
1677         if (error != 0) {
1678                 device_printf(sc->arge_dev,
1679                     "failed to create Rx ring DMA tag\n");
1680                 goto fail;
1681         }
1682
1683         /* Create tag for Tx buffers. */
1684         error = bus_dma_tag_create(
1685             sc->arge_cdata.arge_parent_tag,     /* parent */
1686             sizeof(uint32_t), 0,        /* alignment, boundary */
1687             BUS_SPACE_MAXADDR,          /* lowaddr */
1688             BUS_SPACE_MAXADDR,          /* highaddr */
1689             NULL, NULL,                 /* filter, filterarg */
1690             MCLBYTES * ARGE_MAXFRAGS,   /* maxsize */
1691             ARGE_MAXFRAGS,              /* nsegments */
1692             MCLBYTES,                   /* maxsegsize */
1693             0,                          /* flags */
1694             NULL, NULL,                 /* lockfunc, lockarg */
1695             &sc->arge_cdata.arge_tx_tag);
1696         if (error != 0) {
1697                 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1698                 goto fail;
1699         }
1700
1701         /* Create tag for Rx buffers. */
1702         error = bus_dma_tag_create(
1703             sc->arge_cdata.arge_parent_tag,     /* parent */
1704             ARGE_RX_ALIGN, 0,           /* alignment, boundary */
1705             BUS_SPACE_MAXADDR,          /* lowaddr */
1706             BUS_SPACE_MAXADDR,          /* highaddr */
1707             NULL, NULL,                 /* filter, filterarg */
1708             MCLBYTES,                   /* maxsize */
1709             ARGE_MAXFRAGS,              /* nsegments */
1710             MCLBYTES,                   /* maxsegsize */
1711             0,                          /* flags */
1712             NULL, NULL,                 /* lockfunc, lockarg */
1713             &sc->arge_cdata.arge_rx_tag);
1714         if (error != 0) {
1715                 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
1716                 goto fail;
1717         }
1718
1719         /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1720         error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
1721             (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
1722             BUS_DMA_COHERENT | BUS_DMA_ZERO,
1723             &sc->arge_cdata.arge_tx_ring_map);
1724         if (error != 0) {
1725                 device_printf(sc->arge_dev,
1726                     "failed to allocate DMA'able memory for Tx ring\n");
1727                 goto fail;
1728         }
1729
1730         ctx.arge_busaddr = 0;
1731         error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
1732             sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
1733             ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1734         if (error != 0 || ctx.arge_busaddr == 0) {
1735                 device_printf(sc->arge_dev,
1736                     "failed to load DMA'able memory for Tx ring\n");
1737                 goto fail;
1738         }
1739         sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
1740
1741         /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1742         error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
1743             (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
1744             BUS_DMA_COHERENT | BUS_DMA_ZERO,
1745             &sc->arge_cdata.arge_rx_ring_map);
1746         if (error != 0) {
1747                 device_printf(sc->arge_dev,
1748                     "failed to allocate DMA'able memory for Rx ring\n");
1749                 goto fail;
1750         }
1751
1752         ctx.arge_busaddr = 0;
1753         error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
1754             sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
1755             ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1756         if (error != 0 || ctx.arge_busaddr == 0) {
1757                 device_printf(sc->arge_dev,
1758                     "failed to load DMA'able memory for Rx ring\n");
1759                 goto fail;
1760         }
1761         sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
1762
1763         /* Create DMA maps for Tx buffers. */
1764         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1765                 txd = &sc->arge_cdata.arge_txdesc[i];
1766                 txd->tx_m = NULL;
1767                 txd->tx_dmamap = NULL;
1768                 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
1769                     &txd->tx_dmamap);
1770                 if (error != 0) {
1771                         device_printf(sc->arge_dev,
1772                             "failed to create Tx dmamap\n");
1773                         goto fail;
1774                 }
1775         }
1776         /* Create DMA maps for Rx buffers. */
1777         if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1778             &sc->arge_cdata.arge_rx_sparemap)) != 0) {
1779                 device_printf(sc->arge_dev,
1780                     "failed to create spare Rx dmamap\n");
1781                 goto fail;
1782         }
1783         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1784                 rxd = &sc->arge_cdata.arge_rxdesc[i];
1785                 rxd->rx_m = NULL;
1786                 rxd->rx_dmamap = NULL;
1787                 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1788                     &rxd->rx_dmamap);
1789                 if (error != 0) {
1790                         device_printf(sc->arge_dev,
1791                             "failed to create Rx dmamap\n");
1792                         goto fail;
1793                 }
1794         }
1795
1796 fail:
1797         return (error);
1798 }
1799
1800 static void
1801 arge_dma_free(struct arge_softc *sc)
1802 {
1803         struct arge_txdesc      *txd;
1804         struct arge_rxdesc      *rxd;
1805         int                     i;
1806
1807         /* Tx ring. */
1808         if (sc->arge_cdata.arge_tx_ring_tag) {
1809                 if (sc->arge_cdata.arge_tx_ring_map)
1810                         bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
1811                             sc->arge_cdata.arge_tx_ring_map);
1812                 if (sc->arge_cdata.arge_tx_ring_map &&
1813                     sc->arge_rdata.arge_tx_ring)
1814                         bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
1815                             sc->arge_rdata.arge_tx_ring,
1816                             sc->arge_cdata.arge_tx_ring_map);
1817                 sc->arge_rdata.arge_tx_ring = NULL;
1818                 sc->arge_cdata.arge_tx_ring_map = NULL;
1819                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
1820                 sc->arge_cdata.arge_tx_ring_tag = NULL;
1821         }
1822         /* Rx ring. */
1823         if (sc->arge_cdata.arge_rx_ring_tag) {
1824                 if (sc->arge_cdata.arge_rx_ring_map)
1825                         bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
1826                             sc->arge_cdata.arge_rx_ring_map);
1827                 if (sc->arge_cdata.arge_rx_ring_map &&
1828                     sc->arge_rdata.arge_rx_ring)
1829                         bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
1830                             sc->arge_rdata.arge_rx_ring,
1831                             sc->arge_cdata.arge_rx_ring_map);
1832                 sc->arge_rdata.arge_rx_ring = NULL;
1833                 sc->arge_cdata.arge_rx_ring_map = NULL;
1834                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
1835                 sc->arge_cdata.arge_rx_ring_tag = NULL;
1836         }
1837         /* Tx buffers. */
1838         if (sc->arge_cdata.arge_tx_tag) {
1839                 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1840                         txd = &sc->arge_cdata.arge_txdesc[i];
1841                         if (txd->tx_dmamap) {
1842                                 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
1843                                     txd->tx_dmamap);
1844                                 txd->tx_dmamap = NULL;
1845                         }
1846                 }
1847                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
1848                 sc->arge_cdata.arge_tx_tag = NULL;
1849         }
1850         /* Rx buffers. */
1851         if (sc->arge_cdata.arge_rx_tag) {
1852                 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1853                         rxd = &sc->arge_cdata.arge_rxdesc[i];
1854                         if (rxd->rx_dmamap) {
1855                                 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1856                                     rxd->rx_dmamap);
1857                                 rxd->rx_dmamap = NULL;
1858                         }
1859                 }
1860                 if (sc->arge_cdata.arge_rx_sparemap) {
1861                         bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1862                             sc->arge_cdata.arge_rx_sparemap);
1863                         sc->arge_cdata.arge_rx_sparemap = 0;
1864                 }
1865                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
1866                 sc->arge_cdata.arge_rx_tag = NULL;
1867         }
1868
1869         if (sc->arge_cdata.arge_parent_tag) {
1870                 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
1871                 sc->arge_cdata.arge_parent_tag = NULL;
1872         }
1873 }
1874
1875 /*
1876  * Initialize the transmit descriptors.
1877  */
1878 static int
1879 arge_tx_ring_init(struct arge_softc *sc)
1880 {
1881         struct arge_ring_data   *rd;
1882         struct arge_txdesc      *txd;
1883         bus_addr_t              addr;
1884         int                     i;
1885
1886         sc->arge_cdata.arge_tx_prod = 0;
1887         sc->arge_cdata.arge_tx_cons = 0;
1888         sc->arge_cdata.arge_tx_cnt = 0;
1889
1890         rd = &sc->arge_rdata;
1891         bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
1892         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1893                 if (i == ARGE_TX_RING_COUNT - 1)
1894                         addr = ARGE_TX_RING_ADDR(sc, 0);
1895                 else
1896                         addr = ARGE_TX_RING_ADDR(sc, i + 1);
1897                 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
1898                 rd->arge_tx_ring[i].next_desc = addr;
1899                 txd = &sc->arge_cdata.arge_txdesc[i];
1900                 txd->tx_m = NULL;
1901         }
1902
1903         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1904             sc->arge_cdata.arge_tx_ring_map,
1905             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1906
1907         return (0);
1908 }
1909
1910 /*
1911  * Free the Tx ring, unload any pending dma transaction and free the mbuf.
1912  */
1913 static void
1914 arge_tx_ring_free(struct arge_softc *sc)
1915 {
1916         struct arge_txdesc      *txd;
1917         int                     i;
1918
1919         /* Free the Tx buffers. */
1920         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1921                 txd = &sc->arge_cdata.arge_txdesc[i];
1922                 if (txd->tx_dmamap) {
1923                         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag,
1924                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1925                         bus_dmamap_unload(sc->arge_cdata.arge_tx_tag,
1926                             txd->tx_dmamap);
1927                 }
1928                 if (txd->tx_m)
1929                         m_freem(txd->tx_m);
1930                 txd->tx_m = NULL;
1931         }
1932 }
1933
1934 /*
1935  * Initialize the RX descriptors and allocate mbufs for them. Note that
1936  * we arrange the descriptors in a closed ring, so that the last descriptor
1937  * points back to the first.
1938  */
1939 static int
1940 arge_rx_ring_init(struct arge_softc *sc)
1941 {
1942         struct arge_ring_data   *rd;
1943         struct arge_rxdesc      *rxd;
1944         bus_addr_t              addr;
1945         int                     i;
1946
1947         sc->arge_cdata.arge_rx_cons = 0;
1948
1949         rd = &sc->arge_rdata;
1950         bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
1951         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1952                 rxd = &sc->arge_cdata.arge_rxdesc[i];
1953                 if (rxd->rx_m != NULL) {
1954                         device_printf(sc->arge_dev,
1955                             "%s: ring[%d] rx_m wasn't free?\n",
1956                             __func__,
1957                             i);
1958                 }
1959                 rxd->rx_m = NULL;
1960                 rxd->desc = &rd->arge_rx_ring[i];
1961                 if (i == ARGE_RX_RING_COUNT - 1)
1962                         addr = ARGE_RX_RING_ADDR(sc, 0);
1963                 else
1964                         addr = ARGE_RX_RING_ADDR(sc, i + 1);
1965                 rd->arge_rx_ring[i].next_desc = addr;
1966                 if (arge_newbuf(sc, i) != 0) {
1967                         return (ENOBUFS);
1968                 }
1969         }
1970
1971         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1972             sc->arge_cdata.arge_rx_ring_map,
1973             BUS_DMASYNC_PREWRITE);
1974
1975         return (0);
1976 }
1977
1978 /*
1979  * Free all the buffers in the RX ring.
1980  *
1981  * TODO: ensure that DMA is disabled and no pending DMA
1982  * is lurking in the FIFO.
1983  */
1984 static void
1985 arge_rx_ring_free(struct arge_softc *sc)
1986 {
1987         int i;
1988         struct arge_rxdesc      *rxd;
1989
1990         ARGE_LOCK_ASSERT(sc);
1991
1992         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1993                 rxd = &sc->arge_cdata.arge_rxdesc[i];
1994                 /* Unmap the mbuf */
1995                 if (rxd->rx_m != NULL) {
1996                         bus_dmamap_unload(sc->arge_cdata.arge_rx_tag,
1997                             rxd->rx_dmamap);
1998                         m_free(rxd->rx_m);
1999                         rxd->rx_m = NULL;
2000                 }
2001         }
2002 }
2003
2004 /*
2005  * Initialize an RX descriptor and attach an MBUF cluster.
2006  */
2007 static int
2008 arge_newbuf(struct arge_softc *sc, int idx)
2009 {
2010         struct arge_desc                *desc;
2011         struct arge_rxdesc      *rxd;
2012         struct mbuf             *m;
2013         bus_dma_segment_t       segs[1];
2014         bus_dmamap_t            map;
2015         int                     nsegs;
2016
2017         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2018         if (m == NULL)
2019                 return (ENOBUFS);
2020         m->m_len = m->m_pkthdr.len = MCLBYTES;
2021         m_adj(m, sizeof(uint64_t));
2022
2023         if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2024             sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2025                 m_freem(m);
2026                 return (ENOBUFS);
2027         }
2028         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2029
2030         rxd = &sc->arge_cdata.arge_rxdesc[idx];
2031         if (rxd->rx_m != NULL) {
2032                 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2033         }
2034         map = rxd->rx_dmamap;
2035         rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2036         sc->arge_cdata.arge_rx_sparemap = map;
2037         rxd->rx_m = m;
2038         desc = rxd->desc;
2039         if (segs[0].ds_addr & 3)
2040                 panic("RX packet address unaligned");
2041         desc->packet_addr = segs[0].ds_addr;
2042         desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2043
2044         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2045             sc->arge_cdata.arge_rx_ring_map,
2046             BUS_DMASYNC_PREWRITE);
2047
2048         return (0);
2049 }
2050
2051 static __inline void
2052 arge_fixup_rx(struct mbuf *m)
2053 {
2054         int             i;
2055         uint16_t        *src, *dst;
2056
2057         src = mtod(m, uint16_t *);
2058         dst = src - 1;
2059
2060         for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
2061                 *dst++ = *src++;
2062         }
2063
2064         if (m->m_len % sizeof(uint16_t))
2065                 *(uint8_t *)dst = *(uint8_t *)src;
2066
2067         m->m_data -= ETHER_ALIGN;
2068 }
2069
2070 #ifdef DEVICE_POLLING
2071 static int
2072 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2073 {
2074         struct arge_softc *sc = ifp->if_softc;
2075         int rx_npkts = 0;
2076
2077         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2078                 ARGE_LOCK(sc);
2079                 arge_tx_locked(sc);
2080                 rx_npkts = arge_rx_locked(sc);
2081                 ARGE_UNLOCK(sc);
2082         }
2083
2084         return (rx_npkts);
2085 }
2086 #endif /* DEVICE_POLLING */
2087
2088
2089 static void
2090 arge_tx_locked(struct arge_softc *sc)
2091 {
2092         struct arge_txdesc      *txd;
2093         struct arge_desc        *cur_tx;
2094         struct ifnet            *ifp;
2095         uint32_t                ctrl;
2096         int                     cons, prod;
2097
2098         ARGE_LOCK_ASSERT(sc);
2099
2100         cons = sc->arge_cdata.arge_tx_cons;
2101         prod = sc->arge_cdata.arge_tx_prod;
2102
2103         ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons,
2104             prod);
2105
2106         if (cons == prod)
2107                 return;
2108
2109         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2110             sc->arge_cdata.arge_tx_ring_map,
2111             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2112
2113         ifp = sc->arge_ifp;
2114         /*
2115          * Go through our tx list and free mbufs for those
2116          * frames that have been transmitted.
2117          */
2118         for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
2119                 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
2120                 ctrl = cur_tx->packet_ctrl;
2121                 /* Check if descriptor has "finished" flag */
2122                 if ((ctrl & ARGE_DESC_EMPTY) == 0)
2123                         break;
2124
2125                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
2126
2127                 sc->arge_cdata.arge_tx_cnt--;
2128                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2129
2130                 txd = &sc->arge_cdata.arge_txdesc[cons];
2131
2132                 ifp->if_opackets++;
2133
2134                 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
2135                     BUS_DMASYNC_POSTWRITE);
2136                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
2137
2138                 /* Free only if it's first descriptor in list */
2139                 if (txd->tx_m)
2140                         m_freem(txd->tx_m);
2141                 txd->tx_m = NULL;
2142
2143                 /* reset descriptor */
2144                 cur_tx->packet_addr = 0;
2145         }
2146
2147         sc->arge_cdata.arge_tx_cons = cons;
2148
2149         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
2150             sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
2151 }
2152
2153
2154 static int
2155 arge_rx_locked(struct arge_softc *sc)
2156 {
2157         struct arge_rxdesc      *rxd;
2158         struct ifnet            *ifp = sc->arge_ifp;
2159         int                     cons, prog, packet_len, i;
2160         struct arge_desc        *cur_rx;
2161         struct mbuf             *m;
2162         int                     rx_npkts = 0;
2163
2164         ARGE_LOCK_ASSERT(sc);
2165
2166         cons = sc->arge_cdata.arge_rx_cons;
2167
2168         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2169             sc->arge_cdata.arge_rx_ring_map,
2170             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2171
2172         for (prog = 0; prog < ARGE_RX_RING_COUNT;
2173             ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
2174                 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
2175                 rxd = &sc->arge_cdata.arge_rxdesc[cons];
2176                 m = rxd->rx_m;
2177
2178                 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
2179                        break;
2180
2181                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
2182
2183                 prog++;
2184
2185                 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
2186                 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
2187                     BUS_DMASYNC_POSTREAD);
2188                 m = rxd->rx_m;
2189
2190                 arge_fixup_rx(m);
2191                 m->m_pkthdr.rcvif = ifp;
2192                 /* Skip 4 bytes of CRC */
2193                 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
2194                 ifp->if_ipackets++;
2195                 rx_npkts++;
2196
2197                 ARGE_UNLOCK(sc);
2198                 (*ifp->if_input)(ifp, m);
2199                 ARGE_LOCK(sc);
2200                 cur_rx->packet_addr = 0;
2201         }
2202
2203         if (prog > 0) {
2204
2205                 i = sc->arge_cdata.arge_rx_cons;
2206                 for (; prog > 0 ; prog--) {
2207                         if (arge_newbuf(sc, i) != 0) {
2208                                 device_printf(sc->arge_dev,
2209                                     "Failed to allocate buffer\n");
2210                                 break;
2211                         }
2212                         ARGE_INC(i, ARGE_RX_RING_COUNT);
2213                 }
2214
2215                 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2216                     sc->arge_cdata.arge_rx_ring_map,
2217                     BUS_DMASYNC_PREWRITE);
2218
2219                 sc->arge_cdata.arge_rx_cons = cons;
2220         }
2221
2222         return (rx_npkts);
2223 }
2224
2225 static int
2226 arge_intr_filter(void *arg)
2227 {
2228         struct arge_softc       *sc = arg;
2229         uint32_t                status, ints;
2230
2231         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2232         ints = ARGE_READ(sc, AR71XX_DMA_INTR);
2233
2234         ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
2235             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2236             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2237         ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2238             "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2239             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2240
2241         if (status & DMA_INTR_ALL) {
2242                 sc->arge_intr_status |= status;
2243                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2244                 return (FILTER_SCHEDULE_THREAD);
2245         }
2246
2247         sc->arge_intr_status = 0;
2248         return (FILTER_STRAY);
2249 }
2250
2251 static void
2252 arge_intr(void *arg)
2253 {
2254         struct arge_softc       *sc = arg;
2255         uint32_t                status;
2256         struct ifnet            *ifp = sc->arge_ifp;
2257
2258         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
2259         status |= sc->arge_intr_status;
2260
2261         ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2262             "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2263             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2264
2265         /*
2266          * Is it our interrupt at all?
2267          */
2268         if (status == 0)
2269                 return;
2270
2271         if (status & DMA_INTR_RX_BUS_ERROR) {
2272                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2273                 device_printf(sc->arge_dev, "RX bus error");
2274                 return;
2275         }
2276
2277         if (status & DMA_INTR_TX_BUS_ERROR) {
2278                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
2279                 device_printf(sc->arge_dev, "TX bus error");
2280                 return;
2281         }
2282
2283         ARGE_LOCK(sc);
2284
2285         if (status & DMA_INTR_RX_PKT_RCVD)
2286                 arge_rx_locked(sc);
2287
2288         /*
2289          * RX overrun disables the receiver.
2290          * Clear indication and re-enable rx.
2291          */
2292         if ( status & DMA_INTR_RX_OVERFLOW) {
2293                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
2294                 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
2295                 sc->stats.rx_overflow++;
2296         }
2297
2298         if (status & DMA_INTR_TX_PKT_SENT)
2299                 arge_tx_locked(sc);
2300         /*
2301          * Underrun turns off TX. Clear underrun indication.
2302          * If there's anything left in the ring, reactivate the tx.
2303          */
2304         if (status & DMA_INTR_TX_UNDERRUN) {
2305                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
2306                 sc->stats.tx_underflow++;
2307                 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n",
2308                     __func__, sc->arge_cdata.arge_tx_cnt);
2309                 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
2310                         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
2311                             DMA_TX_CONTROL_EN);
2312                 }
2313         }
2314
2315         /*
2316          * If we've finished TXing and there's space for more packets
2317          * to be queued for TX, do so. Otherwise we may end up in a
2318          * situation where the interface send queue was filled
2319          * whilst the hardware queue was full, then the hardware
2320          * queue was drained by the interface send queue wasn't,
2321          * and thus if_start() is never called to kick-start
2322          * the send process (and all subsequent packets are simply
2323          * discarded.
2324          *
2325          * XXX TODO: make sure that the hardware deals nicely
2326          * with the possibility of the queue being enabled above
2327          * after a TX underrun, then having the hardware queue added
2328          * to below.
2329          */
2330         if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
2331             (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2332                 if (!IFQ_IS_EMPTY(&ifp->if_snd))
2333                         arge_start_locked(ifp);
2334         }
2335
2336         /*
2337          * We handled all bits, clear status
2338          */
2339         sc->arge_intr_status = 0;
2340         ARGE_UNLOCK(sc);
2341         /*
2342          * re-enable all interrupts
2343          */
2344         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
2345 }
2346
2347
2348 static void
2349 arge_tick(void *xsc)
2350 {
2351         struct arge_softc       *sc = xsc;
2352         struct mii_data         *mii;
2353
2354         ARGE_LOCK_ASSERT(sc);
2355
2356         if (sc->arge_miibus) {
2357                 mii = device_get_softc(sc->arge_miibus);
2358                 mii_tick(mii);
2359                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
2360         }
2361 }
2362
2363 int
2364 arge_multiphy_mediachange(struct ifnet *ifp)
2365 {
2366         struct arge_softc *sc = ifp->if_softc;
2367         struct ifmedia *ifm = &sc->arge_ifmedia;
2368         struct ifmedia_entry *ife = ifm->ifm_cur;
2369
2370         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2371                 return (EINVAL);
2372
2373         if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
2374                 device_printf(sc->arge_dev,
2375                     "AUTO is not supported for multiphy MAC");
2376                 return (EINVAL);
2377         }
2378
2379         /*
2380          * Ignore everything
2381          */
2382         return (0);
2383 }
2384
2385 void
2386 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2387 {
2388         struct arge_softc *sc = ifp->if_softc;
2389
2390         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2391         ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
2392             sc->arge_duplex_mode;
2393 }
2394
2395 #if defined(ARGE_MDIO)
2396 static int
2397 argemdio_probe(device_t dev)
2398 {
2399         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller");
2400         return (0);
2401 }
2402
2403 static int
2404 argemdio_attach(device_t dev)
2405 {
2406         struct arge_softc       *sc;
2407         int                     error = 0;
2408
2409         sc = device_get_softc(dev);
2410         sc->arge_dev = dev;
2411         sc->arge_mac_unit = device_get_unit(dev);
2412         sc->arge_rid = 0;
2413         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2414             &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE);
2415         if (sc->arge_res == NULL) {
2416                 device_printf(dev, "couldn't map memory\n");
2417                 error = ENXIO;
2418                 goto fail;
2419         }
2420
2421         /* Reset MAC - required for AR71xx MDIO to successfully occur */
2422         arge_reset_mac(sc);
2423         /* Reset MII bus */
2424         arge_reset_miibus(sc);
2425
2426         bus_generic_probe(dev);
2427         bus_enumerate_hinted_children(dev);
2428         error = bus_generic_attach(dev);
2429 fail:
2430         return (error);
2431 }
2432
2433 static int
2434 argemdio_detach(device_t dev)
2435 {
2436         return (0);
2437 }
2438
2439 #endif