2 * Copyright (c) 2009, Oleksandr Tymoshenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __IF_ARGEVAR_H__
31 #define __IF_ARGEVAR_H__
34 #define ARGE_TX_RING_COUNT 128
35 #define ARGE_RX_RING_COUNT 128
36 #define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
37 #define ARGE_TX_DMA_SIZE ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
38 #define ARGE_MAXFRAGS 8
39 #define ARGE_RING_ALIGN sizeof(struct arge_desc)
40 #define ARGE_RX_ALIGN sizeof(uint32_t)
41 #define ARGE_MAXFRAGS 8
42 #define ARGE_TX_RING_ADDR(sc, i) \
43 ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
44 #define ARGE_RX_RING_ADDR(sc, i) \
45 ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
46 #define ARGE_INC(x,y) (x) = (((x) + 1) % y)
49 #define ARGE_MII_TIMEOUT 1000
51 #define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx)
52 #define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx)
53 #define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
56 * register space access macros
58 #define ARGE_BARRIER_READ(sc) bus_barrier(sc->arge_res, 0, 0, \
59 BUS_SPACE_BARRIER_READ)
60 #define ARGE_BARRIER_WRITE(sc) bus_barrier(sc->arge_res, 0, 0, \
61 BUS_SPACE_BARRIER_WRITE)
62 #define ARGE_BARRIER_RW(sc) bus_barrier(sc->arge_res, 0, 0, \
63 BUS_SPACE_BARRIER_READ | \
64 BUS_SPACE_BARRIER_WRITE)
65 #define ARGE_WRITE(sc, reg, val) do { \
66 bus_write_4(sc->arge_res, (reg), (val)); \
67 ARGE_BARRIER_WRITE((sc)); \
69 #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
71 #define ARGE_SET_BITS(sc, reg, bits) \
72 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
74 #define ARGE_CLEAR_BITS(sc, reg, bits) \
75 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
78 * The linux driver code for the MDIO bus does a read-after-write
79 * which seems to be required on MIPS74k platforms for correct
82 * So, ARGE_WRITE() does the write + barrier, and the following
83 * ARGE_READ() seems to flush the thing all the way through the device
84 * FIFO(s) before we continue issuing MDIO bus updates.
86 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \
88 ARGE_WRITE((_sc), (_reg), (_val)); \
89 ARGE_READ((_sc), (_reg)); \
91 #define ARGE_MDIO_READ(_sc, _reg) \
92 ARGE_READ((_sc), (_reg))
93 #define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc)
94 #define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc)
95 #define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_READ_RW(_sc)
97 #define ARGE_DESC_EMPTY (1U << 31)
98 #define ARGE_DESC_MORE (1 << 24)
99 #define ARGE_DESC_SIZE_MASK ((1 << 12) - 1)
100 #define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK)
102 uint32_t packet_addr;
103 uint32_t packet_ctrl;
110 bus_dmamap_t tx_dmamap;
115 bus_dmamap_t rx_dmamap;
116 struct arge_desc *desc;
119 struct arge_chain_data {
120 bus_dma_tag_t arge_parent_tag;
121 bus_dma_tag_t arge_tx_tag;
122 struct arge_txdesc arge_txdesc[ARGE_TX_RING_COUNT];
123 bus_dma_tag_t arge_rx_tag;
124 struct arge_rxdesc arge_rxdesc[ARGE_RX_RING_COUNT];
125 bus_dma_tag_t arge_tx_ring_tag;
126 bus_dma_tag_t arge_rx_ring_tag;
127 bus_dmamap_t arge_tx_ring_map;
128 bus_dmamap_t arge_rx_ring_map;
129 bus_dmamap_t arge_rx_sparemap;
136 struct arge_ring_data {
137 struct arge_desc *arge_rx_ring;
138 struct arge_desc *arge_tx_ring;
139 bus_addr_t arge_rx_ring_paddr;
140 bus_addr_t arge_tx_ring_paddr;
144 * Allow PLL values to be overridden.
146 struct arge_pll_data {
153 struct ifnet *arge_ifp; /* interface info */
155 struct ifmedia arge_ifmedia;
157 * Media & duples settings for multiPHY MAC
159 uint32_t arge_media_type;
160 uint32_t arge_duplex_mode;
161 uint32_t arge_phymask;
162 uint8_t arge_eaddr[ETHER_ADDR_LEN];
163 struct resource *arge_res;
165 struct resource *arge_irq;
167 device_t arge_miibus;
168 device_t arge_miiproxy;
169 ar71xx_mii_mode arge_miicfg;
170 struct arge_pll_data arge_pllcfg;
171 bus_dma_tag_t arge_parent_tag;
172 bus_dma_tag_t arge_tag;
174 struct callout arge_stat_callout;
175 struct task arge_link_task;
176 struct arge_chain_data arge_cdata;
177 struct arge_ring_data arge_rdata;
178 int arge_link_status;
180 uint32_t arge_intr_status;
184 uint32_t arge_mdiofreq;
186 uint32_t tx_pkts_unaligned;
187 uint32_t tx_pkts_aligned;
188 uint32_t rx_overflow;
189 uint32_t tx_underflow;
193 #endif /* __IF_ARGEVAR_H__ */