sys/mips/atheros/qca953xreg.h

   1 /*-
   2  * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28 #ifndef __QCA953XREG_H__
  29 #define __QCA953XREG_H__
  30
  31 #define BIT(x)                          (1 << (x))
  32
  33 /* Revision ID information */
  34 #define REV_ID_MAJOR_QCA9533            0x0140
  35 #define REV_ID_MAJOR_QCA9533_V2         0x0160
  36 #define QCA953X_REV_ID_REVISION_MASK    0xf
  37
  38 /* Big enough to cover APB and SPI, and most peripherals */
  39 /*
  40  * it needs to cover SPI because right now the if_ath_ahb
  41  * code uses rman to map in the SPI address into memory
  42  * to read data instead of us squirreling it away at early
  43  * boot-time and using the firmware interface.
  44  *
  45  * if_ath_ahb.c should use the same firmware interface
  46  * that if_ath_pci.c uses.
  47  */
  48 #define QCA953X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
  49 #define QCA953X_GMAC_SIZE      0x14
  50 #define QCA953X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
  51 #define QCA953X_WMAC_SIZE      0x20000
  52 #define QCA953X_EHCI_BASE      0x1b000000
  53 #define QCA953X_EHCI_SIZE      0x200
  54 #define QCA953X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
  55 #define QCA953X_SRIF_SIZE      0x1000
  56
  57 #define QCA953X_PCI_CFG_BASE0  0x14000000
  58 #define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
  59 #define QCA953X_PCI_CRP_BASE0  (AR71XX_APB_BASE + 0x000c0000)
  60 #define QCA953X_PCI_MEM_BASE0  0x10000000
  61 #define QCA953X_PCI_MEM_SIZE   0x02000000
  62
  63 /* PLL Block */
  64 #define QCA953X_PLL_CPU_CONFIG_REG              (AR71XX_PLL_CPU_BASE + 0x00)
  65 #define QCA953X_PLL_DDR_CONFIG_REG              (AR71XX_PLL_CPU_BASE + 0x04)
  66 #define QCA953X_PLL_CLK_CTRL_REG                (AR71XX_PLL_CPU_BASE + 0x08)
  67
  68 #define QCA953X_PLL_ETH_XMII_CONTROL_REG        (AR71XX_PLL_CPU_BASE + 0x2c)
  69 #define QCA953X_PLL_ETH_SGMII_CONTROL_REG       (AR71XX_PLL_CPU_BASE + 0x48)
  70
  71 #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
  72 #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
  73 #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT       6
  74 #define QCA953X_PLL_CPU_CONFIG_NINT_MASK        0x3f
  75 #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT     12
  76 #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK      0x1f
  77 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT     19
  78 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK      0x3
  79
  80 #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT      0
  81 #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK       0x3ff
  82 #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT       10
  83 #define QCA953X_PLL_DDR_CONFIG_NINT_MASK        0x3f
  84 #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT     16
  85 #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK      0x1f
  86 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT     23
  87 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK      0x7
  88
  89 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS     BIT(2)
  90 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS     BIT(3)
  91 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS     BIT(4)
  92 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
  93 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK  0x1f
  94 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
  95 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK  0x1f
  96 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
  97 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK  0x1f
  98 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
  99 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
 100 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
 101
 102 #define QCA953X_PLL_VAL_1000                    0x16000000
 103 #define QCA953X_PLL_VAL_100                     0x00000101
 104 #define QCA953X_PLL_VAL_10                      0x00001616
 105
 106 /* Reset block */
 107
 108 #define QCA953X_RESET_REG_RESET_MODULE          (AR71XX_RST_BLOCK_BASE + 0x1c)
 109 #define QCA953X_RESET_USB_EXT_PWR               BIT(29)
 110 #define QCA953X_RESET_EXTERNAL                  BIT(28)
 111 #define QCA953X_RESET_RTC                       BIT(27)
 112 #define QCA953X_RESET_FULL_CHIP                 BIT(24)
 113 #define QCA953X_RESET_GE1_MDIO                  BIT(23)
 114 #define QCA953X_RESET_GE0_MDIO                  BIT(22)
 115 #define QCA953X_RESET_CPU_NMI                   BIT(21)
 116 #define QCA953X_RESET_CPU_COLD                  BIT(20)
 117 #define QCA953X_RESET_DDR                       BIT(16)
 118 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT       BIT(15)
 119 #define QCA953X_RESET_GE1_MAC                   BIT(13)
 120 #define QCA953X_RESET_ETH_SWITCH_ANALOG         BIT(12)
 121 #define QCA953X_RESET_USB_PHY_ANALOG            BIT(11)
 122 #define QCA953X_RESET_GE0_MAC                   BIT(9)
 123 #define QCA953X_RESET_ETH_SWITCH                BIT(8)
 124 #define QCA953X_RESET_PCIE_PHY                  BIT(7)
 125 #define QCA953X_RESET_PCIE                      BIT(6)
 126 #define QCA953X_RESET_USB_HOST                  BIT(5)
 127 #define QCA953X_RESET_USB_PHY                   BIT(4)
 128 #define QCA953X_RESET_USBSUS_OVERRIDE           BIT(3)
 129
 130 #define QCA953X_RESET_REG_BOOTSTRAP             (AR71XX_RST_BLOCK_BASE + 0xb0)
 131 #define QCA953X_BOOTSTRAP_SW_OPTION2            BIT(12)
 132 #define QCA953X_BOOTSTRAP_SW_OPTION1            BIT(11)
 133 #define QCA953X_BOOTSTRAP_EJTAG_MODE            BIT(5)
 134 #define QCA953X_BOOTSTRAP_REF_CLK_40            BIT(4)
 135 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED        BIT(1)
 136 #define QCA953X_BOOTSTRAP_DDR1                  BIT(0)
 137
 138 #define QCA953X_RESET_REG_EXT_INT_STATUS        (AR71XX_RST_BLOCK_BASE + 0xac)
 139
 140 #define QCA953X_DDR_REG_FLUSH_GE0               (AR71XX_APB_BASE + 0x9c)
 141 #define QCA953X_DDR_REG_FLUSH_GE1               (AR71XX_APB_BASE + 0xa0)
 142 #define QCA953X_DDR_REG_FLUSH_USB               (AR71XX_APB_BASE + 0xa4)
 143 #define QCA953X_DDR_REG_FLUSH_PCIE              (AR71XX_APB_BASE + 0xa8)
 144 #define QCA953X_DDR_REG_FLUSH_WMAC              (AR71XX_APB_BASE + 0xac)
 145
 146 /* GPIO block */
 147 #define QCA953X_GPIO_REG_OUT_FUNC0      0x2c
 148 #define QCA953X_GPIO_REG_OUT_FUNC1      0x30
 149 #define QCA953X_GPIO_REG_OUT_FUNC2      0x34
 150 #define QCA953X_GPIO_REG_OUT_FUNC3      0x38
 151 #define QCA953X_GPIO_REG_OUT_FUNC4      0x3c
 152 #define QCA953X_GPIO_REG_IN_ENABLE0     0x44
 153 #define QCA953X_GPIO_REG_FUNC           0x6c
 154
 155 #define QCA953X_GPIO_OUT_MUX_SPI_CS1    10
 156 #define QCA953X_GPIO_OUT_MUX_SPI_CS2    11
 157 #define QCA953X_GPIO_OUT_MUX_SPI_CS0    9
 158 #define QCA953X_GPIO_OUT_MUX_SPI_CLK    8
 159 #define QCA953X_GPIO_OUT_MUX_SPI_MOSI   12
 160 #define QCA953X_GPIO_OUT_MUX_LED_LINK1  41
 161 #define QCA953X_GPIO_OUT_MUX_LED_LINK2  42
 162 #define QCA953X_GPIO_OUT_MUX_LED_LINK3  43
 163 #define QCA953X_GPIO_OUT_MUX_LED_LINK4  44
 164 #define QCA953X_GPIO_OUT_MUX_LED_LINK5  45
 165
 166 #define QCA953X_GPIO_COUNT              18
 167
 168 /* GMAC block */
 169 #define QCA953X_GMAC_REG_ETH_CFG        (QCA953X_GMAC_BASE + 0x00)
 170
 171 #define QCA953X_ETH_CFG_SW_ONLY_MODE            BIT(6)
 172 #define QCA953X_ETH_CFG_SW_PHY_SWAP             BIT(7)
 173 #define QCA953X_ETH_CFG_SW_APB_ACCESS           BIT(9)
 174 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
 175
 176 /* SRIF block */
 177 #define QCA953X_SRIF_CPU_DPLL1_REG              0x1c0
 178 #define QCA953X_SRIF_CPU_DPLL2_REG              0x1c4
 179 #define QCA953X_SRIF_CPU_DPLL3_REG              0x1c8
 180
 181 #define QCA953X_SRIF_DDR_DPLL1_REG              0x240
 182 #define QCA953X_SRIF_DDR_DPLL2_REG              0x244
 183 #define QCA953X_SRIF_DDR_DPLL3_REG              0x248
 184
 185 #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT         27
 186 #define QCA953X_SRIF_DPLL1_REFDIV_MASK          0x1f
 187 #define QCA953X_SRIF_DPLL1_NINT_SHIFT           18
 188 #define QCA953X_SRIF_DPLL1_NINT_MASK            0x1ff
 189 #define QCA953X_SRIF_DPLL1_NFRAC_MASK           0x0003ffff
 190
 191 #define QCA953X_SRIF_DPLL2_LOCAL_PLL            BIT(30)
 192 #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT         13
 193 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK          0x7
 194
 195 #endif  /* __QCA953XREG_H__ */