2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <machine/bus.h>
38 #include <dev/uart/uart.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_bus.h>
42 #include <mips/atheros/ar933x_uart.h>
47 * Default system clock is 25MHz; see ar933x_chip.c for how
48 * the startup process determines whether it's 25MHz or 40MHz.
50 #define DEFAULT_RCLK (25 * 1000 * 1000)
52 #define ar933x_getreg(bas, reg) \
53 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
54 #define ar933x_setreg(bas, reg, value) \
55 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
58 ar933x_drain(struct uart_bas *bas, int what)
62 if (what & UART_DRAIN_TRANSMITTER) {
65 /* Loop over until the TX FIFO shows entirely clear */
67 if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
68 & AR933X_UART_CS_TX_BUSY) == 0)
76 if (what & UART_DRAIN_RECEIVER) {
79 /* XXX duplicated from ar933x_getc() */
80 /* XXX TODO: refactor! */
82 /* If there's nothing to read, stop! */
83 if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
84 AR933X_UART_DATA_RX_CSR) == 0) {
88 /* Read the top of the RX FIFO */
89 (void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
91 /* Remove that entry from said RX FIFO */
92 ar933x_setreg(bas, AR933X_UART_DATA_REG,
93 AR933X_UART_DATA_RX_CSR);
106 * Calculate the baud from the given chip configuration parameters.
109 ar933x_uart_get_baud(unsigned int clk, unsigned int scale,
115 div = (2 << 16) * (scale + 1);
125 * Calculate the scale/step with the lowest possible deviation from
126 * the target baudrate.
129 ar933x_uart_get_scale_step(struct uart_bas *bas, unsigned int baud,
130 unsigned int *scale, unsigned int *step)
141 for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
145 tstep = baud * (tscale + 1);
149 if (tstep > AR933X_UART_MAX_STEP)
152 diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
153 if (diff < min_diff) {
162 ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
165 /* UART always 8 bits */
167 /* UART always 1 stop bit */
169 /* UART parity is controllable by bits 0:1, ignore for now */
171 /* Set baudrate if required. */
173 uint32_t clock_scale, clock_step;
175 /* Find the best fit for the given baud rate */
176 ar933x_uart_get_scale_step(bas, baudrate, &clock_scale,
180 * Program the clock register in its entirety - no need
181 * for Read-Modify-Write.
183 ar933x_setreg(bas, AR933X_UART_CLOCK_REG,
184 ((clock_scale & AR933X_UART_CLOCK_SCALE_M)
185 << AR933X_UART_CLOCK_SCALE_S) |
186 (clock_step & AR933X_UART_CLOCK_STEP_M));
194 * Low-level UART interface.
196 static int ar933x_probe(struct uart_bas *bas);
197 static void ar933x_init(struct uart_bas *bas, int, int, int, int);
198 static void ar933x_term(struct uart_bas *bas);
199 static void ar933x_putc(struct uart_bas *bas, int);
200 static int ar933x_rxready(struct uart_bas *bas);
201 static int ar933x_getc(struct uart_bas *bas, struct mtx *);
203 static struct uart_ops uart_ar933x_ops = {
204 .probe = ar933x_probe,
208 .rxready = ar933x_rxready,
213 ar933x_probe(struct uart_bas *bas)
216 /* We always know this will be here */
221 ar933x_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
226 /* Setup default parameters */
227 ar933x_param(bas, baudrate, databits, stopbits, parity);
229 /* XXX Force enable UART in case it was disabled */
231 /* Disable all interrupts */
232 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
234 /* Disable the host interrupt */
235 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
236 reg &= ~AR933X_UART_CS_HOST_INT_EN;
237 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
241 /* XXX Set RTS/DTR? */
245 * Detach from console.
248 ar933x_term(struct uart_bas *bas)
255 ar933x_putc(struct uart_bas *bas, int c)
261 /* Wait for space in the TX FIFO */
262 while ( ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
263 AR933X_UART_DATA_TX_CSR) == 0) && --limit)
266 /* Write the actual byte */
267 ar933x_setreg(bas, AR933X_UART_DATA_REG,
268 (c & 0xff) | AR933X_UART_DATA_TX_CSR);
272 ar933x_rxready(struct uart_bas *bas)
275 /* Wait for a character to come ready */
276 return (!!(ar933x_getreg(bas, AR933X_UART_DATA_REG)
277 & AR933X_UART_DATA_RX_CSR));
281 ar933x_getc(struct uart_bas *bas, struct mtx *hwmtx)
287 /* Wait for a character to come ready */
288 while ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
289 AR933X_UART_DATA_RX_CSR) == 0) {
295 /* Read the top of the RX FIFO */
296 c = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
298 /* Remove that entry from said RX FIFO */
299 ar933x_setreg(bas, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
307 * High-level UART interface.
309 struct ar933x_softc {
310 struct uart_softc base;
315 static int ar933x_bus_attach(struct uart_softc *);
316 static int ar933x_bus_detach(struct uart_softc *);
317 static int ar933x_bus_flush(struct uart_softc *, int);
318 static int ar933x_bus_getsig(struct uart_softc *);
319 static int ar933x_bus_ioctl(struct uart_softc *, int, intptr_t);
320 static int ar933x_bus_ipend(struct uart_softc *);
321 static int ar933x_bus_param(struct uart_softc *, int, int, int, int);
322 static int ar933x_bus_probe(struct uart_softc *);
323 static int ar933x_bus_receive(struct uart_softc *);
324 static int ar933x_bus_setsig(struct uart_softc *, int);
325 static int ar933x_bus_transmit(struct uart_softc *);
326 static void ar933x_bus_grab(struct uart_softc *);
327 static void ar933x_bus_ungrab(struct uart_softc *);
329 static kobj_method_t ar933x_methods[] = {
330 KOBJMETHOD(uart_attach, ar933x_bus_attach),
331 KOBJMETHOD(uart_detach, ar933x_bus_detach),
332 KOBJMETHOD(uart_flush, ar933x_bus_flush),
333 KOBJMETHOD(uart_getsig, ar933x_bus_getsig),
334 KOBJMETHOD(uart_ioctl, ar933x_bus_ioctl),
335 KOBJMETHOD(uart_ipend, ar933x_bus_ipend),
336 KOBJMETHOD(uart_param, ar933x_bus_param),
337 KOBJMETHOD(uart_probe, ar933x_bus_probe),
338 KOBJMETHOD(uart_receive, ar933x_bus_receive),
339 KOBJMETHOD(uart_setsig, ar933x_bus_setsig),
340 KOBJMETHOD(uart_transmit, ar933x_bus_transmit),
341 KOBJMETHOD(uart_grab, ar933x_bus_grab),
342 KOBJMETHOD(uart_ungrab, ar933x_bus_ungrab),
346 struct uart_class uart_ar933x_class = {
349 sizeof(struct ar933x_softc),
350 .uc_ops = &uart_ar933x_ops,
352 .uc_rclk = DEFAULT_RCLK,
356 #define SIGCHG(c, i, s, d) \
358 i |= (i & s) ? s : s | d; \
360 i = (i & s) ? (i & ~s) | d : i; \
364 ar933x_bus_attach(struct uart_softc *sc)
366 struct ar933x_softc *u = (struct ar933x_softc *)sc;
367 struct uart_bas *bas = &sc->sc_bas;
370 /* XXX TODO: flush transmitter */
373 * Setup initial interrupt notifications.
375 * XXX for now, just RX FIFO valid.
376 * Later on (when they're handled), also handle
377 * RX errors/overflow.
379 u->u_ier = AR933X_UART_INT_RX_VALID;
381 /* Enable RX interrupts to kick-start things */
382 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
384 /* Enable the host interrupt now */
385 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
386 reg |= AR933X_UART_CS_HOST_INT_EN;
387 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
393 ar933x_bus_detach(struct uart_softc *sc)
395 struct uart_bas *bas = &sc->sc_bas;
398 /* Disable all interrupts */
399 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
401 /* Disable the host interrupt */
402 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
403 reg &= ~AR933X_UART_CS_HOST_INT_EN;
404 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
411 ar933x_bus_flush(struct uart_softc *sc, int what)
413 struct uart_bas *bas;
416 uart_lock(sc->sc_hwmtx);
417 ar933x_drain(bas, what);
418 uart_unlock(sc->sc_hwmtx);
424 ar933x_bus_getsig(struct uart_softc *sc)
426 uint32_t sig = sc->sc_hwsig;
429 * For now, let's just return that DSR/DCD/CTS is asserted.
431 SIGCHG(1, sig, SER_DSR, SER_DDSR);
432 SIGCHG(1, sig, SER_CTS, SER_DCTS);
433 SIGCHG(1, sig, SER_DCD, SER_DDCD);
434 SIGCHG(1, sig, SER_RI, SER_DRI);
436 sc->sc_hwsig = sig & ~SER_MASK_DELTA;
442 * XXX TODO: actually implement the rest of this!
445 ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
451 case UART_IOCTL_BREAK:
452 case UART_IOCTL_IFLOW:
453 case UART_IOCTL_OFLOW:
455 case UART_IOCTL_BAUD:
456 *(int*)data = 115200;
469 * Bus interrupt handler.
471 * For now, system interrupts are disabled.
472 * So this is just called from a callout in uart_core.c
473 * to poll various state.
476 ar933x_bus_ipend(struct uart_softc *sc)
478 struct ar933x_softc *u = (struct ar933x_softc *)sc;
479 struct uart_bas *bas = &sc->sc_bas;
483 uart_lock(sc->sc_hwmtx);
486 * Fetch/ACK the ISR status.
488 isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
489 ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
493 * RX ready - notify upper layer.
495 if (isr & AR933X_UART_INT_RX_VALID) {
496 ipend |= SER_INT_RXREADY;
500 * If we get this interrupt, we should disable
501 * it from the interrupt mask and inform the uart
502 * driver appropriately.
504 * We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
505 * all the time or IO stops working. So we will always
506 * clear this interrupt if we get it, then we only signal
507 * the upper layer if we were doing active TX in the
510 * Also, the name is misleading. This actually means
511 * "the FIFO is almost empty." So if we just write some
512 * more data to the FIFO without checking whether it can
513 * take said data, we'll overflow the thing.
515 * Unfortunately the FreeBSD uart device has no concept of
516 * partial UART writes - it expects that the whole buffer
517 * is written to the hardware. Thus for now, ar933x_bus_transmit()
518 * will wait for the FIFO to finish draining before it pushes
519 * more frames into it.
521 if (isr & AR933X_UART_INT_TX_EMPTY) {
523 * Update u_ier to disable TX notifications; update hardware
525 u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
526 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
531 * Only signal TX idle if we're not busy transmitting.
533 * XXX I never get _out_ of txbusy? Debug that!
536 if (isr & AR933X_UART_INT_TX_EMPTY) {
537 ipend |= SER_INT_TXIDLE;
539 ipend |= SER_INT_SIGCHG;
543 uart_unlock(sc->sc_hwmtx);
548 ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
549 int stopbits, int parity)
551 struct uart_bas *bas;
555 uart_lock(sc->sc_hwmtx);
556 error = ar933x_param(bas, baudrate, databits, stopbits, parity);
557 uart_unlock(sc->sc_hwmtx);
562 ar933x_bus_probe(struct uart_softc *sc)
564 struct uart_bas *bas;
569 error = ar933x_probe(bas);
574 ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
576 /* XXX TODO: actually find out what the FIFO depth is! */
577 sc->sc_rxfifosz = 16;
578 sc->sc_txfifosz = 16;
584 ar933x_bus_receive(struct uart_softc *sc)
586 struct uart_bas *bas = &sc->sc_bas;
589 uart_lock(sc->sc_hwmtx);
591 /* Loop over until we are full, or no data is available */
592 while (ar933x_rxready(bas)) {
593 if (uart_rx_full(sc)) {
594 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
598 /* Read the top of the RX FIFO */
599 xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
601 /* Remove that entry from said RX FIFO */
602 ar933x_setreg(bas, AR933X_UART_DATA_REG,
603 AR933X_UART_DATA_RX_CSR);
606 /* XXX frame, parity error */
611 * XXX TODO: Discard everything left in the Rx FIFO?
612 * XXX only if we've hit an overrun condition?
615 uart_unlock(sc->sc_hwmtx);
621 ar933x_bus_setsig(struct uart_softc *sc, int sig)
624 struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
625 struct uart_bas *bas;
632 if (sig & SER_DDTR) {
633 SIGCHG(sig & SER_DTR, new, SER_DTR,
636 if (sig & SER_DRTS) {
637 SIGCHG(sig & SER_RTS, new, SER_RTS,
640 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
641 uart_lock(sc->sc_hwmtx);
642 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
644 ns8250->mcr |= MCR_DTR;
646 ns8250->mcr |= MCR_RTS;
647 uart_setreg(bas, REG_MCR, ns8250->mcr);
649 uart_unlock(sc->sc_hwmtx);
655 * Write the current transmit buffer to the TX FIFO.
657 * Unfortunately the FreeBSD uart device has no concept of
658 * partial UART writes - it expects that the whole buffer
659 * is written to the hardware. Thus for now, this will wait for
660 * the FIFO to finish draining before it pushes more frames into it.
662 * If non-blocking operation is truely needed here, either
663 * the FreeBSD uart device will need to handle partial writes
664 * in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
668 ar933x_bus_transmit(struct uart_softc *sc)
670 struct uart_bas *bas = &sc->sc_bas;
671 struct ar933x_softc *u = (struct ar933x_softc *)sc;
674 uart_lock(sc->sc_hwmtx);
676 /* Wait for the FIFO to be clear - see above */
677 while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
678 AR933X_UART_CS_TX_BUSY)
684 for (i = 0; i < sc->sc_txdatasz; i++) {
685 /* Write the TX data */
686 ar933x_setreg(bas, AR933X_UART_DATA_REG,
687 (sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
692 * Now that we're transmitting, get interrupt notification
693 * when the FIFO is (almost) empty - see above.
695 u->u_ier |= AR933X_UART_INT_TX_EMPTY;
696 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
700 * Inform the upper layer that we are presently transmitting
701 * data to the hardware; this will be cleared when the
702 * TXIDLE interrupt occurs.
705 uart_unlock(sc->sc_hwmtx);
711 ar933x_bus_grab(struct uart_softc *sc)
713 struct uart_bas *bas = &sc->sc_bas;
716 /* Disable the host interrupt now */
717 uart_lock(sc->sc_hwmtx);
718 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
719 reg &= ~AR933X_UART_CS_HOST_INT_EN;
720 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
721 uart_unlock(sc->sc_hwmtx);
725 ar933x_bus_ungrab(struct uart_softc *sc)
727 struct uart_bas *bas = &sc->sc_bas;
730 /* Enable the host interrupt now */
731 uart_lock(sc->sc_hwmtx);
732 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
733 reg |= AR933X_UART_CS_HOST_INT_EN;
734 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
735 uart_unlock(sc->sc_hwmtx);