2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2013 SRI International
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
8 * ("CTSRD"), as part of the DARPA CRASH research programme.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include "opt_platform.h"
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
44 #include <sys/systm.h>
47 #include <machine/bus.h>
48 #include <machine/intr.h>
51 #include <mips/beri/beri_mp.h>
54 #include <dev/fdt/fdt_common.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
61 #define BP_NUM_HARD_IRQS 5
62 #define BP_NUM_IRQS 32
63 /* We use hard irqs 15-31 as soft */
64 #define BP_FIRST_SOFT 16
66 #define BP_CFG_IRQ_S 0
67 #define BP_CFG_IRQ_M (0xf << BP_CFG_IRQ_S)
68 #define BP_CFG_TID_S 8
69 #define BP_CFG_TID_M (0x7FFFFF << BP_CFG_TID_S)
70 #define BP_CFG_ENABLE (1 << 31)
81 struct beri_pic_isrc {
82 struct intr_irqsrc isrc;
84 uint32_t mips_hard_irq;
89 struct beripic_softc *sc;
92 struct beripic_softc {
95 struct beri_pic_isrc irqs[BP_NUM_IRQS];
96 struct resource *res[4 + BP_NUM_HARD_IRQS];
97 void *ih[BP_NUM_HARD_IRQS];
98 struct hirq hirq[BP_NUM_HARD_IRQS];
99 uint8_t mips_hard_irq_idx;
102 static struct resource_spec beri_pic_spec[] = {
103 { SYS_RES_MEMORY, 0, RF_ACTIVE },
104 { SYS_RES_MEMORY, 1, RF_ACTIVE },
105 { SYS_RES_MEMORY, 2, RF_ACTIVE },
106 { SYS_RES_MEMORY, 3, RF_ACTIVE },
107 { SYS_RES_IRQ, 0, RF_ACTIVE },
108 { SYS_RES_IRQ, 1, RF_ACTIVE },
109 { SYS_RES_IRQ, 2, RF_ACTIVE },
110 { SYS_RES_IRQ, 3, RF_ACTIVE },
111 { SYS_RES_IRQ, 4, RF_ACTIVE },
116 beri_pic_intr(void *arg)
118 struct beripic_softc *sc;
119 struct intr_irqsrc *isrc;
128 intr = bus_read_8(sc->res[BP_IP_READ], 0);
129 while ((i = fls(intr)) != 0) {
133 isrc = &sc->irqs[i].isrc;
135 reg = bus_read_8(sc->res[BP_CFG], i * 8);
136 if ((reg & BP_CFG_IRQ_M) != h->irq) {
139 if ((reg & (BP_CFG_ENABLE)) == 0) {
143 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
144 device_printf(sc->dev, "Stray interrupt %u detected\n", i);
147 bus_write_8(sc->res[BP_IP_CLEAR], 0, (1 << i));
150 return (FILTER_HANDLED);
154 beripic_probe(device_t dev)
157 if (!ofw_bus_status_okay(dev))
160 if (!ofw_bus_is_compatible(dev, "sri-cambridge,beri-pic"))
163 device_set_desc(dev, "BERI Programmable Interrupt Controller");
165 return (BUS_PROBE_DEFAULT);
169 beripic_attach(device_t dev)
171 struct beripic_softc *sc;
172 struct beri_pic_isrc *pic_isrc;
174 struct intr_irqsrc *isrc;
180 sc = device_get_softc(dev);
183 if (bus_alloc_resources(dev, beri_pic_spec, sc->res)) {
184 device_printf(dev, "could not allocate resources\n");
188 xref = OF_xref_from_node(ofw_bus_get_node(dev));
189 name = device_get_nameunit(dev);
190 unit = device_get_unit(dev);
191 sc->nirqs = BP_NUM_IRQS;
193 for (i = 0; i < sc->nirqs; i++) {
195 isrc = &sc->irqs[i].isrc;
197 /* Assign mips hard irq number. */
198 pic_isrc = (struct beri_pic_isrc *)isrc;
199 pic_isrc->mips_hard_irq = sc->mips_hard_irq_idx++;
200 /* Last IRQ is used for IPIs. */
201 if (sc->mips_hard_irq_idx >= (BP_NUM_HARD_IRQS - 1)) {
202 sc->mips_hard_irq_idx = 0;
205 err = intr_isrc_register(isrc, sc->dev,
206 0, "pic%d,%d", unit, i);
207 bus_write_8(sc->res[BP_CFG], i * 8, 0);
211 * Now, when everything is initialized, it's right time to
212 * register interrupt controller to interrupt framefork.
214 if (intr_pic_register(dev, xref) == NULL) {
215 device_printf(dev, "could not register PIC\n");
219 /* Last IRQ is used for IPIs. */
220 for (i = 0; i < (BP_NUM_HARD_IRQS - 1); i++) {
223 if (bus_setup_intr(dev, sc->res[4+i], INTR_TYPE_CLK,
224 beri_pic_intr, NULL, &sc->hirq[i], sc->ih[i])) {
225 device_printf(dev, "could not setup irq handler\n");
226 intr_pic_deregister(dev, xref);
235 beri_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
237 struct beri_pic_isrc *pic_isrc;
238 struct beripic_softc *sc;
241 sc = device_get_softc(dev);
242 pic_isrc = (struct beri_pic_isrc *)isrc;
245 reg |= (pic_isrc->mips_hard_irq << BP_CFG_IRQ_S);
246 bus_write_8(sc->res[BP_CFG], pic_isrc->irq * 8, reg);
250 beri_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
252 struct beri_pic_isrc *pic_isrc;
253 struct beripic_softc *sc;
256 sc = device_get_softc(dev);
257 pic_isrc = (struct beri_pic_isrc *)isrc;
259 reg = bus_read_8(sc->res[BP_CFG], pic_isrc->irq * 8);
260 reg &= ~BP_CFG_ENABLE;
261 bus_write_8(sc->res[BP_CFG], pic_isrc->irq * 8, reg);
265 beri_pic_map_intr(device_t dev, struct intr_map_data *data,
266 struct intr_irqsrc **isrcp)
268 struct beripic_softc *sc;
269 struct intr_map_data_fdt *daf;
272 sc = device_get_softc(dev);
273 daf = (struct intr_map_data_fdt *)data;
275 if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
276 daf->ncells != 1 || daf->cells[0] >= sc->nirqs)
281 *isrcp = &sc->irqs[irq].isrc;
287 beri_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
290 beri_pic_enable_intr(dev, isrc);
294 beri_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
297 beri_pic_disable_intr(dev, isrc);
302 beripic_setup_ipi(device_t dev, u_int tid, u_int ipi_irq)
304 struct beripic_softc *sc;
307 sc = device_get_softc(dev);
309 reg = (BP_CFG_ENABLE);
310 reg |= (ipi_irq << BP_CFG_IRQ_S);
311 reg |= (tid << BP_CFG_TID_S);
312 bus_write_8(sc->res[BP_CFG], ((BP_FIRST_SOFT + tid) * 8), reg);
316 beripic_send_ipi(device_t dev, u_int tid)
318 struct beripic_softc *sc;
321 sc = device_get_softc(dev);
323 bit = (BP_FIRST_SOFT + tid);
324 KASSERT(bit < BP_NUM_IRQS, ("tid (%d) to large\n", tid));
326 bus_write_8(sc->res[BP_IP_SET], 0x0, (1 << bit));
330 beripic_clear_ipi(device_t dev, u_int tid)
332 struct beripic_softc *sc;
335 sc = device_get_softc(dev);
337 bit = (BP_FIRST_SOFT + tid);
338 KASSERT(bit < BP_NUM_IRQS, ("tid (%d) to large\n", tid));
340 bus_write_8(sc->res[BP_IP_CLEAR], 0x0, (1 << bit));
344 static device_method_t beripic_fdt_methods[] = {
345 /* Device interface */
346 DEVMETHOD(device_probe, beripic_probe),
347 DEVMETHOD(device_attach, beripic_attach),
349 /* Interrupt controller interface */
350 DEVMETHOD(pic_enable_intr, beri_pic_enable_intr),
351 DEVMETHOD(pic_disable_intr, beri_pic_disable_intr),
352 DEVMETHOD(pic_map_intr, beri_pic_map_intr),
353 DEVMETHOD(pic_post_ithread, beri_pic_post_ithread),
354 DEVMETHOD(pic_pre_ithread, beri_pic_pre_ithread),
359 devclass_t beripic_devclass;
361 static driver_t beripic_driver = {
364 sizeof(struct beripic_softc)
367 EARLY_DRIVER_MODULE(beripic, ofwbus, beripic_driver, beripic_devclass, 0, 0,
368 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);