2 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
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32 #ifndef _MIPS_BROADCOM_BMIPSREG_H_
33 #define _MIPS_BROADCOM_BMIPSREG_H_
36 * Common BMIPS32/BMIPS3300 Registers
38 #define BCM_BMIPS_CORECTL 0x00 /**< core control */
39 #define BCM_BMIPS_CORECTL_FORCE_RST 0x01 /**< force reset */
40 #define BCM_BMIPS_CORECTL_NO_FLSH_EXC 0x02 /**< flash exception disable */
41 #define BCM_BMIPS_INTR_STATUS 0x20 /**< interrupt status */
42 #define BCM_BMIPS_INTR_MASK 0x24 /**< interrupt mask */
43 #define BCM_BMIPS_TIMER_INTMASK 0x01 /**< timer interrupt mask */
44 #define BCM_BMIPS_TIMER_CTRL 0x28 /**< timer interval (?) */
47 * Broadcom BMIPS32 (BHND_COREID_MIPS)
50 #define BCM_BMIPS32_CORECTL BCM_BMIPS_CORECTL
51 #define BCM_BMIPS32_BIST_STATUS 0x04 /**< built-in self-test status */
52 #define BCM_BMIPS32_INTR_STATUS BCM_BMIPS_INTR_STATUS
53 #define BCM_BMIPS32_INTR_MASK BCM_BMIPS_INTR_MASK
54 #define BCM_BMIPS32_TIMER_CTRL BCM_BMIPS_TIMER_CTRL
57 * Broadcom BMIPS3300+ (BHND_COREID_MIPS33)
60 #define BCM_BMIPS33_CORECTL BCM_BMIPS_CORECTL
61 #define BCM_BMIPS33_BIST_CTRL 0x04 /**< build-in self-test control */
62 #define BCM_BMIPS33_BIST_CTRL_DUMP 0x01 /**< BIST dump */
63 #define BCM_BMIPS33_BIST_CTRL_DEBUG 0x02 /**< BIST debug */
64 #define BCM_BMIPS33_BIST_CTRL_HOLD 0x04 /**< BIST hold */
65 #define BCM_BMIPS33_BIST_STATUS 0x08 /**< built-in self-test status */
66 #define BCM_BMIPS33_INTR_STATUS BCM_BMIPS_INTR_STATUS
67 #define BCM_BMIPS33_INTR_MASK BCM_BMIPS_INTR_MASK
68 #define BCM_BMIPS33_TIMER_CTRL BCM_BMIPS_TIMER_CTRL
69 #define BCM_BMIPS33_TEST_MUX_SEL 0x30 /**< test multiplexer select (?) */
70 #define BCM_BMIPS33_TEST_MUX_EN 0x34 /**< test multiplexer enable (?) */
71 #define BCM_BMIPS33_EJTAG_GPIO_EN 0x2C /**< ejtag gpio enable */
73 #endif /* _MIPS_BROADCOM_BMIPSREG_H_ */