2 * Copyright (c) 2007 Bruce M. Simpson.
3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
4 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
5 * Copyright (c) 2017 The FreeBSD Foundation
8 * Portions of this software were developed by Landon Fuller
9 * under sponsorship from the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
40 #include <sys/kernel.h>
41 #include <sys/systm.h>
42 #include <sys/imgact.h>
49 #include <sys/ucontext.h>
52 #include <sys/ptrace.h>
53 #include <sys/reboot.h>
54 #include <sys/signalvar.h>
55 #include <sys/sysent.h>
56 #include <sys/sysproto.h>
60 #include <vm/vm_object.h>
61 #include <vm/vm_page.h>
63 #include <machine/cache.h>
64 #include <machine/clock.h>
65 #include <machine/cpu.h>
66 #include <machine/cpuinfo.h>
67 #include <machine/cpufunc.h>
68 #include <machine/cpuregs.h>
69 #include <machine/hwfunc.h>
70 #include <machine/intr_machdep.h>
71 #include <machine/locore.h>
72 #include <machine/md_var.h>
73 #include <machine/pte.h>
74 #include <machine/sigframe.h>
75 #include <machine/trap.h>
76 #include <machine/vmparam.h>
78 #include <dev/bhnd/bhnd.h>
79 #include <dev/bhnd/bhndreg.h>
80 #include <dev/bhnd/bhnd_eromvar.h>
82 #include <dev/bhnd/bcma/bcma_eromvar.h>
84 #include <dev/bhnd/siba/sibareg.h>
85 #include <dev/bhnd/siba/sibavar.h>
87 #include <dev/bhnd/cores/chipc/chipcreg.h>
88 #include <dev/bhnd/cores/pmu/bhnd_pmureg.h>
90 #include "bcm_machdep.h"
91 #include "bcm_bmips_exts.h"
94 #include <dev/cfe/cfe_api.h>
95 #include <dev/cfe/cfe_error.h>
99 #define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
101 #define BCM_TRACE(_fmt, ...)
104 static int bcm_init_platform_data(struct bcm_platform *bp);
106 static int bcm_find_core(struct bcm_platform *bp,
107 const struct bhnd_core_match *descs, size_t num_descs,
108 struct bhnd_core_info *info, uintptr_t *addr);
110 static int bcm_erom_probe_and_attach(bhnd_erom_class_t **erom_cls,
111 kobj_ops_t erom_ops, bhnd_erom_t *erom, size_t esize,
112 struct bhnd_erom_io *eio, struct bhnd_chipid *cid);
117 static struct bcm_platform bcm_platform_data;
118 static bool bcm_platform_data_avail = false;
121 static struct bcm_nvram_iocfe bcm_cfe_nvram;
124 static const struct bhnd_core_match bcm_chipc_cores[] = {
125 { BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_CC) },
126 { BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_4706_CC) },
129 static const struct bhnd_core_match bcm_pmu_cores[] = {
130 { BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_PMU) },
133 struct bcm_platform *
134 bcm_get_platform(void)
136 if (!bcm_platform_data_avail)
137 panic("platform data not available");
139 return (&bcm_platform_data);
143 bcm_get_bus_addr(void)
147 if (resource_long_value("bhnd", 0, "maddr", &maddr) == 0)
148 return ((u_long)maddr);
150 return (BHND_DEFAULT_CHIPC_ADDR);
154 bcm_get_bus_size(void)
158 if (resource_long_value("bhnd", 0, "msize", &msize) == 0)
159 return ((u_long)msize);
161 return (BHND_DEFAULT_ENUM_SIZE);
165 * Search the device enumeration table for a core matching @p descs,
167 * @param bp Platform state containing a valid EROM parser.
168 * @param descs The core match descriptor table.
169 * @param num_descs The number of match descriptors in @p descs.
170 * @param[out] info If non-NULL, will be populated with the core
172 * @param[out] addr If non-NULL, will be populated with the core's
173 * physical register address.
176 bcm_find_core(struct bcm_platform *bp, const struct bhnd_core_match *descs,
177 size_t num_descs, struct bhnd_core_info *info, uintptr_t *addr)
183 /* Fetch core info */
184 for (size_t i = 0; i < num_descs; i++) {
185 error = bhnd_erom_lookup_core_addr(&bp->erom.obj, &descs[i],
186 BHND_PORT_DEVICE, 0, 0, info, &b_addr, &b_size);
188 /* Terminate search on first match */
192 /* Terminate on first error (other than core not found) */
196 /* Continue search ... */
199 /* Provide the core's base address */
200 if (addr != NULL && b_addr > UINTPTR_MAX) {
201 BCM_ERR("core address %#jx overflows native address width\n",
213 * Read a variable directly from NVRAM, decoding as @p type.
215 * @param bp Platform state.
216 * @param name The raw name of the variable to be fetched,
217 * including any device path (/pci/1/1/varname) or
218 * alias prefix (0:varname).
219 * @param[out] buf On success, the requested value will be written
220 * to this buffer. This argment may be NULL if
221 * the value is not desired.
222 * @param[in,out] len The capacity of @p buf. On success, will be set
223 * to the actual size of the requested value.
224 * @param type The data type to be written to @p buf.
227 * @retval ENOMEM If @p buf is non-NULL and a buffer of @p len is too
228 * small to hold the requested value.
229 * @retval ENOENT If @p name is not found.
230 * @retval EFTYPE If the variable data cannot be coerced to @p type.
231 * @retval ERANGE If value coercion would overflow @p type.
232 * @retval non-zero If parsing NVRAM otherwise fails, a regular unix error
233 * code will be returned.
236 bcm_get_nvram(struct bcm_platform *bp, const char *name, void *buf, size_t *len,
237 bhnd_nvram_type type)
239 if (bp->nvram_io == NULL || bp->nvram_cls == NULL)
242 return (bhnd_nvram_data_getvar_direct(bp->nvram_cls, bp->nvram_io, name,
247 * Probe and attach a bhnd_erom parser instance for the bhnd bus.
249 * @param[out] erom_cls The probed EROM class.
250 * @param[out] erom_ops The storage to be used when compiling
252 * @param[out] erom The storage to be used when initializing the
253 * static instance of @p erom_cls.
254 * @param esize The total available number of bytes allocated
255 * for @p erom. If this is less than is required
256 * by @p erom_cls ENOMEM will be returned.
257 * @param eio EROM I/O callbacks to be used.
258 * @param[out] cid On success, the probed chip identification.
261 bcm_erom_probe_and_attach(bhnd_erom_class_t **erom_cls, kobj_ops_t erom_ops,
262 bhnd_erom_t *erom, size_t esize, struct bhnd_erom_io *eio,
263 struct bhnd_chipid *cid)
265 bhnd_erom_class_t **clsp;
267 int error, prio, result;
272 /* Map our first bus core for the erom probe */
273 bus_addr = bcm_get_bus_addr();
274 if ((error = bhnd_erom_io_map(eio, bus_addr, BHND_DEFAULT_CORE_SIZE))) {
275 BCM_ERR("failed to map first core at %#jx+%#jx: %d\n",
276 (uintmax_t)bus_addr, (uintmax_t)BHND_DEFAULT_CORE_SIZE,
282 SET_FOREACH(clsp, bhnd_erom_class_set) {
283 struct bhnd_chipid pcid;
284 bhnd_erom_class_t *cls;
285 struct kobj_ops kops;
289 /* Compile the class' ops table */
290 kobj_class_compile_static(cls, &kops);
292 /* Probe the bus address */
293 result = bhnd_erom_probe(cls, eio, NULL, &pcid);
295 /* Drop pointer to stack allocated ops table */
298 /* The parser did not match if an error was returned */
302 /* Check for a new highest priority match */
303 if (*erom_cls == NULL || result > prio) {
310 /* Terminate immediately on BUS_PROBE_SPECIFIC */
311 if (result == BUS_PROBE_SPECIFIC)
315 /* Valid EROM class probed? */
316 if (*erom_cls == NULL) {
317 BCM_ERR("no erom parser found for root bus at %#jx\n",
318 (uintmax_t)bus_addr);
323 /* Using the provided storage, recompile the erom class ... */
324 kobj_class_compile_static(*erom_cls, erom_ops);
326 /* ... and initialize the erom parser instance */
327 error = bhnd_erom_init_static(*erom_cls, erom, esize, cid, eio);
333 * Populate platform configuration data.
336 bcm_init_platform_data(struct bcm_platform *bp)
338 bus_addr_t bus_addr, bus_size;
339 bus_space_tag_t erom_bst;
340 bus_space_handle_t erom_bsh;
344 bus_addr = bcm_get_bus_addr();
345 bus_size = bcm_get_bus_size();
348 /* Fetch CFE console handle (if any). Must be initialized before
349 * any calls to printf/early_putc. */
350 if ((bp->cfe_console = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE)) < 0)
351 bp->cfe_console = -1;
353 /* Probe CFE NVRAM sources */
354 bp->nvram_io = &bcm_cfe_nvram.io;
355 error = bcm_nvram_find_cfedev(&bcm_cfe_nvram, &bp->nvram_cls);
358 bp->nvram_cls = NULL;
362 /* Probe and attach device table provider, populating our
363 * chip identification */
364 erom_bst = mips_bus_space_generic;
365 erom_bsh = BCM_SOC_BSH(bus_addr, 0);
367 error = bhnd_erom_iobus_init(&bp->erom_io, bus_addr, bus_size, erom_bst,
370 BCM_ERR("failed to initialize erom I/O callbacks: %d\n", error);
374 error = bcm_erom_probe_and_attach(&bp->erom_impl, &bp->erom_ops,
375 &bp->erom.obj, sizeof(bp->erom), &bp->erom_io.eio, &bp->cid);
377 BCM_ERR("error attaching erom parser: %d\n", error);
378 bhnd_erom_io_fini(&bp->erom_io.eio);
383 bhnd_erom_dump(&bp->erom.obj);
385 /* Fetch chipcommon core info */
386 error = bcm_find_core(bp, bcm_chipc_cores, nitems(bcm_chipc_cores),
387 &bp->cc_id, &bp->cc_addr);
389 BCM_ERR("error locating chipc core: %d\n", error);
393 /* Fetch chipc capability flags */
394 bp->cc_caps = BCM_SOC_READ_4(bp->cc_addr, CHIPC_CAPABILITIES);
395 bp->cc_caps_ext = 0x0;
397 if (CHIPC_HWREV_HAS_CAP_EXT(bp->cc_id.hwrev))
398 bp->cc_caps_ext = BCM_CHIPC_READ_4(bp, CHIPC_CAPABILITIES_EXT);
401 pmu = CHIPC_GET_FLAG(bp->cc_caps, CHIPC_CAP_PMU);
402 aob = CHIPC_GET_FLAG(bp->cc_caps_ext, CHIPC_CAP2_AOB);
405 /* PMU block mapped to a PMU core on the Always-on-Bus (aob) */
406 error = bcm_find_core(bp, bcm_pmu_cores, nitems(bcm_pmu_cores),
407 &bp->pmu_id, &bp->pmu_addr);
409 BCM_ERR("error locating pmu core: %d\n", error);
413 /* PMU block mapped to chipc */
414 bp->pmu_addr = bp->cc_addr;
415 bp->pmu_id = bp->cc_id;
419 memset(&bp->pmu_id, 0, sizeof(bp->pmu_id));
422 /* Initialize PMU query state */
424 error = bhnd_pmu_query_init(&bp->pmu, NULL, bp->cid,
425 &bcm_pmu_soc_io, bp);
427 BCM_ERR("bhnd_pmu_query_init() failed: %d\n", error);
432 /* Initialize our platform service registry */
433 if ((error = bhnd_service_registry_init(&bp->services))) {
434 BCM_ERR("error initializing service registry: %d\n", error);
438 bcm_platform_data_avail = true;
445 /* Nothing special */
453 printf("entry: mips_init()\n");
457 * Query DRAM memory map from CFE.
460 for (i = 0; i < 10; i += 2) {
462 uint64_t addr, len, type;
464 result = cfe_enummem(i / 2, 0, &addr, &len, &type);
466 BCM_TRACE("There is no phys memory for: %d\n", i);
467 phys_avail[i] = phys_avail[i + 1] = 0;
470 if (type != CFE_MI_AVAILABLE) {
471 BCM_TRACE("phys memory is not available: %d\n", i);
475 phys_avail[i] = addr;
476 if (i == 0 && addr == 0) {
478 * If this is the first physical memory segment probed
479 * from CFE, omit the region at the start of physical
480 * memory where the kernel has been loaded.
482 phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
485 BCM_TRACE("phys memory is available for: %d\n", i);
486 BCM_TRACE(" => addr = %jx\n", addr);
487 BCM_TRACE(" => len = %jd\n", len);
489 phys_avail[i + 1] = addr + len;
493 BCM_TRACE("Total phys memory is : %ld\n", physmem);
494 realmem = btoc(physmem);
497 for (j = 0; j < i; j++)
498 dump_avail[j] = phys_avail[j];
503 init_param2(physmem);
510 if (boothowto & RB_KDB)
511 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
518 struct bcm_platform *bp;
521 printf("bcm::platform_reset()\n");
525 /* Fall back on CFE if reset requested during platform
526 * data initialization */
527 if (!bcm_platform_data_avail) {
533 bp = bcm_get_platform();
536 /* Handle BCM4785-specific behavior */
537 if (bp->cid.chip_id == BHND_CHIPID_BCM4785) {
540 /* Switch to async mode */
541 bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM);
544 /* Set watchdog (PMU or ChipCommon) */
545 if (bp->pmu_addr != 0x0) {
546 BCM_PMU_WRITE_4(bp, BHND_PMU_WATCHDOG, 1);
548 BCM_CHIPC_WRITE_4(bp, CHIPC_WATCHDOG, 1);
553 __asm __volatile("wait");
560 platform_start(__register_t a0, __register_t a1, __register_t a2,
564 uint64_t platform_counter_freq;
567 /* clear the BSS and SBSS segments */
568 kernend = (vm_offset_t)&end;
569 memset(&edata, 0, kernend - (vm_offset_t)(&edata));
571 mips_postboot_fixup();
573 /* Initialize pcpu stuff */
578 * Initialize CFE firmware trampolines. This must be done
579 * before any CFE APIs are called, including writing
580 * to the CFE console.
582 * CFE passes the following values in registers:
583 * a0: firmware handle
584 * a2: firmware entry point
585 * a3: entry point seal
587 if (a3 == CFE_EPTSEAL)
591 /* Init BCM platform data */
592 if ((error = bcm_init_platform_data(&bcm_platform_data)))
593 panic("bcm_init_platform_data() failed: %d", error);
595 platform_counter_freq = bcm_get_cpufreq(bcm_get_platform());
597 /* CP0 ticks every two cycles */
598 mips_timer_early_init(platform_counter_freq / 2);
604 mips_timer_init_params(platform_counter_freq, 1);
608 * CFE-based EARLY_PRINTF support. To use, add the following to the kernel
610 * option EARLY_PRINTF
614 #if defined(EARLY_PRINTF) && defined(CFE)
621 ch = (unsigned char) c;
623 /* bcm_get_platform() cannot be used here, as we may be called
624 * from bcm_init_platform_data(). */
625 if ((handle = bcm_platform_data.cfe_console) < 0)
631 while ((cfe_write(handle, &ch, 1)) == 0)
635 early_putc_t *early_putc = bcm_cfe_eputc;
636 #endif /* EARLY_PRINTF */