2 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
32 #ifndef _MIPS_BROADCOM_BCM_MACHDEP_H_
33 #define _MIPS_BROADCOM_BCM_MACHDEP_H_
35 #include <machine/cpufunc.h>
36 #include <machine/cpuregs.h>
38 #include <dev/bhnd/bhnd.h>
39 #include <dev/bhnd/bhnd_erom.h>
41 #include <dev/bhnd/cores/pmu/bhnd_pmuvar.h>
43 #include "bcm_nvram_cfevar.h"
45 extern const struct bhnd_pmu_io bcm_pmu_soc_io;
48 struct bhnd_chipid cid; /**< chip id */
49 struct bhnd_core_info cc_id; /**< chipc core info */
50 uintptr_t cc_addr; /**< chipc core phys address */
51 uint32_t cc_caps; /**< chipc capabilities */
52 uint32_t cc_caps_ext; /**< chipc extended capabilies */
54 /* On non-AOB devices, the PMU register block is mapped to chipc;
55 * the pmu_id and pmu_addr values will be copied from cc_id
57 struct bhnd_core_info pmu_id; /**< PMU core info */
58 uintptr_t pmu_addr; /**< PMU core phys address, or
61 struct bhnd_pmu_query pmu; /**< PMU query instance */
63 bhnd_erom_class_t *erom_impl; /**< erom parser class */
64 struct kobj_ops erom_ops; /**< compiled kobj opcache */
66 bhnd_erom_static_t data;
70 struct bhnd_nvram_io *nvram_io; /**< NVRAM I/O context, or NULL if unavailable */
71 bhnd_nvram_data_class *nvram_cls; /**< NVRAM data class, or NULL if unavailable */
74 int cfe_console; /**< Console handle, or -1 */
78 struct bcm_platform *bcm_get_platform(void);
80 uint64_t bcm_get_cpufreq(struct bcm_platform *bp);
81 uint64_t bcm_get_sifreq(struct bcm_platform *bp);
82 uint64_t bcm_get_alpfreq(struct bcm_platform *bp);
83 uint64_t bcm_get_ilpfreq(struct bcm_platform *bp);
85 u_int bcm_get_uart_rclk(struct bcm_platform *bp);
87 int bcm_get_nvram(struct bcm_platform *bp,
88 const char *name, void *outp, size_t *olen,
89 bhnd_nvram_type type);
91 #define BCM_ERR(fmt, ...) \
92 printf("%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
94 #define BCM_SOC_BSH(_addr, _offset) \
95 ((bus_space_handle_t)BCM_SOC_ADDR((_addr), (_offset)))
97 #define BCM_SOC_ADDR(_addr, _offset) \
98 MIPS_PHYS_TO_KSEG1((_addr) + (_offset))
100 #define BCM_SOC_READ_4(_addr, _offset) \
101 readl(BCM_SOC_ADDR((_addr), (_offset)))
102 #define BCM_SOC_WRITE_4(_addr, _reg, _val) \
103 writel(BCM_SOC_ADDR((_addr), (_offset)), (_val))
105 #define BCM_CORE_ADDR(_bp, _name, _reg) \
106 BCM_SOC_ADDR(_bp->_name, (_reg))
108 #define BCM_CORE_READ_4(_bp, _name, _reg) \
109 readl(BCM_CORE_ADDR(_bp, _name, (_reg)))
110 #define BCM_CORE_WRITE_4(_bp, _name, _reg, _val) \
111 writel(BCM_CORE_ADDR(_bp, _name, (_reg)), (_val))
113 #define BCM_CHIPC_READ_4(_bp, _reg) \
114 BCM_CORE_READ_4(_bp, cc_addr, (_reg))
115 #define BCM_CHIPC_WRITE_4(_bp, _reg, _val) \
116 BCM_CORE_WRITE_4(_bp, cc_addr, (_reg), (_val))
118 #define BCM_PMU_READ_4(_bp, _reg) \
119 BCM_CORE_READ_4(_bp, pmu_addr, (_reg))
120 #define BCM_PMU_WRITE_4(_bp, _reg, _val) \
121 BCM_CORE_WRITE_4(_bp, pmu_addr, (_reg), (_val))
123 #endif /* _MIPS_BROADCOM_BCM_MACHDEP_H_ */