2 * Copyright (c) 2017 The FreeBSD Foundation
5 * This software was developed by Landon Fuller under sponsorship from
6 * the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
16 * redistribution must be conditioned upon including a substantially
17 * similar Disclaimer requirement for further binary redistribution.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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35 #ifndef _MIPS_BROADCOM_BCM_MIPSVAR_H_
36 #define _MIPS_BROADCOM_BCM_MIPSVAR_H_
38 #include <sys/param.h>
43 #include <machine/intr.h>
45 DECLARE_CLASS(bcm_mips_driver);
47 struct bcm_mips_irqsrc;
48 struct bcm_mips_softc;
50 #define BCM_MIPS_NINTR 32 /**< maximum number of addressable backplane interrupt vectors */
51 #define BCM_MIPS_IRQ_SHARED 0 /**< MIPS CPU IRQ reserved for shared interrupt handling */
52 #define INTR_MAP_DATA_BCM_MIPS INTR_MAP_DATA_PLAT_2 /**< Broadcom MIPS PIC interrupt map data type */
54 int bcm_mips_attach(device_t dev, u_int num_cpuirqs, u_int timer_irq,
55 driver_filter_t filter);
56 int bcm_mips_detach(device_t dev);
59 * Broadcom MIPS PIC interrupt map data.
61 struct bcm_mips_intr_map_data {
62 struct intr_map_data mdata;
63 u_int ivec; /**< bus interrupt vector */
67 * Nested MIPS CPU interrupt handler state.
69 struct bcm_mips_cpuirq {
70 struct bcm_mips_softc *sc; /**< driver instance state, or NULL if uninitialized. */
71 u_int mips_irq; /**< mips hardware interrupt number (relative to NSOFT_IRQ) */
72 int irq_rid; /**< mips IRQ resource id, or -1 if this entry is unavailable */
73 struct resource *irq_res; /**< mips interrupt resource */
74 void *irq_cookie; /**< mips interrupt handler cookie, or NULL */
75 struct bcm_mips_irqsrc *isrc_solo; /**< solo isrc assigned to this interrupt, or NULL */
76 u_int refs; /**< isrc consumer refcount */
80 * Broadcom MIPS PIC interrupt source definition.
82 struct bcm_mips_irqsrc {
83 struct intr_irqsrc isrc;
84 u_int ivec; /**< bus interrupt vector */
85 u_int refs; /**< active reference count */
86 struct bcm_mips_cpuirq *cpuirq; /**< assigned MIPS HW IRQ, or NULL if no assignment */
90 * bcm_mips driver instance state. Must be first member of all subclass
93 struct bcm_mips_softc {
95 struct bcm_mips_cpuirq cpuirqs[NREAL_IRQS]; /**< nested CPU IRQ handlers */
96 u_int num_cpuirqs; /**< number of nested CPU IRQ handlers */
97 u_int timer_irq; /**< CPU timer IRQ */
98 struct bcm_mips_irqsrc isrcs[BCM_MIPS_NINTR];
102 #define BCM_MIPS_IVEC_MASK(_isrc) (1 << ((_isrc)->ivec))
104 #define BCM_MIPS_LOCK_INIT(sc) \
105 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
106 "bhnd mips driver lock", MTX_DEF)
107 #define BCM_MIPS_LOCK(sc) mtx_lock(&(sc)->mtx)
108 #define BCM_MIPS_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
109 #define BCM_MIPS_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
110 #define BCM_MIPS_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
112 #endif /* _MIPS_BROADCOM_BCM_MIPSVAR_H_ */