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41 /*------------------------------------------------------------------
42 * octeon_fpa.h Free Pool Allocator
44 *------------------------------------------------------------------
48 #ifndef ___OCTEON_FPA__H___
49 #define ___OCTEON_FPA__H___
52 #define OCTEON_FPA_FPA_OUTPUT_BUFFER_POOL 2 /* Same in octeon_rgmx.h */
56 * OCTEON_FPA_FPF_MARKS = FPA's Queue Free Page FIFO Read Write Marks
58 * The high and low watermark register that determines when we write and
59 * read free pages from L2C for Queue.
64 uint64_t reserved : 42; /* Must be zero */
65 uint64_t fpf_wr : 11; /* Write Hi Water mark */
66 uint64_t fpf_rd : 11; /* Read Lo Water mark */
68 } octeon_fpa_fpf_marks_t;
72 * OCTEON_FPA_CTL_STATUS = FPA's Control/Status Register
74 * The FPA's interrupt enable register.
75 * - Use with the CVMX_FPA_CTL_STATUS CSR.
80 uint64_t reserved : 49; /* Must be zero */
81 uint64_t enb : 1; /* Enable */
82 uint64_t mem1_err : 7; /* ECC flip 1 */
83 uint64_t mem0_err : 7; /* ECC flip 0 */
85 } octeon_fpa_ctl_status_t;
89 * OCTEON_FPA_FPF_SIZE = FPA's Queue N Free Page FIFO Size
91 * The number of page pointers that will be kept local to the FPA for
92 * this Queue. FPA Queues are assigned in order from Queue 0 to
93 * Queue 7, though only Queue 0 through Queue x can be used.
94 * The sum of the 8 (0-7)OCTEON_FPA_FPF#_SIZE registers must be limited to 2048.
95 * - Use with the CVMX_FPA_FPF0_SIZE CSR.
100 uint64_t reserved : 52; /* Must be zero */
102 * The number of entries assigned in the FPA FIFO (used to hold
103 * page-pointers) for this Queue.
104 * The value of this register must divisable by 2, and the FPA will
105 * ignore bit [0] of this register.
106 * The total of the FPF_SIZ field of the 8 (0-7)OCTEON_FPA_FPF#_MARKS
107 * registers must not exceed 2048.
108 * After writing this field the FPA will need 10 core clock cycles
109 * to be ready for operation. The assignment of location in
110 * the FPA FIFO must start with Queue 0, then 1, 2, etc.
111 * The number of useable entries will be FPF_SIZ-2.
113 uint64_t fpf_siz : 12;
115 } octeon_fpa_fpf_size_t;
118 *OCTEON_FPA_INT_ENB = FPA's Interrupt Enable
120 * The FPA's interrupt enable register.
121 * - Use with the CVMX_FPA_INT_ENB CSR.
126 uint64_t reserved : 60; /* Must be zero */
127 uint64_t fed1_dbe : 1; /* Int iff bit3 Int-Sum set */
128 uint64_t fed1_sbe : 1; /* Int iff bit2 Int-Sum set */
129 uint64_t fed0_dbe : 1; /* Int iff bit1 Int-Sum set */
130 uint64_t fed0_sbe : 1; /* Int iff bit0 Int-Sum set */
132 } octeon_fpa_int_enb_t;
135 *OCTEON_FPA_INT_SUM = FPA's Interrupt Summary Register
137 * Contains the diffrent interrupt summary bits of the FPA.
138 * - Use with the CVMX_FPA_INT_SUM CSR.
143 uint64_t reserved : 60; /**< Must be zero */
144 uint64_t fed1_dbe : 1;
145 uint64_t fed1_sbe : 1;
146 uint64_t fed0_dbe : 1;
147 uint64_t fed0_sbe : 1;
149 } octeon_fpa_int_sum_t;
153 *OCTEON_FPA_QUEUE_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register
155 * The number of page pointers that are available in the FPA and local DRAM.
156 * - Use with the CVMX_FPA_QUEX_AVAILABLE(0..7) CSR.
161 uint64_t reserved : 38; /* Must be zero */
162 uint64_t queue_size : 26; /* free pages available */
164 } octeon_fpa_queue_available_t;
168 *OCTEON_FPA_QUEUE_PAGE_INDEX
174 uint64_t reserved : 39; /* Must be zero */
175 uint64_t page_index : 25; /* page_index */
177 } octeon_fpa_queue_page_index_t;
180 #define OCTEON_DID_FPA 5ULL
182 #define OCTEON_FPA_POOL_ALIGNMENT (OCTEON_CACHE_LINE_SIZE)
188 extern void octeon_dump_fpa(void);
189 extern void octeon_dump_fpa_pool(u_int pool);
190 extern u_int octeon_fpa_pool_size(u_int pool);
191 extern void octeon_enable_fpa(void);
192 extern void octeon_fpa_fill_pool_mem(u_int pool,
193 u_int block_size_words,
199 * Free a mem-block to FPA pool.
201 * Takes away this 'buffer' from SW and passes it to FPA for management.
203 * pool is FPA pool num, ptr is block ptr, num_cache_lines is number of
204 * cache lines to invalidate (not written back).
206 static inline void octeon_fpa_free (void *ptr, u_int pool,
207 u_int num_cache_lines)
209 octeon_addr_t free_ptr;
211 free_ptr.word64 = (uint64_t)OCTEON_PTR2PHYS(ptr);
213 free_ptr.sfilldidspace.didspace = OCTEON_ADDR_DIDSPACE(
214 OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA, pool));
218 * asm volatile ("sync\n");
220 oct_write64(free_ptr.word64, num_cache_lines);
228 * Allocate a new block from the FPA
230 * Buffer passes away from FPA management to SW control
232 static inline void *octeon_fpa_alloc (u_int pool)
236 address = oct_read64(OCTEON_ADDR_DID(OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA,
241 * 32 bit FPA pointers only
244 * We only use 32 bit pointers at this time
246 /*XXX mips64 issue */
247 return ((void *) MIPS_PHYS_TO_KSEG0(address & 0xffffffff));
252 static inline uint64_t octeon_fpa_alloc_phys (u_int pool)
255 return (oct_read64(OCTEON_ADDR_DID(OCTEON_ADDR_FULL_DID(OCTEON_DID_FPA,
259 #endif /* ___OCTEON_FPA__H___ */