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41 /*------------------------------------------------------------------
42 * octeon_pko.h Packet Output Block
44 *------------------------------------------------------------------
48 #ifndef ___OCTEON_PKO__H___
49 #define ___OCTEON_PKO__H___
54 * PKO Command Buffer Register.
55 * Specify Pool-# and Size of each entry in Pool. For Output Cmd Buffers.
60 uint64_t unused_mbz : 41; /* Must be zero */
61 uint64_t pool : 3; /* FPA Pool to use */
62 uint64_t unused_mbz2 : 7; /* Must be zero */
63 uint64_t size : 13; /* Size of the pool blocks */
65 } octeon_pko_pool_cfg_t;
69 * PKO GMX Mode Register
70 * Specify the # of GMX1 ports and GMX0 ports
75 uint64_t unused_mbz : 58; /* MBZ */
76 uint64_t mode1 : 3; /* # GMX1 ports; */
77 /* 16 >> MODE1, 0 <= MODE1 <=4 */
78 uint64_t mode0 : 3; /* # GMX0 ports; */
79 /* 16 >> MODE0, 0 <= MODE0 <=4 */
81 } octeon_pko_reg_gmx_port_mode_t;
87 uint64_t unused_mbz : 62; /* MBZ */
88 uint64_t mode : 2; /* Queues Mode */
90 } octeon_pko_queue_mode_t;
96 uint64_t unused_mbz : 32; /* MBZ */
97 uint64_t crc_ports_mask : 32; /* CRC Ports Enable mask */
99 } octeon_pko_crc_ports_enable_t;
103 #define OCTEON_PKO_QUEUES_MAX 128
104 #define OCTEON_PKO_PORTS_MAX 36
105 #define OCTEON_PKO_PORT_ILLEGAL 63
107 /* Defines how the PKO command buffer FAU register is used */
109 #define OCTEON_PKO_INDEX_BITS 12
110 #define OCTEON_PKO_INDEX_MASK ((1ull << OCTEON_PKO_INDEX_BITS) - 1)
116 OCTEON_PKO_INVALID_PORT,
117 OCTEON_PKO_INVALID_QUEUE,
118 OCTEON_PKO_INVALID_PRIORITY,
120 } octeon_pko_status_t;
127 } octeon_pko_port_status_t;
133 octeon_mips_space_t mem_space : 2; /* Octeon IO_SEG */
134 uint64_t unused_mbz :13; /* Must be zero */
135 uint64_t is_io : 1; /* Must be one */
136 uint64_t did : 8; /* device-ID on non-coherent bus*/
137 uint64_t unused_mbz2 : 4; /* Must be zero */
138 uint64_t unused_mbz3 :18; /* Must be zero */
139 uint64_t port : 6; /* output port */
140 uint64_t queue : 9; /* output queue to send */
141 uint64_t unused_mbz4 : 3; /* Must be zero */
143 } octeon_pko_doorbell_address_t;
146 * Structure of the first packet output command word.
151 octeon_fau_op_size_t size1 : 2; /* The size of reg1 operation */
152 /* - could be 8, 16, 32, or 64 bits */
153 octeon_fau_op_size_t size0 : 2; /* The size of the reg0 operation */
154 /* - could be 8, 16, 32, or 64 bits */
155 uint64_t subone1 : 1; /* Subtract 1, else sub pkt size */
156 uint64_t reg1 :11; /* The register, subtract will be */
157 /* done if reg1 is non-zero */
158 uint64_t subone0 : 1; /* Subtract 1, else sub pkt size */
159 uint64_t reg0 :11; /* The register, subtract will be */
160 /* done if reg0 is non-zero */
161 uint64_t unused : 2; /* Must be zero */
162 uint64_t wqp : 1; /* If rsp, then word3 contains a */
163 /* ptr to a work queue entry */
164 uint64_t rsp : 1; /* HW will respond when done */
165 uint64_t gather : 1; /* If set, the supplied pkt_ptr is */
166 /* a ptr to a list of pkt_ptr's */
167 uint64_t ipoffp1 : 7; /* Off to IP hdr. For HW checksum */
168 uint64_t ignore_i : 1; /* Ignore I bit in all pointers */
169 uint64_t dontfree : 1; /* Don't free buffs containing pkt */
170 uint64_t segs : 6; /* Number of segs. If gather set, */
171 /* also gather list length */
172 uint64_t total_bytes :16; /* Includes L2, w/o trailing CRC */
174 } octeon_pko_command_word0_t;
181 uint64_t i : 1; /* Invert the "free" pick of the overall pkt. */
182 /* For inbound pkts, HW always sets this to 0 */
183 uint64_t back : 4; /* Amount to back up to get to buffer start */
184 /* in cache lines. This is mostly less than 1 */
185 /* complete cache line; so the value is zero */
186 uint64_t pool : 3; /* FPA pool that the buffer belongs to */
187 uint64_t size :16; /* segment size (bytes) pointed at by addr */
188 uint64_t addr :40; /* Ptr to 1st data byte. NOT buffer */
190 } octeon_pko_packet_ptr_t;
194 * Definition of the hardware structure used to configure an
200 uint64_t unused_mbz : 3; /* Must be zero */
201 uint64_t qos_mask : 8; /* Control Mask priority */
202 /* across 8 QOS levels */
203 uint64_t buf_ptr : 36; /* Command buffer pointer, */
205 uint64_t tail : 1; /* Set if this queue is the tail */
206 /* of the port queue array */
207 uint64_t index : 3; /* Index (distance from head) in */
208 /* the port queue array */
209 uint64_t port : 6; /* Port ID for this queue mapping */
210 uint64_t queue : 7; /* Hardware queue number */
212 } octeon_pko_queue_cfg_t;
218 uint64_t unused_mbz : 48;
222 } octeon_pko_read_idx_t;
225 typedef struct octeon_pko_sw_queue_info_t_
227 uint64_t xmit_command_state;
228 octeon_spinlock_t lock;
230 } octeon_pko_sw_queue_info_t;
234 #define OCTEON_DID_PKT 10ULL
235 #define OCTEON_DID_PKT_SEND OCTEON_ADDR_FULL_DID(OCTEON_DID_PKT,2ULL)
239 * Ring the packet output doorbell. This tells the packet
240 * output hardware that "len" command words have been added
241 * to its pending list. This command includes the required
242 * SYNCW before the doorbell ring.
244 * @param port Port the packet is for
245 * @param queue Queue the packet is for
246 * @param len Length of the command in 64 bit words
248 extern void octeon_pko_doorbell_data(u_int port);
250 //#define CORE_0_ONLY 1
252 static inline void octeon_pko_ring_doorbell (u_int port, u_int queue,
255 octeon_pko_doorbell_address_t ptr;
258 ptr.bits.mem_space = OCTEON_IO_SEG;
259 ptr.bits.did = OCTEON_DID_PKT_SEND;
261 ptr.bits.port = port;
262 ptr.bits.queue = queue;
264 oct_write64(ptr.word64, len);
269 #define OCTEON_PKO_QUEUES_PER_PORT_INTERFACE0 1
270 #define OCTEON_PKO_QUEUES_PER_PORT_INTERFACE1 1
271 #define OCTEON_PKO_QUEUES_PER_PORT_PCI 1
274 * octeon_pko_get_base_queue
276 * For a given port number, return the base pko output queue
279 static inline u_int octeon_pko_get_base_queue (u_int port)
282 return (port * OCTEON_PKO_QUEUES_PER_PORT_INTERFACE0);
285 return (16 * OCTEON_PKO_QUEUES_PER_PORT_INTERFACE0 +
286 (port - 16) * OCTEON_PKO_QUEUES_PER_PORT_INTERFACE1);
288 return (16 * OCTEON_PKO_QUEUES_PER_PORT_INTERFACE0 +
289 16 * OCTEON_PKO_QUEUES_PER_PORT_INTERFACE1 +
290 (port - 32) * OCTEON_PKO_QUEUES_PER_PORT_PCI);
295 * For a given port number, return the number of pko output queues.
297 * @param port Port number
298 * @return Number of output queues
300 static inline u_int octeon_pko_get_num_queues(u_int port)
303 return (OCTEON_PKO_QUEUES_PER_PORT_INTERFACE0);
304 } else if (port<32) {
305 return (OCTEON_PKO_QUEUES_PER_PORT_INTERFACE1);
308 return (OCTEON_PKO_QUEUES_PER_PORT_PCI);
316 extern void octeon_pko_init(void);
317 extern void octeon_pko_enable(void);
318 extern void octeon_pko_disable(void);
319 extern void octeon_pko_show(u_int start_port, u_int end_port);
320 extern void octeon_pko_config(void);
321 extern void octeon_pko_config_cmdbuf_global_defaults(u_int cmdbuf_pool, u_int elem_size);
322 extern void octeon_pko_config_rgmx_ports(void);
323 extern void octeon_pko_get_port_status(u_int, u_int, octeon_pko_port_status_t *status);
324 extern octeon_pko_status_t octeon_pko_config_port(u_int port,
327 const u_int priority[],
328 u_int pko_output_cmdbuf_fpa_pool,
329 octeon_pko_sw_queue_info_t sw_queues[]);
332 #endif /* ___OCTEON_PKO__H___ */