2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010 Juli Mallett <jmallett@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
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12 * 2. Redistributions in binary form must reproduce the above copyright
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23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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32 * Register definitions for Marvell MV88E61XX
34 * Note that names and definitions were gleaned from Linux and U-Boot patches
35 * released by Marvell, often by looking at contextual use of the registers
36 * involved, and may not be representative of the full functionality of those
37 * registers and are certainly not an exhaustive enumeration of registers.
39 * For an exhaustive enumeration of registers, check out the QD-DSDT package
40 * included in the Marvell ARM Feroceon Board Support Package for Linux.
43 #ifndef _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
44 #define _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
47 * Port addresses & per-port registers.
49 #define MV88E61XX_PORT(x) (0x10 + (x))
50 #define MV88E61XX_HOST_PORT (5)
51 #define MV88E61XX_PORTS (6)
53 #define MV88E61XX_PORT_STATUS (0x00)
54 #define MV88E61XX_PORT_FORCE_MAC (0x01)
55 #define MV88E61XX_PORT_PAUSE_CONTROL (0x02)
56 #define MV88E61XX_PORT_REVISION (0x03)
57 #define MV88E61XX_PORT_CONTROL (0x04)
58 #define MV88E61XX_PORT_CONTROL2 (0x05)
59 #define MV88E61XX_PORT_VLAN_MAP (0x06)
60 #define MV88E61XX_PORT_VLAN (0x07)
61 #define MV88E61XX_PORT_FILTER (0x08)
62 #define MV88E61XX_PORT_EGRESS_CONTROL (0x09)
63 #define MV88E61XX_PORT_EGRESS_CONTROL2 (0x0a)
64 #define MV88E61XX_PORT_PORT_LEARN (0x0b)
65 #define MV88E61XX_PORT_ATU_CONTROL (0x0c)
66 #define MV88E61XX_PORT_PRIORITY_CONTROL (0x0d)
67 #define MV88E61XX_PORT_ETHER_PROTO (0x0f)
68 #define MV88E61XX_PORT_PROVIDER_PROTO (0x1a)
69 #define MV88E61XX_PORT_PRIORITY_MAP (0x18)
70 #define MV88E61XX_PORT_PRIORITY_MAP2 (0x19)
73 * Fields and values in each register.
75 #define MV88E61XX_PORT_STATUS_MEDIA (0x0300)
76 #define MV88E61XX_PORT_STATUS_MEDIA_10M (0x0000)
77 #define MV88E61XX_PORT_STATUS_MEDIA_100M (0x0100)
78 #define MV88E61XX_PORT_STATUS_MEDIA_1G (0x0200)
79 #define MV88E61XX_PORT_STATUS_DUPLEX (0x0400)
80 #define MV88E61XX_PORT_STATUS_LINK (0x0800)
81 #define MV88E61XX_PORT_STATUS_FC (0x8000)
83 #define MV88E61XX_PORT_CONTROL_DOUBLE_TAG (0x0200)
85 #define MV88E61XX_PORT_FILTER_MAP_DEST (0x0080)
86 #define MV88E61XX_PORT_FILTER_DISCARD_UNTAGGED (0x0100)
87 #define MV88E61XX_PORT_FILTER_DISCARD_TAGGED (0x0200)
88 #define MV88E61XX_PORT_FILTER_8021Q_MODE (0x0c00)
89 #define MV88E61XX_PORT_FILTER_8021Q_DISABLED (0x0000)
90 #define MV88E61XX_PORT_FILTER_8021Q_FALLBACK (0x0400)
91 #define MV88E61XX_PORT_FILTER_8021Q_CHECK (0x0800)
92 #define MV88E61XX_PORT_FILTER_8021Q_SECURE (0x0c00)
95 * Global address & global registers.
97 #define MV88E61XX_GLOBAL (0x1b)
99 #define MV88E61XX_GLOBAL_STATUS (0x00)
100 #define MV88E61XX_GLOBAL_CONTROL (0x04)
101 #define MV88E61XX_GLOBAL_VTU_OP (0x05)
102 #define MV88E61XX_GLOBAL_VTU_VID (0x06)
103 #define MV88E61XX_GLOBAL_VTU_DATA_P0P3 (0x07)
104 #define MV88E61XX_GLOBAL_VTU_DATA_P4P5 (0x08)
105 #define MV88E61XX_GLOBAL_ATU_CONTROL (0x0a)
106 #define MV88E61XX_GLOBAL_PRIORITY_MAP (0x18)
107 #define MV88E61XX_GLOBAL_MONITOR (0x1a)
108 #define MV88E61XX_GLOBAL_REMOTE_MGMT (0x1c)
109 #define MV88E61XX_GLOBAL_STATS (0x1d)
112 * Fields and values in each register.
114 #define MV88E61XX_GLOBAL_VTU_OP_BUSY (0x8000)
115 #define MV88E61XX_GLOBAL_VTU_OP_OP (0x7000)
116 #define MV88E61XX_GLOBAL_VTU_OP_OP_FLUSH (0x1000)
117 #define MV88E61XX_GLOBAL_VTU_OP_OP_VTU_LOAD (0x3000)
119 #define MV88E61XX_GLOBAL_VTU_VID_VALID (0x1000)
122 * Second global address & second global registers.
124 #define MV88E61XX_GLOBAL2 (0x1c)
126 #define MV88E61XX_GLOBAL2_MANAGE_2X (0x02)
127 #define MV88E61XX_GLOBAL2_MANAGE_0X (0x03)
128 #define MV88E61XX_GLOBAL2_CONTROL2 (0x05)
129 #define MV88E61XX_GLOBAL2_TRUNK_MASK (0x07)
130 #define MV88E61XX_GLOBAL2_TRUNK_MAP (0x08)
131 #define MV88E61XX_GLOBAL2_RATELIMIT (0x09)
132 #define MV88E61XX_GLOBAL2_VLAN_CONTROL (0x0b)
133 #define MV88E61XX_GLOBAL2_MAC_ADDRESS (0x0d)
136 * Fields and values in each register.
138 #define MV88E61XX_GLOBAL2_CONTROL2_DOUBLE_USE (0x8000)
139 #define MV88E61XX_GLOBAL2_CONTROL2_LOOP_PREVENT (0x4000)
140 #define MV88E61XX_GLOBAL2_CONTROL2_FLOW_MESSAGE (0x2000)
141 #define MV88E61XX_GLOBAL2_CONTROL2_FLOOD_BC (0x1000)
142 #define MV88E61XX_GLOBAL2_CONTROL2_REMOVE_PTAG (0x0800)
143 #define MV88E61XX_GLOBAL2_CONTROL2_AGE_INT (0x0400)
144 #define MV88E61XX_GLOBAL2_CONTROL2_FLOW_TAG (0x0200)
145 #define MV88E61XX_GLOBAL2_CONTROL2_ALWAYS_VTU (0x0100)
146 #define MV88E61XX_GLOBAL2_CONTROL2_FORCE_FC_PRI (0x0080)
147 #define MV88E61XX_GLOBAL2_CONTROL2_FC_PRI (0x0070)
148 #define MV88E61XX_GLOBAL2_CONTROL2_MGMT_TO_HOST (0x0008)
149 #define MV88E61XX_GLOBAL2_CONTROL2_MGMT_PRI (0x0007)
151 #endif /* !_MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ */