2 * Copyright (c) 2011, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * GPIO driver for Cavium Octeon
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
43 #include <sys/mutex.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
49 #include <contrib/octeon-sdk/cvmx.h>
50 #include <contrib/octeon-sdk/cvmx-gpio.h>
51 #include <mips/cavium/octeon_irq.h>
53 #include <mips/cavium/octeon_gpiovar.h>
54 #include <dev/gpio/gpiobusvar.h>
58 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
60 struct octeon_gpio_pin {
67 * on CAP100 GPIO 7 is "Factory defaults" button
70 static struct octeon_gpio_pin octeon_gpio_pins[] = {
71 { "F/D", 7, GPIO_PIN_INPUT},
78 static void octeon_gpio_pin_configure(struct octeon_gpio_softc *sc,
79 struct gpio_pin *pin, uint32_t flags);
84 static void octeon_gpio_identify(driver_t *, device_t);
85 static int octeon_gpio_probe(device_t dev);
86 static int octeon_gpio_attach(device_t dev);
87 static int octeon_gpio_detach(device_t dev);
88 static int octeon_gpio_filter(void *arg);
89 static void octeon_gpio_intr(void *arg);
94 static device_t octeon_gpio_get_bus(device_t);
95 static int octeon_gpio_pin_max(device_t dev, int *maxpin);
96 static int octeon_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
97 static int octeon_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
99 static int octeon_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
100 static int octeon_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
101 static int octeon_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
102 static int octeon_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
103 static int octeon_gpio_pin_toggle(device_t dev, uint32_t pin);
106 octeon_gpio_pin_configure(struct octeon_gpio_softc *sc, struct gpio_pin *pin,
110 cvmx_gpio_bit_cfgx_t gpio_cfgx;
112 mask = 1 << pin->gp_pin;
116 * Manage input/output
118 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
119 gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(pin->gp_pin));
120 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
121 if (flags & GPIO_PIN_OUTPUT) {
122 pin->gp_flags |= GPIO_PIN_OUTPUT;
123 gpio_cfgx.s.tx_oe = 1;
126 pin->gp_flags |= GPIO_PIN_INPUT;
127 gpio_cfgx.s.tx_oe = 0;
129 if (flags & GPIO_PIN_INVIN)
130 gpio_cfgx.s.rx_xor = 1;
132 gpio_cfgx.s.rx_xor = 0;
133 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(pin->gp_pin), gpio_cfgx.u64);
140 octeon_gpio_get_bus(device_t dev)
142 struct octeon_gpio_softc *sc;
144 sc = device_get_softc(dev);
150 octeon_gpio_pin_max(device_t dev, int *maxpin)
153 *maxpin = OCTEON_GPIO_PINS - 1;
158 octeon_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
160 struct octeon_gpio_softc *sc = device_get_softc(dev);
163 for (i = 0; i < sc->gpio_npins; i++) {
164 if (sc->gpio_pins[i].gp_pin == pin)
168 if (i >= sc->gpio_npins)
172 *caps = sc->gpio_pins[i].gp_caps;
179 octeon_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
181 struct octeon_gpio_softc *sc = device_get_softc(dev);
184 for (i = 0; i < sc->gpio_npins; i++) {
185 if (sc->gpio_pins[i].gp_pin == pin)
189 if (i >= sc->gpio_npins)
193 *flags = sc->gpio_pins[i].gp_flags;
200 octeon_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
202 struct octeon_gpio_softc *sc = device_get_softc(dev);
205 for (i = 0; i < sc->gpio_npins; i++) {
206 if (sc->gpio_pins[i].gp_pin == pin)
210 if (i >= sc->gpio_npins)
214 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
221 octeon_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
224 struct octeon_gpio_softc *sc = device_get_softc(dev);
226 for (i = 0; i < sc->gpio_npins; i++) {
227 if (sc->gpio_pins[i].gp_pin == pin)
231 if (i >= sc->gpio_npins)
234 octeon_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
240 octeon_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
242 struct octeon_gpio_softc *sc = device_get_softc(dev);
245 for (i = 0; i < sc->gpio_npins; i++) {
246 if (sc->gpio_pins[i].gp_pin == pin)
250 if (i >= sc->gpio_npins)
255 cvmx_gpio_set(1 << pin);
257 cvmx_gpio_clear(1 << pin);
264 octeon_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
266 struct octeon_gpio_softc *sc = device_get_softc(dev);
270 for (i = 0; i < sc->gpio_npins; i++) {
271 if (sc->gpio_pins[i].gp_pin == pin)
275 if (i >= sc->gpio_npins)
279 state = cvmx_gpio_read();
280 *val = (state & (1 << pin)) ? 1 : 0;
287 octeon_gpio_pin_toggle(device_t dev, uint32_t pin)
291 struct octeon_gpio_softc *sc = device_get_softc(dev);
293 for (i = 0; i < sc->gpio_npins; i++) {
294 if (sc->gpio_pins[i].gp_pin == pin)
298 if (i >= sc->gpio_npins)
303 * XXX: Need to check if read returns actual state of output
304 * pins or we need to keep this information by ourself
306 state = cvmx_gpio_read();
307 if (state & (1 << pin))
308 cvmx_gpio_clear(1 << pin);
310 cvmx_gpio_set(1 << pin);
317 octeon_gpio_filter(void *arg)
319 cvmx_gpio_bit_cfgx_t gpio_cfgx;
321 struct octeon_gpio_softc *sc = *cookie;
322 long int irq = (cookie - sc->gpio_intr_cookies);
324 if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS))
325 return (FILTER_STRAY);
327 gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(irq));
328 /* Clear rising edge detector */
329 if (gpio_cfgx.s.int_type == OCTEON_GPIO_IRQ_EDGE)
330 cvmx_gpio_interrupt_clear(1 << irq);
331 /* disable interrupt */
332 gpio_cfgx.s.int_en = 0;
333 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq), gpio_cfgx.u64);
335 return (FILTER_SCHEDULE_THREAD);
339 octeon_gpio_intr(void *arg)
341 cvmx_gpio_bit_cfgx_t gpio_cfgx;
343 struct octeon_gpio_softc *sc = *cookie;
344 long int irq = (cookie - sc->gpio_intr_cookies);
346 if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS)) {
347 printf("%s: invalid GPIO IRQ: %ld\n",
353 gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(irq));
354 /* disable interrupt */
355 gpio_cfgx.s.int_en = 1;
356 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq), gpio_cfgx.u64);
358 /* TODO: notify bus here or something */
359 printf("GPIO IRQ for pin %ld\n", irq);
364 octeon_gpio_identify(driver_t *drv, device_t parent)
367 BUS_ADD_CHILD(parent, 0, "gpio", 0);
371 octeon_gpio_probe(device_t dev)
374 device_set_desc(dev, "Cavium Octeon GPIO driver");
379 octeon_gpio_attach(device_t dev)
381 struct octeon_gpio_softc *sc = device_get_softc(dev);
382 struct octeon_gpio_pin *pinp;
383 cvmx_gpio_bit_cfgx_t gpio_cfgx;
387 KASSERT((device_get_unit(dev) == 0),
388 ("octeon_gpio: Only one gpio module supported"));
390 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
392 for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
393 if ((sc->gpio_irq_res[i] = bus_alloc_resource(dev,
394 SYS_RES_IRQ, &sc->gpio_irq_rid[i],
395 OCTEON_IRQ_GPIO0 + i, OCTEON_IRQ_GPIO0 + i, 1,
396 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
397 device_printf(dev, "unable to allocate IRQ resource\n");
398 octeon_gpio_detach(dev);
402 sc->gpio_intr_cookies[i] = sc;
403 if ((bus_setup_intr(dev, sc->gpio_irq_res[i], INTR_TYPE_MISC,
404 octeon_gpio_filter, octeon_gpio_intr,
405 &(sc->gpio_intr_cookies[i]), &sc->gpio_ih[i]))) {
407 "WARNING: unable to register interrupt handler\n");
408 octeon_gpio_detach(dev);
414 /* Configure all pins as input */
415 /* disable interrupts for all pins */
416 pinp = octeon_gpio_pins;
419 strncpy(sc->gpio_pins[i].gp_name, pinp->name, GPIOMAXNAME);
420 sc->gpio_pins[i].gp_pin = pinp->pin;
421 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
422 sc->gpio_pins[i].gp_flags = 0;
423 octeon_gpio_pin_configure(sc, &sc->gpio_pins[i], pinp->flags);
432 * Sample: how to enable edge-triggered interrupt
435 gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(7));
436 gpio_cfgx.s.int_en = 1;
437 gpio_cfgx.s.int_type = OCTEON_GPIO_IRQ_EDGE;
438 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(7), gpio_cfgx.u64);
442 for (i = 0; i < 16; i++) {
443 gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(i));
444 device_printf(dev, "[pin%d] output=%d, invinput=%d, intr=%d, intr_type=%s\n",
445 i, gpio_cfgx.s.tx_oe, gpio_cfgx.s.rx_xor,
446 gpio_cfgx.s.int_en, gpio_cfgx.s.int_type ? "rising edge" : "level");
449 sc->busdev = gpiobus_attach_bus(dev);
450 if (sc->busdev == NULL) {
451 octeon_gpio_detach(dev);
459 octeon_gpio_detach(device_t dev)
461 struct octeon_gpio_softc *sc = device_get_softc(dev);
464 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
466 for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
468 bus_teardown_intr(dev, sc->gpio_irq_res[i],
470 if (sc->gpio_irq_res[i])
471 bus_release_resource(dev, SYS_RES_IRQ,
472 sc->gpio_irq_rid[i], sc->gpio_irq_res[i]);
474 gpiobus_detach_bus(dev);
475 mtx_destroy(&sc->gpio_mtx);
480 static device_method_t octeon_gpio_methods[] = {
481 DEVMETHOD(device_identify, octeon_gpio_identify),
482 DEVMETHOD(device_probe, octeon_gpio_probe),
483 DEVMETHOD(device_attach, octeon_gpio_attach),
484 DEVMETHOD(device_detach, octeon_gpio_detach),
487 DEVMETHOD(gpio_get_bus, octeon_gpio_get_bus),
488 DEVMETHOD(gpio_pin_max, octeon_gpio_pin_max),
489 DEVMETHOD(gpio_pin_getname, octeon_gpio_pin_getname),
490 DEVMETHOD(gpio_pin_getflags, octeon_gpio_pin_getflags),
491 DEVMETHOD(gpio_pin_getcaps, octeon_gpio_pin_getcaps),
492 DEVMETHOD(gpio_pin_setflags, octeon_gpio_pin_setflags),
493 DEVMETHOD(gpio_pin_get, octeon_gpio_pin_get),
494 DEVMETHOD(gpio_pin_set, octeon_gpio_pin_set),
495 DEVMETHOD(gpio_pin_toggle, octeon_gpio_pin_toggle),
499 static driver_t octeon_gpio_driver = {
502 sizeof(struct octeon_gpio_softc),
504 static devclass_t octeon_gpio_devclass;
506 DRIVER_MODULE(octeon_gpio, ciu, octeon_gpio_driver, octeon_gpio_devclass, 0, 0);