2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
33 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <machine/hwfunc.h>
38 #include <machine/md_var.h>
39 #include <machine/smp.h>
41 #include <mips/cavium/octeon_pcmap_regs.h>
43 #include <contrib/octeon-sdk/cvmx.h>
44 #include <contrib/octeon-sdk/cvmx-interrupt.h>
47 extern cvmx_bootinfo_t *octeon_bootinfo;
49 /* NOTE: this 64-bit mask (and many others) limits MAXCPU to 64 */
50 uint64_t octeon_ap_boot = ~0ULL;
53 platform_ipi_send(int cpuid)
55 cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
60 platform_ipi_clear(void)
64 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
65 KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
66 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
70 platform_ipi_intrnum(void)
76 platform_init_ap(int cpuid)
78 unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
81 * Set the exception base.
83 mips_wr_ebase(0x80000000);
86 * Clear any pending IPIs.
88 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
96 * Unmask the clock, ipi and ciu interrupts.
98 ciu_int_mask = hard_int_mask(0);
99 clock_int_mask = hard_int_mask(5);
100 ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
101 set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
107 platform_cpu_mask(cpuset_t *mask)
109 uint64_t core_mask = octeon_bootinfo->core_mask;
113 for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1)
119 platform_smp_topo(void)
121 return (smp_topo_none());
125 platform_start_ap(int cpuid)
127 uint64_t cores_in_reset;
130 * Release the core if it is in reset, and let it rev up a bit.
131 * The real synchronization happens below via octeon_ap_boot.
133 cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST);
134 if (cores_in_reset & (1ULL << cpuid)) {
136 printf ("AP #%d still in reset\n", cpuid);
137 cores_in_reset &= ~(1ULL << cpuid);
138 cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
139 DELAY(2000); /* Give it a moment to start */
142 if (atomic_cmpset_64(&octeon_ap_boot, ~0, cpuid) == 0)
146 if (atomic_cmpset_64(&octeon_ap_boot, 0, ~0) != 0)
148 printf("Waiting for cpu%d to start\n", cpuid);