2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Juli Mallett <jmallett@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/reboot.h>
42 #include <contrib/octeon-sdk/cvmx.h>
43 #include <contrib/octeon-sdk/cvmx-bootmem.h>
44 #include <contrib/octeon-sdk/cvmx-interrupt.h>
45 #include <contrib/octeon-sdk/octeon-pci-console.h>
47 #ifdef OCTEON_VENDOR_RADISYS
48 #define OPCIC_FLAG_RSYS (0x00000001)
50 #define OPCIC_RSYS_FIFO_SIZE (0x2000)
55 uint64_t sc_base_addr;
58 static struct opcic_softc opcic_instance;
60 static cn_probe_t opcic_cnprobe;
61 static cn_init_t opcic_cninit;
62 static cn_term_t opcic_cnterm;
63 static cn_getc_t opcic_cngetc;
64 static cn_putc_t opcic_cnputc;
65 static cn_grab_t opcic_cngrab;
66 static cn_ungrab_t opcic_cnungrab;
68 #ifdef OCTEON_VENDOR_RADISYS
69 static int opcic_rsys_cngetc(struct opcic_softc *);
70 static void opcic_rsys_cnputc(struct opcic_softc *, int);
73 CONSOLE_DRIVER(opcic);
76 opcic_cnprobe(struct consdev *cp)
78 const struct cvmx_bootmem_named_block_desc *pci_console_block;
79 struct opcic_softc *sc;
87 switch (cvmx_sysinfo_get()->board_type) {
88 #ifdef OCTEON_VENDOR_RADISYS
89 case CVMX_BOARD_TYPE_CUST_RADISYS_RSYS4GBE:
91 cvmx_bootmem_find_named_block("rsys_gbl_memory");
92 if (pci_console_block != NULL) {
93 sc->sc_flags |= OPCIC_FLAG_RSYS;
94 sc->sc_base_addr = pci_console_block->base_addr;
100 cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
101 if (pci_console_block == NULL)
103 sc->sc_base_addr = pci_console_block->base_addr;
108 snprintf(cp->cn_name, sizeof cp->cn_name, "opcic@%p", cp->cn_arg);
109 cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL;
113 opcic_cninit(struct consdev *cp)
119 opcic_cnterm(struct consdev *cp)
125 opcic_cngetc(struct consdev *cp)
127 struct opcic_softc *sc;
133 #ifdef OCTEON_VENDOR_RADISYS
134 if ((sc->sc_flags & OPCIC_FLAG_RSYS) != 0)
135 return (opcic_rsys_cngetc(sc));
138 rv = octeon_pci_console_read(sc->sc_base_addr, 0, &ch, 1,
139 OCT_PCI_CON_FLAG_NONBLOCK);
146 opcic_cnputc(struct consdev *cp, int c)
148 struct opcic_softc *sc;
155 #ifdef OCTEON_VENDOR_RADISYS
156 if ((sc->sc_flags & OPCIC_FLAG_RSYS) != 0) {
157 opcic_rsys_cnputc(sc, c);
162 rv = octeon_pci_console_write(sc->sc_base_addr, 0, &ch, 1, 0);
164 panic("%s: octeon_pci_console_write failed.", __func__);
168 opcic_cngrab(struct consdev *cp)
174 opcic_cnungrab(struct consdev *cp)
179 #ifdef OCTEON_VENDOR_RADISYS
181 opcic_rsys_cngetc(struct opcic_softc *sc)
184 uint64_t console_base;
185 uint64_t console_rbuf;
186 uint64_t console_rcnt[2];
191 gbl_base = CVMX_ADD_IO_SEG(sc->sc_base_addr);
192 console_base = gbl_base + 0x10;
194 console_rbuf = console_base + 0x2018;
195 console_rcnt[0] = console_base + 0x08;
196 console_rcnt[1] = console_base + 0x0a;
198 /* Check if there is anything new in the FIFO. */
199 rcnt[0] = cvmx_read64_uint16(console_rcnt[0]);
200 rcnt[1] = cvmx_read64_uint16(console_rcnt[1]);
201 if (rcnt[0] == rcnt[1])
204 /* Get first new character in the FIFO. */
208 roff = OPCIC_RSYS_FIFO_SIZE - 1;
209 c = cvmx_read64_uint8(console_rbuf + roff);
212 rcnt[1] = (rcnt[1] + 1) % OPCIC_RSYS_FIFO_SIZE;
213 cvmx_write64_uint16(console_rcnt[1], rcnt[1]);
219 opcic_rsys_cnputc(struct opcic_softc *sc, int c)
222 uint64_t console_base;
223 uint64_t console_wbuf;
224 uint64_t console_wcnt;
227 gbl_base = CVMX_ADD_IO_SEG(sc->sc_base_addr);
228 console_base = gbl_base + 0x10;
230 console_wbuf = console_base + 0x0018;
231 console_wcnt = console_base + 0x0c;
233 /* Append character to FIFO. */
234 wcnt = cvmx_read64_uint16(console_wcnt) % OPCIC_RSYS_FIFO_SIZE;
235 cvmx_write64_uint8(console_wbuf + wcnt, (uint8_t)c);
236 cvmx_write64_uint16(console_wcnt, wcnt + 1);