2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010-2011 Juli Mallett <jmallett@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/endian.h>
39 #include <sys/interrupt.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
47 #include <vm/vm_extern.h>
49 #include <machine/bus.h>
50 #include <machine/cpu.h>
52 #include <contrib/octeon-sdk/cvmx.h>
53 #include <mips/cavium/octeon_irq.h>
54 #include <contrib/octeon-sdk/cvmx-pcie.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
59 #include <dev/pci/pcib_private.h>
61 #include <mips/cavium/octopcireg.h>
62 #include <mips/cavium/octopcivar.h>
66 #define NPI_WRITE(addr, value) cvmx_write64_uint32((addr) ^ 4, (value))
67 #define NPI_READ(addr) cvmx_read64_uint32((addr) ^ 4)
69 struct octopci_softc {
75 bus_addr_t sc_io_base;
79 bus_addr_t sc_mem1_base;
80 unsigned sc_mem1_next;
84 static void octopci_identify(driver_t *, device_t);
85 static int octopci_probe(device_t);
86 static int octopci_attach(device_t);
87 static int octopci_read_ivar(device_t, device_t, int,
89 static struct resource *octopci_alloc_resource(device_t, device_t, int, int *,
90 rman_res_t, rman_res_t,
92 static int octopci_activate_resource(device_t, device_t, int, int,
94 static int octopci_maxslots(device_t);
95 static uint32_t octopci_read_config(device_t, u_int, u_int, u_int, u_int, int);
96 static void octopci_write_config(device_t, u_int, u_int, u_int, u_int,
98 static int octopci_route_interrupt(device_t, device_t, int);
100 static unsigned octopci_init_bar(device_t, unsigned, unsigned, unsigned, unsigned, uint8_t *);
101 static unsigned octopci_init_device(device_t, unsigned, unsigned, unsigned, unsigned);
102 static unsigned octopci_init_bus(device_t, unsigned);
103 static void octopci_init_pci(device_t);
104 static uint64_t octopci_cs_addr(unsigned, unsigned, unsigned, unsigned);
107 octopci_identify(driver_t *drv, device_t parent)
109 BUS_ADD_CHILD(parent, 0, "pcib", 0);
110 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
111 BUS_ADD_CHILD(parent, 0, "pcib", 1);
115 octopci_probe(device_t dev)
117 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
118 device_set_desc(dev, "Cavium Octeon PCIe bridge");
122 /* Check whether we are a PCI host. */
123 if ((cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST) == 0)
126 if (device_get_unit(dev) != 0)
129 device_set_desc(dev, "Cavium Octeon PCI bridge");
134 octopci_attach(device_t dev)
136 struct octopci_softc *sc;
140 sc = device_get_softc(dev);
143 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
144 sc->sc_domain = device_get_unit(dev);
146 error = cvmx_pcie_rc_initialize(sc->sc_domain);
148 device_printf(dev, "Failed to put PCIe bus in host mode.\n");
153 * In RC mode, the Simple Executive programs the first bus to
154 * be numbered as bus 1, because some IDT bridges used in
155 * Octeon systems object to being attached to bus 0.
159 sc->sc_io_base = CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(sc->sc_domain));
160 sc->sc_io.rm_descr = "Cavium Octeon PCIe I/O Ports";
162 sc->sc_mem1_base = CVMX_ADD_IO_SEG(cvmx_pcie_get_mem_base_address(sc->sc_domain));
163 sc->sc_mem1.rm_descr = "Cavium Octeon PCIe Memory";
165 octopci_init_pci(dev);
170 sc->sc_io_base = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI, CVMX_OCT_SUBDID_PCI_IO));
171 sc->sc_io.rm_descr = "Cavium Octeon PCI I/O Ports";
173 sc->sc_mem1_base = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI, CVMX_OCT_SUBDID_PCI_MEM1));
174 sc->sc_mem1.rm_descr = "Cavium Octeon PCI Memory";
177 sc->sc_io.rm_type = RMAN_ARRAY;
178 error = rman_init(&sc->sc_io);
182 error = rman_manage_region(&sc->sc_io, CVMX_OCT_PCI_IO_BASE,
183 CVMX_OCT_PCI_IO_BASE + CVMX_OCT_PCI_IO_SIZE);
187 sc->sc_mem1.rm_type = RMAN_ARRAY;
188 error = rman_init(&sc->sc_mem1);
192 error = rman_manage_region(&sc->sc_mem1, CVMX_OCT_PCI_MEM1_BASE,
193 CVMX_OCT_PCI_MEM1_BASE + CVMX_OCT_PCI_MEM1_SIZE);
198 * Next offsets for resource allocation in octopci_init_bar.
201 sc->sc_mem1_next = 0;
206 octopci_write_config(dev, sc->sc_bus, 0, 0, PCIR_SUBBUS_1, 0xff, 1);
207 subbus = octopci_init_bus(dev, sc->sc_bus);
208 octopci_write_config(dev, sc->sc_bus, 0, 0, PCIR_SUBBUS_1, subbus, 1);
210 device_add_child(dev, "pci", -1);
212 return (bus_generic_attach(dev));
216 octopci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
218 struct octopci_softc *sc;
220 sc = device_get_softc(dev);
223 case PCIB_IVAR_DOMAIN:
224 *result = sc->sc_domain;
227 *result = sc->sc_bus;
234 static struct resource *
235 octopci_alloc_resource(device_t bus, device_t child, int type, int *rid,
236 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
238 struct octopci_softc *sc;
239 struct resource *res;
243 sc = device_get_softc(bus);
247 res = bus_generic_alloc_resource(bus, child, type, rid, start,
262 res = rman_reserve_resource(rm, start, end, count, flags, child);
266 rman_set_rid(res, *rid);
267 rman_set_bustag(res, octopci_bus_space);
271 rman_set_bushandle(res, sc->sc_mem1_base + rman_get_start(res));
274 rman_set_bushandle(res, sc->sc_io_base + rman_get_start(res));
276 rman_set_virtual(res, (void *)rman_get_bushandle(res));
280 * We can't access ports via a 32-bit pointer.
282 rman_set_virtual(res, NULL);
287 if ((flags & RF_ACTIVE) != 0) {
288 error = bus_activate_resource(child, type, *rid, res);
290 rman_release_resource(res);
299 octopci_activate_resource(device_t bus, device_t child, int type, int rid,
300 struct resource *res)
302 bus_space_handle_t bh;
307 error = bus_generic_activate_resource(bus, child, type, rid,
314 error = bus_space_map(rman_get_bustag(res),
315 rman_get_bushandle(res), rman_get_size(res), 0, &bh);
318 rman_set_bushandle(res, bh);
324 error = rman_activate_resource(res);
331 octopci_maxslots(device_t dev)
333 return (PCI_SLOTMAX);
337 octopci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
340 struct octopci_softc *sc;
344 sc = device_get_softc(dev);
346 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
347 if (bus == 0 && slot == 0 && func == 0)
348 return ((uint32_t)-1);
352 return (cvmx_pcie_config_read32(sc->sc_domain, bus, slot, func, reg));
354 return (cvmx_pcie_config_read16(sc->sc_domain, bus, slot, func, reg));
356 return (cvmx_pcie_config_read8(sc->sc_domain, bus, slot, func, reg));
358 return ((uint32_t)-1);
362 addr = octopci_cs_addr(bus, slot, func, reg);
366 data = le32toh(cvmx_read64_uint32(addr));
369 data = le16toh(cvmx_read64_uint16(addr));
372 data = cvmx_read64_uint8(addr);
375 return ((uint32_t)-1);
380 octopci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
381 u_int reg, uint32_t data, int bytes)
383 struct octopci_softc *sc;
386 sc = device_get_softc(dev);
388 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
391 cvmx_pcie_config_write32(sc->sc_domain, bus, slot, func, reg, data);
394 cvmx_pcie_config_write16(sc->sc_domain, bus, slot, func, reg, data);
397 cvmx_pcie_config_write8(sc->sc_domain, bus, slot, func, reg, data);
404 addr = octopci_cs_addr(bus, slot, func, reg);
408 cvmx_write64_uint32(addr, htole32(data));
411 cvmx_write64_uint16(addr, htole16(data));
414 cvmx_write64_uint8(addr, data);
422 octopci_route_interrupt(device_t dev, device_t child, int pin)
424 struct octopci_softc *sc;
425 unsigned bus, slot, func;
428 sc = device_get_softc(dev);
430 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
431 return (OCTEON_IRQ_PCI_INT0 + pin - 1);
433 bus = pci_get_bus(child);
434 slot = pci_get_slot(child);
435 func = pci_get_function(child);
438 * Board types we have to know at compile-time.
440 #if defined(OCTEON_BOARD_CAPK_0100ND)
441 if (bus == 0 && slot == 12 && func == 0)
442 return (OCTEON_IRQ_PCI_INT2);
446 * For board types we can determine at runtime.
448 switch (cvmx_sysinfo_get()->board_type) {
449 #if defined(OCTEON_VENDOR_LANNER)
450 case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
451 return (OCTEON_IRQ_PCI_INT0 + pin - 1);
452 case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
454 if (slot == 3 || slot == 9)
458 return (OCTEON_IRQ_PCI_INT0 + (irq & 3));
466 irq = slot + pin - 3;
468 return (OCTEON_IRQ_PCI_INT0 + (irq & 3));
472 octopci_init_bar(device_t dev, unsigned b, unsigned s, unsigned f, unsigned barnum, uint8_t *commandp)
474 struct octopci_softc *sc;
479 sc = device_get_softc(dev);
481 octopci_write_config(dev, b, s, f, PCIR_BAR(barnum), 0xffffffff, 4);
482 bar = octopci_read_config(dev, b, s, f, PCIR_BAR(barnum), 4);
485 /* Bar not implemented; got to next bar. */
489 if (PCI_BAR_IO(bar)) {
490 size = ~(bar & PCIM_BAR_IO_BASE) + 1;
492 sc->sc_io_next = roundup2(sc->sc_io_next, size);
493 if (sc->sc_io_next + size > CVMX_OCT_PCI_IO_SIZE) {
494 device_printf(dev, "%02x.%02x:%02x: no ports for BAR%u.\n",
498 octopci_write_config(dev, b, s, f, PCIR_BAR(barnum),
499 CVMX_OCT_PCI_IO_BASE + sc->sc_io_next, 4);
500 sc->sc_io_next += size;
505 *commandp |= PCIM_CMD_PORTEN;
509 if (PCIR_BAR(barnum) == PCIR_BIOS) {
511 * ROM BAR is always 32-bit.
515 switch (bar & PCIM_BAR_MEM_TYPE) {
516 case PCIM_BAR_MEM_64:
519 * High 32 bits are all zeroes for now.
521 octopci_write_config(dev, b, s, f, PCIR_BAR(barnum + 1), 0, 4);
530 size = ~(bar & (uint32_t)PCIM_BAR_MEM_BASE) + 1;
532 sc->sc_mem1_next = roundup2(sc->sc_mem1_next, size);
533 if (sc->sc_mem1_next + size > CVMX_OCT_PCI_MEM1_SIZE) {
534 device_printf(dev, "%02x.%02x:%02x: no memory for BAR%u.\n",
536 return (barnum + barsize);
538 octopci_write_config(dev, b, s, f, PCIR_BAR(barnum),
539 CVMX_OCT_PCI_MEM1_BASE + sc->sc_mem1_next, 4);
540 sc->sc_mem1_next += size;
543 * Enable memory access.
545 *commandp |= PCIM_CMD_MEMEN;
547 return (barnum + barsize);
552 octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned secbus)
554 unsigned barnum, bars;
556 uint8_t class, subclass;
560 /* Read header type (again.) */
561 hdrtype = octopci_read_config(dev, b, s, f, PCIR_HDRTYPE, 1);
564 * Disable memory and I/O while programming BARs.
566 command = octopci_read_config(dev, b, s, f, PCIR_COMMAND, 1);
567 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
568 octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
573 switch (hdrtype & PCIM_HDRTYPE) {
574 case PCIM_HDRTYPE_NORMAL:
577 case PCIM_HDRTYPE_BRIDGE:
580 case PCIM_HDRTYPE_CARDBUS:
584 device_printf(dev, "%02x.%02x:%02x: invalid header type %#x\n",
590 while (barnum < bars)
591 barnum = octopci_init_bar(dev, b, s, f, barnum, &command);
593 /* Enable bus mastering. */
594 command |= PCIM_CMD_BUSMASTEREN;
596 /* Enable whatever facilities the BARs require. */
597 octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
602 * Set cache line size. On Octeon it should be 128 bytes,
603 * but according to Linux some Intel bridges have trouble
604 * with values over 64 bytes, so use 64 bytes.
606 octopci_write_config(dev, b, s, f, PCIR_CACHELNSZ, 16, 1);
608 /* Set latency timer. */
609 octopci_write_config(dev, b, s, f, PCIR_LATTIMER, 48, 1);
611 /* Board-specific or device-specific fixups and workarounds. */
612 switch (cvmx_sysinfo_get()->board_type) {
613 #if defined(OCTEON_VENDOR_LANNER)
614 case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
615 if (b == 1 && s == 7 && f == 0) {
616 bus_addr_t busaddr, unitbusaddr;
624 bar = octopci_read_config(dev, b, s, f,
626 busaddr = CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_PCI,
627 CVMX_OCT_SUBDID_PCI_MEM1));
628 busaddr += (bar & (uint32_t)PCIM_BAR_MEM_BASE);
629 for (unit = 0; unit < 4; unit++) {
630 unitbusaddr = busaddr + 0x430 + (unit << 8);
631 tmp = le32toh(cvmx_read64_uint32(unitbusaddr));
634 cvmx_write64_uint32(unitbusaddr, htole32(tmp));
643 /* Configure PCI-PCI bridges. */
644 class = octopci_read_config(dev, b, s, f, PCIR_CLASS, 1);
645 if (class != PCIC_BRIDGE)
648 subclass = octopci_read_config(dev, b, s, f, PCIR_SUBCLASS, 1);
649 if (subclass != PCIS_BRIDGE_PCI)
652 /* Enable memory and I/O access. */
653 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
654 octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
656 /* Enable errors and parity checking. Do a bus reset. */
657 brctl = octopci_read_config(dev, b, s, f, PCIR_BRIDGECTL_1, 1);
658 brctl |= PCIB_BCR_PERR_ENABLE | PCIB_BCR_SERR_ENABLE;
660 /* Perform a secondary bus reset. */
661 brctl |= PCIB_BCR_SECBUS_RESET;
662 octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
664 brctl &= ~PCIB_BCR_SECBUS_RESET;
665 octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
669 /* Program memory and I/O ranges. */
670 octopci_write_config(dev, b, s, f, PCIR_MEMBASE_1,
671 CVMX_OCT_PCI_MEM1_BASE >> 16, 2);
672 octopci_write_config(dev, b, s, f, PCIR_MEMLIMIT_1,
673 (CVMX_OCT_PCI_MEM1_BASE + CVMX_OCT_PCI_MEM1_SIZE - 1) >> 16, 2);
675 octopci_write_config(dev, b, s, f, PCIR_IOBASEL_1,
676 CVMX_OCT_PCI_IO_BASE >> 8, 1);
677 octopci_write_config(dev, b, s, f, PCIR_IOBASEH_1,
678 CVMX_OCT_PCI_IO_BASE >> 16, 2);
680 octopci_write_config(dev, b, s, f, PCIR_IOLIMITL_1,
681 (CVMX_OCT_PCI_IO_BASE + CVMX_OCT_PCI_IO_SIZE - 1) >> 8, 1);
682 octopci_write_config(dev, b, s, f, PCIR_IOLIMITH_1,
683 (CVMX_OCT_PCI_IO_BASE + CVMX_OCT_PCI_IO_SIZE - 1) >> 16, 2);
685 /* Program prefetchable memory decoder. */
688 /* Probe secondary/subordinate buses. */
689 octopci_write_config(dev, b, s, f, PCIR_PRIBUS_1, b, 1);
690 octopci_write_config(dev, b, s, f, PCIR_SECBUS_1, secbus, 1);
691 octopci_write_config(dev, b, s, f, PCIR_SUBBUS_1, 0xff, 1);
693 /* Perform a secondary bus reset. */
694 brctl |= PCIB_BCR_SECBUS_RESET;
695 octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
697 brctl &= ~PCIB_BCR_SECBUS_RESET;
698 octopci_write_config(dev, b, s, f, PCIR_BRIDGECTL_1, brctl, 1);
700 /* Give the bus time to settle now before reading configspace. */
703 secbus = octopci_init_bus(dev, secbus);
705 octopci_write_config(dev, b, s, f, PCIR_SUBBUS_1, secbus, 1);
711 octopci_init_bus(device_t dev, unsigned b)
719 for (s = 0; s <= PCI_SLOTMAX; s++) {
720 for (f = 0; f <= PCI_FUNCMAX; f++) {
721 hdrtype = octopci_read_config(dev, b, s, f, PCIR_HDRTYPE, 1);
723 if (hdrtype == 0xff) {
725 break; /* Next slot. */
726 continue; /* Next function. */
729 secbus = octopci_init_device(dev, b, s, f, secbus);
731 if (f == 0 && (hdrtype & PCIM_MFDEV) == 0)
732 break; /* Next slot. */
740 octopci_cs_addr(unsigned bus, unsigned slot, unsigned func, unsigned reg)
742 octeon_pci_config_space_address_t pci_addr;
745 pci_addr.s.upper = 2;
748 pci_addr.s.subdid = CVMX_OCT_SUBDID_PCI_CFG;
749 pci_addr.s.endian_swap = 1;
750 pci_addr.s.bus = bus;
751 pci_addr.s.dev = slot;
752 pci_addr.s.func = func;
753 pci_addr.s.reg = reg;
755 return (pci_addr.u64);
759 octopci_init_pci(device_t dev)
761 cvmx_npi_mem_access_subid_t npi_mem_access_subid;
762 cvmx_npi_pci_int_arb_cfg_t npi_pci_int_arb_cfg;
763 cvmx_npi_ctl_status_t npi_ctl_status;
764 cvmx_pci_ctl_status_2_t pci_ctl_status_2;
765 cvmx_pci_cfg56_t pci_cfg56;
766 cvmx_pci_cfg22_t pci_cfg22;
767 cvmx_pci_cfg16_t pci_cfg16;
768 cvmx_pci_cfg19_t pci_cfg19;
769 cvmx_pci_cfg01_t pci_cfg01;
775 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
776 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
780 npi_ctl_status.u64 = 0;
781 npi_ctl_status.s.max_word = 1;
782 npi_ctl_status.s.timer = 1;
783 cvmx_write_csr(CVMX_NPI_CTL_STATUS, npi_ctl_status.u64);
788 switch (cvmx_sysinfo_get()->board_type) {
789 #if defined(OCTEON_VENDOR_LANNER)
790 case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
791 case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
793 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x0);
798 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
801 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
806 * Enable BARs and configure big BAR mode.
808 pci_ctl_status_2.u32 = 0;
809 pci_ctl_status_2.s.bb1_hole = 5; /* 256MB hole in BAR1 */
810 pci_ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
811 pci_ctl_status_2.s.bb_ca = 1; /* Bypass cache for big BAR */
812 pci_ctl_status_2.s.bb_es = 1; /* Do big BAR byte-swapping */
813 pci_ctl_status_2.s.bb1 = 1; /* BAR1 is big */
814 pci_ctl_status_2.s.bb0 = 1; /* BAR0 is big */
815 pci_ctl_status_2.s.bar2pres = 1; /* BAR2 present */
816 pci_ctl_status_2.s.pmo_amod = 1; /* Round-robin priority */
817 pci_ctl_status_2.s.tsr_hwm = 1;
818 pci_ctl_status_2.s.bar2_enb = 1; /* Enable BAR2 */
819 pci_ctl_status_2.s.bar2_esx = 1; /* Do BAR2 byte-swapping */
820 pci_ctl_status_2.s.bar2_cax = 1; /* Bypass cache for BAR2 */
822 NPI_WRITE(CVMX_NPI_PCI_CTL_STATUS_2, pci_ctl_status_2.u32);
826 pci_ctl_status_2.u32 = NPI_READ(CVMX_NPI_PCI_CTL_STATUS_2);
828 device_printf(dev, "%u-bit PCI%s bus.\n",
829 pci_ctl_status_2.s.ap_64ad ? 64 : 32,
830 pci_ctl_status_2.s.ap_pcix ? "-X" : "");
833 * Set up transaction splitting, etc., parameters.
836 pci_cfg19.s.mrbcm = 1;
837 if (pci_ctl_status_2.s.ap_pcix) {
838 pci_cfg19.s.mdrrmc = 0;
839 pci_cfg19.s.tdomc = 4;
841 pci_cfg19.s.mdrrmc = 2;
842 pci_cfg19.s.tdomc = 1;
844 NPI_WRITE(CVMX_NPI_PCI_CFG19, pci_cfg19.u32);
845 NPI_READ(CVMX_NPI_PCI_CFG19);
848 * Set up PCI error handling and memory access.
851 pci_cfg01.s.fbbe = 1;
855 pci_cfg01.s.msae = 1;
856 if (pci_ctl_status_2.s.ap_pcix) {
861 NPI_WRITE(CVMX_NPI_PCI_CFG01, pci_cfg01.u32);
862 NPI_READ(CVMX_NPI_PCI_CFG01);
865 * Enable the Octeon bus arbiter.
867 npi_pci_int_arb_cfg.u64 = 0;
868 npi_pci_int_arb_cfg.s.en = 1;
869 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, npi_pci_int_arb_cfg.u64);
872 * Disable master latency timer.
875 pci_cfg16.s.mltd = 1;
876 NPI_WRITE(CVMX_NPI_PCI_CFG16, pci_cfg16.u32);
877 NPI_READ(CVMX_NPI_PCI_CFG16);
880 * Configure master arbiter.
883 pci_cfg22.s.flush = 1;
884 pci_cfg22.s.mrv = 255;
885 NPI_WRITE(CVMX_NPI_PCI_CFG22, pci_cfg22.u32);
886 NPI_READ(CVMX_NPI_PCI_CFG22);
889 * Set up PCI-X capabilities.
891 if (pci_ctl_status_2.s.ap_pcix) {
893 pci_cfg56.s.most = 3;
894 pci_cfg56.s.roe = 1; /* Enable relaxed ordering */
895 pci_cfg56.s.dpere = 1;
896 pci_cfg56.s.ncp = 0xe8;
897 pci_cfg56.s.pxcid = 7;
898 NPI_WRITE(CVMX_NPI_PCI_CFG56, pci_cfg56.u32);
899 NPI_READ(CVMX_NPI_PCI_CFG56);
902 NPI_WRITE(CVMX_NPI_PCI_READ_CMD_6, 0x22);
903 NPI_READ(CVMX_NPI_PCI_READ_CMD_6);
904 NPI_WRITE(CVMX_NPI_PCI_READ_CMD_C, 0x33);
905 NPI_READ(CVMX_NPI_PCI_READ_CMD_C);
906 NPI_WRITE(CVMX_NPI_PCI_READ_CMD_E, 0x33);
907 NPI_READ(CVMX_NPI_PCI_READ_CMD_E);
910 * Configure MEM1 sub-DID access.
912 npi_mem_access_subid.u64 = 0;
913 npi_mem_access_subid.s.esr = 1; /* Byte-swap on read */
914 npi_mem_access_subid.s.esw = 1; /* Byte-swap on write */
915 switch (cvmx_sysinfo_get()->board_type) {
916 #if defined(OCTEON_VENDOR_LANNER)
917 case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
918 npi_mem_access_subid.s.shortl = 1;
924 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, npi_mem_access_subid.u64);
927 * Configure BAR2. Linux says this has to come first.
929 NPI_WRITE(CVMX_NPI_PCI_CFG08, 0x00000000);
930 NPI_READ(CVMX_NPI_PCI_CFG08);
931 NPI_WRITE(CVMX_NPI_PCI_CFG09, 0x00000080);
932 NPI_READ(CVMX_NPI_PCI_CFG09);
935 * Disable BAR1 IndexX.
937 for (i = 0; i < 32; i++) {
938 NPI_WRITE(CVMX_NPI_PCI_BAR1_INDEXX(i), 0);
939 NPI_READ(CVMX_NPI_PCI_BAR1_INDEXX(i));
943 * Configure BAR0 and BAR1.
945 NPI_WRITE(CVMX_NPI_PCI_CFG04, 0x00000000);
946 NPI_READ(CVMX_NPI_PCI_CFG04);
947 NPI_WRITE(CVMX_NPI_PCI_CFG05, 0x00000000);
948 NPI_READ(CVMX_NPI_PCI_CFG05);
950 NPI_WRITE(CVMX_NPI_PCI_CFG06, 0x80000000);
951 NPI_READ(CVMX_NPI_PCI_CFG06);
952 NPI_WRITE(CVMX_NPI_PCI_CFG07, 0x00000000);
953 NPI_READ(CVMX_NPI_PCI_CFG07);
956 * Clear PCI interrupts.
958 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, 0xffffffffffffffffull);
961 static device_method_t octopci_methods[] = {
962 /* Device interface */
963 DEVMETHOD(device_identify, octopci_identify),
964 DEVMETHOD(device_probe, octopci_probe),
965 DEVMETHOD(device_attach, octopci_attach),
968 DEVMETHOD(bus_read_ivar, octopci_read_ivar),
969 DEVMETHOD(bus_alloc_resource, octopci_alloc_resource),
970 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
971 DEVMETHOD(bus_activate_resource,octopci_activate_resource),
972 DEVMETHOD(bus_deactivate_resource,bus_generic_deactivate_resource),
973 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
974 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
976 DEVMETHOD(bus_add_child, bus_generic_add_child),
979 DEVMETHOD(pcib_maxslots, octopci_maxslots),
980 DEVMETHOD(pcib_read_config, octopci_read_config),
981 DEVMETHOD(pcib_write_config, octopci_write_config),
982 DEVMETHOD(pcib_route_interrupt, octopci_route_interrupt),
983 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
988 static driver_t octopci_driver = {
991 sizeof(struct octopci_softc),
993 static devclass_t octopci_devclass;
994 DRIVER_MODULE(octopci, ciu, octopci_driver, octopci_devclass, 0, 0);