1 /***********************license start************************************
2 * Copyright (c) 2005-2007 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
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14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
37 ***********************license end**************************************/
40 #ifndef _CAVIUM_OCTOPCIREG_H_
41 #define _CAVIUM_OCTOPCIREG_H_
44 * This is the bit decoding used for the Octeon PCI controller addresses for config space
56 uint64_t reserved : 13;
60 uint64_t reserved2 : 4;
61 uint64_t endian_swap : 2;
62 uint64_t reserved3 : 10;
68 } octeon_pci_config_space_address_t;
79 uint64_t reserved : 13;
83 uint64_t reserved2 : 4;
84 uint64_t endian_swap : 2;
89 } octeon_pci_io_space_address_t;
92 #define CVMX_OCT_SUBDID_PCI_CFG 1
93 #define CVMX_OCT_SUBDID_PCI_IO 2
94 #define CVMX_OCT_SUBDID_PCI_MEM1 3
95 #define CVMX_OCT_SUBDID_PCI_MEM2 4
96 #define CVMX_OCT_SUBDID_PCI_MEM3 5
97 #define CVMX_OCT_SUBDID_PCI_MEM4 6
99 #define CVMX_OCT_PCI_IO_BASE 0x00004000
100 #define CVMX_OCT_PCI_IO_SIZE 0x08000000
102 #define CVMX_OCT_PCI_MEM1_BASE 0xf0000000
103 #define CVMX_OCT_PCI_MEM1_SIZE 0x0f000000
105 #endif /* !_CAVIUM_OCTOPCIREG_H_ */