3 # This is a placeholder until the hardware support is complete.
6 hint.argemdio.0.at="nexus0"
7 hint.argemdio.0.maddr=0x19000000
8 hint.argemdio.0.msize=0x1000
9 hint.argemdio.0.order=0
11 # DB120 GMAC configuration
12 # + AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0)
13 # + AR934X_ETH_CFG_SW_ONLY_MODE (1 << 6)
14 hint.ar934x_gmac.0.gmac_cfg=0x41
16 # GMAC0 here - connected to an AR8327
17 hint.arswitch.0.at="mdio0"
18 hint.arswitch.0.is_7240=0
19 hint.arswitch.0.is_9340=0 # not the internal switch!
20 hint.arswitch.0.numphys=5
21 hint.arswitch.0.phy4cpu=0
22 hint.arswitch.0.is_rgmii=1
23 hint.arswitch.0.is_gmii=0
24 # XXX other AR8327 configuration parameters
27 # .mode = AR8327_PAD_MAC_RGMII,
28 # .txclk_delay_en = true,
29 # .rxclk_delay_en = true,
30 # .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
31 # .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
33 # .led_ctrl0 = 0x00000000,
34 # .led_ctrl1 = 0xc737c737,
35 # .led_ctrl2 = 0x00000000,
36 # .led_ctrl3 = 0x00c30c00,
41 # .speed = AR8327_PORT_SPEED_1000,
49 # XXX OpenWRT DB120 BSP doesn't have media/duplex set?
50 hint.arge.0.phymask=0x0
51 hint.arge.0.media=1000
53 hint.arge.0.miimode=3 # RGMII
54 hint.arge.0.pll_1000=0x06000000
57 hint.argemdio.1.at="nexus0"
58 hint.argemdio.1.maddr=0x1a000000
59 hint.argemdio.1.msize=0x1000
60 hint.argemdio.1.order=0
62 # Embedded switch on the AR9344
63 # mdio1 is actually created as the AR8327 internal bus; so
64 # this pops up as mdio2.
65 hint.arswitch.1.at="mdio2"
66 hint.arswitch.1.is_7240=0
67 hint.arswitch.1.is_9340=1
68 hint.arswitch.1.numphys=4
69 hint.arswitch.1.phy4cpu=0 # phy 4 is not a "CPU port" PHY here
70 hint.arswitch.1.is_rgmii=0
71 hint.arswitch.1.is_gmii=1 # arge1 <-> switch PHY is GMII
73 # arge1 - lock up to 1000/full
74 hint.arge.1.phymask=0x0 # Nothing attached here (XXX?)
75 hint.arge.1.media=1000
77 hint.arge.1.miimode=1 # GMII
79 # ath0: Where the ART is - last 64k in the flash
80 hint.ath.0.eepromaddr=0x1fff0000
81 hint.ath.0.eepromsize=16384
83 # ath1: it's different; it's a PCIe attached device, so
84 # we instead need to teach the PCIe bridge code about it
85 # (ie, the 'early pci fixup' stuff that programs the PCIe
86 # host registers on the NIC) and then we teach ath where
89 # ath1 hint - pcie slot 0
90 hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
91 hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
93 # ath0 - eeprom comes from here
94 hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
98 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)
101 hint.map.0.at="flash/spi0"
102 hint.map.0.start=0x00000000
103 hint.map.0.end=0x00040000 # 256k u-boot
104 hint.map.0.name="u-boot"
105 hint.map.0.readonly=1
108 hint.map.1.at="flash/spi0"
109 hint.map.1.start=0x00040000
110 hint.map.1.end=0x00050000 # 64k u-boot-env
111 hint.map.1.name="u-boot-env"
112 hint.map.1.readonly=1
115 hint.map.2.at="flash/spi0"
116 hint.map.2.start=0x00050000
117 hint.map.2.end=0x00680000 # 6336k rootfs
118 hint.map.2.name="rootfs"
119 hint.map.2.readonly=1
122 hint.map.3.at="flash/spi0"
123 hint.map.3.start=0x00680000
124 hint.map.3.end=0x007d0000 # 1408k uImage, 64k off the end..
125 hint.map.3.name="uImage"
126 hint.map.3.readonly=1
129 hint.map.4.at="flash/spi0"
130 hint.map.4.start=0x007d0000
131 hint.map.4.end=0x007e0000
132 hint.map.4.name="cfg"
133 hint.map.4.readonly=0
136 hint.map.5.at="flash/spi0"
137 hint.map.5.start=0x007e0000
138 hint.map.5.end=0x007f0000 # 64k mib0
139 hint.map.5.name="mib0"
140 hint.map.5.readonly=1
143 hint.map.6.at="flash/spi0"
144 hint.map.6.start=0x007f0000
145 hint.map.6.end=0x00800000 # 64k ART
146 hint.map.6.name="ART"
147 hint.map.6.readonly=1