3 # This is a placeholder until the hardware support is complete.
6 hint.argemdio.0.at="nexus0"
7 hint.argemdio.0.maddr=0x19000000
8 hint.argemdio.0.msize=0x1000
9 hint.argemdio.0.order=0
11 # DIR-825C1 GMAC configuration
12 # + AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0)
13 # Onboard AR9344 10/100 switch is not wired up
14 hint.ar934x_gmac.0.gmac_cfg=0x1
16 # GMAC0 here - connected to an AR8327
17 hint.arswitch.0.at="mdio0"
18 hint.arswitch.0.is_7240=0
19 hint.arswitch.0.is_9340=0 # not the internal switch!
20 hint.arswitch.0.numphys=5
21 hint.arswitch.0.phy4cpu=0
22 hint.arswitch.0.is_rgmii=1
23 hint.arswitch.0.is_gmii=0
25 # Other AR8327 configuration parameters
27 # AR8327_PAD_MAC_RGMII
28 hint.arswitch.0.pad.0.mode=6
29 hint.arswitch.0.pad.0.txclk_delay_en=1
30 hint.arswitch.0.pad.0.rxclk_delay_en=1
32 # AR8327_CLK_DELAY_SEL1
33 hint.arswitch.0.pad.0.txclk_delay_sel=1
34 # AR8327_CLK_DELAY_SEL2
35 hint.arswitch.0.pad.0.rxclk_delay_sel=2
37 # XXX there's no LED management just yet!
38 hint.arswitch.0.led.ctrl0=0x00000000
39 hint.arswitch.0.led.ctrl1=0xc737c737
40 hint.arswitch.0.led.ctrl2=0x00000000
41 hint.arswitch.0.led.ctrl3=0x00c30c00
42 hint.arswitch.0.led.open_drain=1
44 # force_link=1 is required for the rest of the parameters
46 hint.arswitch.0.port.0.force_link=1
47 hint.arswitch.0.port.0.speed=1000
48 hint.arswitch.0.port.0.duplex=1
49 hint.arswitch.0.port.0.txpause=1
50 hint.arswitch.0.port.0.rxpause=1
52 # XXX OpenWRT DB120 BSP doesn't have media/duplex set?
53 hint.arge.0.phymask=0x0
54 hint.arge.0.media=1000
56 hint.arge.0.miimode=3 # RGMII
57 hint.arge.0.pll_1000=0x06000000
59 # ath0: Where the ART is - last 64k in the flash
60 hint.ath.0.eepromaddr=0x1fff0000
61 hint.ath.0.eepromsize=16384
63 # ath1: it's different; it's a PCIe attached device, so
64 # we instead need to teach the PCIe bridge code about it
65 # (ie, the 'early pci fixup' stuff that programs the PCIe
66 # host registers on the NIC) and then we teach ath where
69 # ath1 hint - pcie slot 0
70 hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
71 hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
73 # ath0 - eeprom comes from here
74 hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
77 # m25p80 spi0.0: mx25l12805d (16384 Kbytes)
79 # uBoot firmware variables:
80 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init
81 # mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)
84 hint.map.0.at="flash/spi0"
85 hint.map.0.start=0x00000000
86 hint.map.0.end= 0x00010000
87 hint.map.0.name="u-boot"
91 hint.map.1.at="flash/spi0"
92 hint.map.1.start=0x00010000
93 hint.map.1.end= 0x00020000
94 hint.map.1.name="u-boot-env"
98 hint.map.2.at="flash/spi0"
99 hint.map.2.start=0x00020000
100 hint.map.2.end="search:0x00100000:0x10000:.!/bin/sh"
101 hint.map.2.name="kernel"
102 hint.map.2.readonly=1
105 hint.map.3.at="flash/spi0"
106 hint.map.3.start="search:0x00100000:0x10000:.!/bin/sh"
107 hint.map.3.end=0x00fb0000
108 hint.map.3.name="rootfs"
109 hint.map.3.readonly=1
111 # 192KiB lang -- remapped to cfg
112 hint.map.4.at="flash/spi0"
113 hint.map.4.start=0x00fb0000
114 hint.map.4.end= 0x00fe0000
115 hint.map.4.name="cfg"
116 hint.map.4.readonly=0
119 hint.map.5.at="flash/spi0"
120 hint.map.5.start=0x00fe0000
121 hint.map.5.end= 0x00ff0000
122 hint.map.5.name="mac"
123 hint.map.5.readonly=1
126 hint.map.6.at="flash/spi0"
127 hint.map.6.start=0x00ff0000
128 hint.map.6.end= 0x01000000
129 hint.map.6.name="art"
130 hint.map.6.readonly=1