1 /* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
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22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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34 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
35 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
42 * Macros used when writing assembler programs.
44 * Copyright (C) 1989 Digital Equipment Corporation.
45 * Permission to use, copy, modify, and distribute this software and
46 * its documentation for any purpose and without fee is hereby granted,
47 * provided that the above copyright notice appears in all copies.
48 * Digital Equipment Corporation makes no representations about the
49 * suitability of this software for any purpose. It is provided "as is"
50 * without express or implied warranty.
52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h,
53 * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL)
56 #ifndef _MACHINE_ASM_H_
57 #define _MACHINE_ASM_H_
59 #include <machine/regdef.h>
60 #include <machine/endian.h>
61 #include <machine/cdefs.h>
64 #if !defined(lint) && !defined(STRIP_FBSDID)
65 #define __FBSDID(s) .ident s
67 #define __FBSDID(s) /* nothing */
71 * Define -pg profile entry code.
72 * Must always be noreorder, must never use a macro instruction
73 * Final addiu to t9 must always equal the size of this _KERN_MCOUNT
75 #define _KERN_MCOUNT \
82 lui t9,%hi(_mcount); \
83 addiu t9,t9,%lo(_mcount); \
92 #define MCOUNT _KERN_MCOUNT
107 * WARN_REFERENCES: create a warning if the specified symbol is referenced
109 #define WARN_REFERENCES(_sym,_msg) \
110 .section .gnu.warning. ## _sym ; .ascii _msg ; .text
113 # define _C_LABEL(x) x
115 # define _C_LABEL(x) _ ## x
119 * WEAK_ALIAS: create a weak alias.
121 #define WEAK_ALIAS(alias,sym) \
126 * STRONG_ALIAS: create a strong alias.
128 #define STRONG_ALIAS(alias,sym) \
132 #define GLOBAL(sym) \
136 .text; .globl sym; .ent sym; sym:
138 #define ASM_ENTRY(sym) \
139 .text; .globl sym; .type sym,@function; sym:
143 * A leaf routine does
144 * - call no other function,
145 * - never use any register that callee-saved (S0-S8), and
146 * - not use any local stack storage.
149 .globl _C_LABEL(x); \
150 .ent _C_LABEL(x), 0; \
157 * No profilable leaf routine.
159 #define LEAF_NOPROFILE(x) \
160 .globl _C_LABEL(x); \
161 .ent _C_LABEL(x), 0; \
167 * declare alternate entry to leaf routine
170 .globl _C_LABEL(x); \
171 AENT (_C_LABEL(x)); \
176 * A function calls other functions and needs
177 * therefore stack space to save/restore registers.
179 #define NESTED(x, fsize, retpc) \
180 .globl _C_LABEL(x); \
181 .ent _C_LABEL(x), 0; \
183 .frame sp, fsize, retpc; \
187 * NESTED_NOPROFILE(x)
188 * No profilable nested routine.
190 #define NESTED_NOPROFILE(x, fsize, retpc) \
191 .globl _C_LABEL(x); \
192 .ent _C_LABEL(x), 0; \
194 .frame sp, fsize, retpc
198 * declare alternate entry point to nested routine.
201 .globl _C_LABEL(x); \
202 AENT (_C_LABEL(x)); \
207 * Mark end of a procedure.
213 * IMPORT -- import external symbol
215 #define IMPORT(sym, size) \
216 .extern _C_LABEL(sym),size
219 * EXPORT -- export definition of symbol
222 .globl _C_LABEL(x); \
227 * exception vector entrypoint
228 * XXX: regmask should be used to generate .mask
230 #define VECTOR(x, regmask) \
231 .ent _C_LABEL(x),0; \
234 #define VECTOR_END(x) \
239 * Macros to panic and printf from assembly language.
243 jal _C_LABEL(panic); \
247 #define PANIC_KSEG0(msg, reg) PANIC(msg)
249 #define PRINTF(msg) \
251 jal _C_LABEL(printf); \
260 #define ASMSTR(str) \
264 #if defined(__mips_o32)
270 #if defined(__mips_o32) || defined(__mips_o64)
271 #define ALSK 7 /* stack alignment */
272 #define ALMASK -7 /* stack alignment */
277 #define ALSK 15 /* stack alignment */
278 #define ALMASK -15 /* stack alignment */
285 * standard callframe {
286 * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1)
287 * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64)
288 * register_t cf_gp; global pointer (only on n32 and n64)
289 * register_t cf_sp; frame pointer
290 * register_t cf_ra; return address
293 #if defined(__mips_o32) || defined(__mips_o64)
294 #define CALLFRAME_SIZ (SZREG * (4 + 2))
295 #define CALLFRAME_S0 0
296 #elif defined(__mips_n32) || defined(__mips_n64)
297 #define CALLFRAME_SIZ (SZREG * 4)
298 #define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG)
301 #define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG)
303 #define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG)
304 #define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG)
307 * Endian-independent assembly-code aliases for unaligned memory accesses.
309 #if _BYTE_ORDER == _LITTLE_ENDIAN
327 #if _BYTE_ORDER == _BIG_ENDIAN
346 * While it would be nice to be compatible with the SGI
347 * REG_L and REG_S macros, because they do not take parameters, it
348 * is impossible to use them with the _MIPS_SIM_ABIX32 model.
350 * These macros hide the use of mips3 instructions from the
351 * assembler to prevent the assembler from generating 64-bit style
354 #if _MIPS_SZPTR == 32
356 #define PTR_ADDI addi
357 #define PTR_ADDU addu
358 #define PTR_ADDIU addiu
360 #define PTR_SUBI subi
361 #define PTR_SUBU subu
362 #define PTR_SUBIU subu
368 #define PTR_SLLV sllv
370 #define PTR_SRLV srlv
372 #define PTR_SRAV srav
375 #define PTR_WORD .word
376 #define PTR_SCALESHIFT 2
377 #else /* _MIPS_SZPTR == 64 */
379 #define PTR_ADDI daddi
380 #define PTR_ADDU daddu
381 #define PTR_ADDIU daddiu
383 #define PTR_SUBI dsubi
384 #define PTR_SUBU dsubu
385 #define PTR_SUBIU dsubu
391 #define PTR_SLLV dsllv
393 #define PTR_SRLV dsrlv
395 #define PTR_SRAV dsrav
398 #define PTR_WORD .dword
399 #define PTR_SCALESHIFT 3
400 #endif /* _MIPS_SZPTR == 64 */
402 #if _MIPS_SZINT == 32
404 #define INT_ADDI addi
405 #define INT_ADDU addu
406 #define INT_ADDIU addiu
408 #define INT_SUBI subi
409 #define INT_SUBU subu
410 #define INT_SUBIU subu
415 #define INT_SLLV sllv
417 #define INT_SRLV srlv
419 #define INT_SRAV srav
422 #define INT_WORD .word
423 #define INT_SCALESHIFT 2
426 #define INT_ADDI daddi
427 #define INT_ADDU daddu
428 #define INT_ADDIU daddiu
430 #define INT_SUBI dsubi
431 #define INT_SUBU dsubu
432 #define INT_SUBIU dsubu
437 #define INT_SLLV dsllv
439 #define INT_SRLV dsrlv
441 #define INT_SRAV dsrav
444 #define INT_WORD .dword
445 #define INT_SCALESHIFT 3
448 #if _MIPS_SZLONG == 32
450 #define LONG_ADDI addi
451 #define LONG_ADDU addu
452 #define LONG_ADDIU addiu
454 #define LONG_SUBI subi
455 #define LONG_SUBU subu
456 #define LONG_SUBIU subu
461 #define LONG_SLLV sllv
463 #define LONG_SRLV srlv
465 #define LONG_SRAV srav
468 #define LONG_WORD .word
469 #define LONG_SCALESHIFT 2
471 #define LONG_ADD dadd
472 #define LONG_ADDI daddi
473 #define LONG_ADDU daddu
474 #define LONG_ADDIU daddiu
475 #define LONG_SUB dadd
476 #define LONG_SUBI dsubi
477 #define LONG_SUBU dsubu
478 #define LONG_SUBIU dsubu
482 #define LONG_SLL dsll
483 #define LONG_SLLV dsllv
484 #define LONG_SRL dsrl
485 #define LONG_SRLV dsrlv
486 #define LONG_SRA dsra
487 #define LONG_SRAV dsrav
490 #define LONG_WORD .dword
491 #define LONG_SCALESHIFT 3
498 #define REG_ADDU addu
500 #define REG_SLLV sllv
502 #define REG_SRLV srlv
504 #define REG_SRAV srav
507 #define REG_SCALESHIFT 2
512 #define REG_ADDU daddu
514 #define REG_SLLV dsllv
516 #define REG_SRLV dsrlv
518 #define REG_SRAV dsrav
521 #define REG_SCALESHIFT 3
524 #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
525 _MIPS_ISA == _MIPS_ISA_MIPS32
529 #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
530 _MIPS_ISA == _MIPS_ISA_MIPS64
535 #if defined(__mips_o32) || defined(__mips_o64)
538 #define CPRESTORE(r) .cprestore r
539 #define CPLOAD(r) .cpload r
541 #define CPRESTORE(r) /* not needed */
542 #define CPLOAD(r) /* not needed */
550 #define SETUP_GPX(r) \
553 move r,ra; /* save old ra */ \
559 #define SETUP_GPX_L(r,lbl) \
562 move r,ra; /* save old ra */ \
568 #define SAVE_GP(x) .cprestore x
570 #define SETUP_GP64(a,b) /* n32/n64 specific */
571 #define SETUP_GP64_R(a,b) /* n32/n64 specific */
572 #define SETUP_GPX64(a,b) /* n32/n64 specific */
573 #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
574 #define RESTORE_GP64 /* n32/n64 specific */
575 #define USE_ALT_CP(a) /* n32/n64 specific */
576 #endif /* __mips_o32 || __mips_o64 */
578 #if defined(__mips_o32) || defined(__mips_o64)
579 #define REG_PROLOGUE .set push
580 #define REG_EPILOGUE .set pop
582 #if defined(__mips_n32) || defined(__mips_n64)
583 #define REG_PROLOGUE .set push ; .set mips3
584 #define REG_EPILOGUE .set pop
587 #if defined(__mips_n32) || defined(__mips_n64)
588 #define SETUP_GP /* o32 specific */
589 #define SETUP_GPX(r) /* o32 specific */
590 #define SETUP_GPX_L(r,lbl) /* o32 specific */
591 #define SAVE_GP(x) /* o32 specific */
592 #define SETUP_GP64(a,b) .cpsetup $25, a, b
593 #define SETUP_GPX64(a,b) \
600 .cpsetup ra, a, 7b; \
602 #define SETUP_GPX64_L(a,b,c) \
611 #define RESTORE_GP64 .cpreturn
612 #define USE_ALT_CP(a) .cplocal a
613 #endif /* __mips_n32 || __mips_n64 */
615 #define GET_CPU_PCPU(reg) \
616 PTR_L reg, _C_LABEL(pcpup);
619 * Description of the setjmp buffer
621 * word 0 magic number (dependant on creator)
633 * 12 GP (dependent on ABI)
634 * 13 signal mask (dependant on magic)
639 * The magic number number identifies the jmp_buf and
640 * how the buffer was created as well as providing
645 #define _JB_MAGIC__SETJMP 0xBADFACED
646 #define _JB_MAGIC_SETJMP 0xFACEDBAD
648 /* Valid for all jmp_buf's */
660 #define _JB_REG_SP 10
661 #define _JB_REG_S8 11
662 #if defined(__mips_n32) || defined(__mips_n64)
663 #define _JB_REG_GP 12
666 /* Only valid with the _JB_MAGIC_SETJMP magic */
668 #define _JB_SIGMASK 13
669 #define __JB_SIGMASK_REMAINDER 14 /* sigmask_t is 128-bits */
671 #define _JB_FPREG_F20 15
672 #define _JB_FPREG_F21 16
673 #define _JB_FPREG_F22 17
674 #define _JB_FPREG_F23 18
675 #define _JB_FPREG_F24 19
676 #define _JB_FPREG_F25 20
677 #define _JB_FPREG_F26 21
678 #define _JB_FPREG_F27 22
679 #define _JB_FPREG_F28 23
680 #define _JB_FPREG_F29 24
681 #define _JB_FPREG_F30 25
682 #define _JB_FPREG_F31 26
683 #define _JB_FPREG_FCSR 27
686 * Various macros for dealing with TLB hazards
689 * (c) why not used everywhere?
692 * Assume that w alaways need nops to escape CP0 hazard
693 * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment
694 * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture
695 * For Programmers Volume III: The MIPS32 Privileged Resource Architecture"
698 #define HAZARD_DELAY sll $0,3
699 #define ITLBNOPFIX sll $0,3
700 #elif defined(CPU_RMI)
703 #elif defined(CPU_MIPS74K)
704 #define HAZARD_DELAY sll $0,$0,3
705 #define ITLBNOPFIX sll $0,$0,3
707 #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
708 #define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3;
711 #endif /* !_MACHINE_ASM_H_ */