1 /* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This code is derived from software contributed to Berkeley by
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13 * modification, are permitted provided that the following conditions
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16 * notice, this list of conditions and the following disclaimer.
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20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
37 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
44 * Macros used when writing assembler programs.
46 * Copyright (C) 1989 Digital Equipment Corporation.
47 * Permission to use, copy, modify, and distribute this software and
48 * its documentation for any purpose and without fee is hereby granted,
49 * provided that the above copyright notice appears in all copies.
50 * Digital Equipment Corporation makes no representations about the
51 * suitability of this software for any purpose. It is provided "as is"
52 * without express or implied warranty.
54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h,
55 * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL)
58 #ifndef _MACHINE_ASM_H_
59 #define _MACHINE_ASM_H_
61 #include <machine/abi.h>
62 #include <machine/regdef.h>
63 #include <machine/endian.h>
64 #include <machine/cdefs.h>
67 #if !defined(lint) && !defined(STRIP_FBSDID)
68 #define __FBSDID(s) .ident s
70 #define __FBSDID(s) /* nothing */
74 * Define -pg profile entry code.
75 * Must always be noreorder, must never use a macro instruction
76 * Final addiu to t9 must always equal the size of this _KERN_MCOUNT
78 #define _KERN_MCOUNT \
85 lui t9,%hi(_mcount); \
86 addiu t9,t9,%lo(_mcount); \
95 #define MCOUNT _KERN_MCOUNT
100 #define _C_LABEL(x) x
110 * WARN_REFERENCES: create a warning if the specified symbol is referenced
112 #define WARN_REFERENCES(_sym,_msg) \
113 .section .gnu.warning. ## _sym ; .ascii _msg ; .text
116 # define _C_LABEL(x) x
118 # define _C_LABEL(x) _ ## x
122 * WEAK_ALIAS: create a weak alias.
124 #define WEAK_ALIAS(alias,sym) \
129 * STRONG_ALIAS: create a strong alias.
131 #define STRONG_ALIAS(alias,sym) \
135 #define GLOBAL(sym) \
139 .text; .globl sym; .ent sym; sym:
141 #define ASM_ENTRY(sym) \
142 .text; .globl sym; .type sym,@function; sym:
146 * A leaf routine does
147 * - call no other function,
148 * - never use any register that callee-saved (S0-S8), and
149 * - not use any local stack storage.
152 .globl _C_LABEL(x); \
153 .ent _C_LABEL(x), 0; \
160 * No profilable leaf routine.
162 #define LEAF_NOPROFILE(x) \
163 .globl _C_LABEL(x); \
164 .ent _C_LABEL(x), 0; \
170 * declare alternate entry to leaf routine
173 .globl _C_LABEL(x); \
174 AENT (_C_LABEL(x)); \
179 * A function calls other functions and needs
180 * therefore stack space to save/restore registers.
182 #define NESTED(x, fsize, retpc) \
183 .globl _C_LABEL(x); \
184 .ent _C_LABEL(x), 0; \
186 .frame sp, fsize, retpc; \
190 * NESTED_NOPROFILE(x)
191 * No profilable nested routine.
193 #define NESTED_NOPROFILE(x, fsize, retpc) \
194 .globl _C_LABEL(x); \
195 .ent _C_LABEL(x), 0; \
197 .frame sp, fsize, retpc
201 * declare alternate entry point to nested routine.
204 .globl _C_LABEL(x); \
205 AENT (_C_LABEL(x)); \
210 * Mark end of a procedure.
216 * IMPORT -- import external symbol
218 #define IMPORT(sym, size) \
219 .extern _C_LABEL(sym),size
222 * EXPORT -- export definition of symbol
225 .globl _C_LABEL(x); \
230 * exception vector entrypoint
231 * XXX: regmask should be used to generate .mask
233 #define VECTOR(x, regmask) \
234 .ent _C_LABEL(x),0; \
237 #define VECTOR_END(x) \
242 * Macros to panic and printf from assembly language.
246 jal _C_LABEL(panic); \
250 #define PANIC_KSEG0(msg, reg) PANIC(msg)
252 #define PRINTF(msg) \
254 jal _C_LABEL(printf); \
263 #define ASMSTR(str) \
267 #if defined(__mips_o32) || defined(__mips_o64)
268 #define ALSK 7 /* stack alignment */
269 #define ALMASK -7 /* stack alignment */
274 #define ALSK 15 /* stack alignment */
275 #define ALMASK -15 /* stack alignment */
282 * Endian-independent assembly-code aliases for unaligned memory accesses.
284 #if _BYTE_ORDER == _LITTLE_ENDIAN
302 #if _BYTE_ORDER == _BIG_ENDIAN
321 * While it would be nice to be compatible with the SGI
322 * REG_L and REG_S macros, because they do not take parameters, it
323 * is impossible to use them with the _MIPS_SIM_ABIX32 model.
325 * These macros hide the use of mips3 instructions from the
326 * assembler to prevent the assembler from generating 64-bit style
329 #if _MIPS_SZPTR == 32
331 #define PTR_ADDI addi
332 #define PTR_ADDU addu
333 #define PTR_ADDIU addiu
335 #define PTR_SUBI subi
336 #define PTR_SUBU subu
337 #define PTR_SUBIU subu
343 #define PTR_SLLV sllv
345 #define PTR_SRLV srlv
347 #define PTR_SRAV srav
350 #define PTR_WORD .word
351 #define PTR_SCALESHIFT 2
352 #else /* _MIPS_SZPTR == 64 */
354 #define PTR_ADDI daddi
355 #define PTR_ADDU daddu
356 #define PTR_ADDIU daddiu
358 #define PTR_SUBI dsubi
359 #define PTR_SUBU dsubu
360 #define PTR_SUBIU dsubu
366 #define PTR_SLLV dsllv
368 #define PTR_SRLV dsrlv
370 #define PTR_SRAV dsrav
373 #define PTR_WORD .dword
374 #define PTR_SCALESHIFT 3
375 #endif /* _MIPS_SZPTR == 64 */
377 #if _MIPS_SZINT == 32
379 #define INT_ADDI addi
380 #define INT_ADDU addu
381 #define INT_ADDIU addiu
383 #define INT_SUBI subi
384 #define INT_SUBU subu
385 #define INT_SUBIU subu
390 #define INT_SLLV sllv
392 #define INT_SRLV srlv
394 #define INT_SRAV srav
397 #define INT_WORD .word
398 #define INT_SCALESHIFT 2
401 #define INT_ADDI daddi
402 #define INT_ADDU daddu
403 #define INT_ADDIU daddiu
405 #define INT_SUBI dsubi
406 #define INT_SUBU dsubu
407 #define INT_SUBIU dsubu
412 #define INT_SLLV dsllv
414 #define INT_SRLV dsrlv
416 #define INT_SRAV dsrav
419 #define INT_WORD .dword
420 #define INT_SCALESHIFT 3
423 #if _MIPS_SZLONG == 32
425 #define LONG_ADDI addi
426 #define LONG_ADDU addu
427 #define LONG_ADDIU addiu
429 #define LONG_SUBI subi
430 #define LONG_SUBU subu
431 #define LONG_SUBIU subu
436 #define LONG_SLLV sllv
438 #define LONG_SRLV srlv
440 #define LONG_SRAV srav
443 #define LONG_WORD .word
444 #define LONG_SCALESHIFT 2
446 #define LONG_ADD dadd
447 #define LONG_ADDI daddi
448 #define LONG_ADDU daddu
449 #define LONG_ADDIU daddiu
450 #define LONG_SUB dadd
451 #define LONG_SUBI dsubi
452 #define LONG_SUBU dsubu
453 #define LONG_SUBIU dsubu
457 #define LONG_SLL dsll
458 #define LONG_SLLV dsllv
459 #define LONG_SRL dsrl
460 #define LONG_SRLV dsrlv
461 #define LONG_SRA dsra
462 #define LONG_SRAV dsrav
465 #define LONG_WORD .dword
466 #define LONG_SCALESHIFT 3
473 #define REG_ADDU addu
475 #define REG_SLLV sllv
477 #define REG_SRLV srlv
479 #define REG_SRAV srav
482 #define REG_SCALESHIFT 2
487 #define REG_ADDU daddu
489 #define REG_SLLV dsllv
491 #define REG_SRLV dsrlv
493 #define REG_SRAV dsrav
496 #define REG_SCALESHIFT 3
499 #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
500 _MIPS_ISA == _MIPS_ISA_MIPS32
504 #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
505 _MIPS_ISA == _MIPS_ISA_MIPS64
510 #if defined(__mips_o32) || defined(__mips_o64)
513 #define CPRESTORE(r) .cprestore r
514 #define CPLOAD(r) .cpload r
516 #define CPRESTORE(r) /* not needed */
517 #define CPLOAD(r) /* not needed */
525 #define SETUP_GPX(r) \
528 move r,ra; /* save old ra */ \
534 #define SETUP_GPX_L(r,lbl) \
537 move r,ra; /* save old ra */ \
543 #define SAVE_GP(x) .cprestore x
545 #define SETUP_GP64(a,b) /* n32/n64 specific */
546 #define SETUP_GP64_R(a,b) /* n32/n64 specific */
547 #define SETUP_GPX64(a,b) /* n32/n64 specific */
548 #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
549 #define RESTORE_GP64 /* n32/n64 specific */
550 #define USE_ALT_CP(a) /* n32/n64 specific */
551 #endif /* __mips_o32 || __mips_o64 */
553 #if defined(__mips_o32) || defined(__mips_o64)
554 #define REG_PROLOGUE .set push
555 #define REG_EPILOGUE .set pop
557 #if defined(__mips_n32) || defined(__mips_n64)
558 #define REG_PROLOGUE .set push ; .set mips3
559 #define REG_EPILOGUE .set pop
562 #if defined(__mips_n32) || defined(__mips_n64)
563 #define SETUP_GP /* o32 specific */
564 #define SETUP_GPX(r) /* o32 specific */
565 #define SETUP_GPX_L(r,lbl) /* o32 specific */
566 #define SAVE_GP(x) /* o32 specific */
567 #define SETUP_GP64(a,b) .cpsetup $25, a, b
568 #define SETUP_GPX64(a,b) \
575 .cpsetup ra, a, 7b; \
577 #define SETUP_GPX64_L(a,b,c) \
586 #define RESTORE_GP64 .cpreturn
587 #define USE_ALT_CP(a) .cplocal a
588 #endif /* __mips_n32 || __mips_n64 */
590 #define GET_CPU_PCPU(reg) \
591 PTR_L reg, _C_LABEL(pcpup);
594 * Description of the setjmp buffer
596 * word 0 magic number (dependant on creator)
608 * 12 GP (dependent on ABI)
609 * 13 signal mask (dependant on magic)
614 * The magic number number identifies the jmp_buf and
615 * how the buffer was created as well as providing
620 #define _JB_MAGIC__SETJMP 0xBADFACED
621 #define _JB_MAGIC_SETJMP 0xFACEDBAD
623 /* Valid for all jmp_buf's */
635 #define _JB_REG_SP 10
636 #define _JB_REG_S8 11
637 #if defined(__mips_n32) || defined(__mips_n64)
638 #define _JB_REG_GP 12
641 /* Only valid with the _JB_MAGIC_SETJMP magic */
643 #define _JB_SIGMASK 13
644 #define __JB_SIGMASK_REMAINDER 14 /* sigmask_t is 128-bits */
646 #define _JB_FPREG_F20 15
647 #define _JB_FPREG_F21 16
648 #define _JB_FPREG_F22 17
649 #define _JB_FPREG_F23 18
650 #define _JB_FPREG_F24 19
651 #define _JB_FPREG_F25 20
652 #define _JB_FPREG_F26 21
653 #define _JB_FPREG_F27 22
654 #define _JB_FPREG_F28 23
655 #define _JB_FPREG_F29 24
656 #define _JB_FPREG_F30 25
657 #define _JB_FPREG_F31 26
658 #define _JB_FPREG_FCSR 27
661 * Various macros for dealing with TLB hazards
664 * (c) why not used everywhere?
667 * Assume that w alaways need nops to escape CP0 hazard
668 * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment
669 * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture
670 * For Programmers Volume III: The MIPS32 Privileged Resource Architecture"
673 #define HAZARD_DELAY sll $0,3
674 #define ITLBNOPFIX sll $0,3
675 #elif defined(CPU_RMI)
678 #elif defined(CPU_MIPS74K)
679 #define HAZARD_DELAY sll $0,$0,3
680 #define ITLBNOPFIX sll $0,$0,3
682 #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
683 #define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3;
686 #endif /* !_MACHINE_ASM_H_ */