1 /* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This code is derived from software contributed to Berkeley by
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13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
37 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
44 * Macros used when writing assembler programs.
46 * Copyright (C) 1989 Digital Equipment Corporation.
47 * Permission to use, copy, modify, and distribute this software and
48 * its documentation for any purpose and without fee is hereby granted,
49 * provided that the above copyright notice appears in all copies.
50 * Digital Equipment Corporation makes no representations about the
51 * suitability of this software for any purpose. It is provided "as is"
52 * without express or implied warranty.
54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h,
55 * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL)
58 #ifndef _MACHINE_ASM_H_
59 #define _MACHINE_ASM_H_
61 #include <machine/regdef.h>
62 #include <machine/endian.h>
63 #include <machine/cdefs.h>
66 #if !defined(lint) && !defined(STRIP_FBSDID)
67 #define __FBSDID(s) .ident s
69 #define __FBSDID(s) /* nothing */
73 * Define -pg profile entry code.
74 * Must always be noreorder, must never use a macro instruction
75 * Final addiu to t9 must always equal the size of this _KERN_MCOUNT
77 #define _KERN_MCOUNT \
84 lui t9,%hi(_mcount); \
85 addiu t9,t9,%lo(_mcount); \
94 #define MCOUNT _KERN_MCOUNT
109 * WARN_REFERENCES: create a warning if the specified symbol is referenced
111 #define WARN_REFERENCES(_sym,_msg) \
112 .section .gnu.warning. ## _sym ; .ascii _msg ; .text
115 # define _C_LABEL(x) x
117 # define _C_LABEL(x) _ ## x
121 * WEAK_ALIAS: create a weak alias.
123 #define WEAK_ALIAS(alias,sym) \
128 * STRONG_ALIAS: create a strong alias.
130 #define STRONG_ALIAS(alias,sym) \
134 #define GLOBAL(sym) \
138 .text; .globl sym; .ent sym; sym:
140 #define ASM_ENTRY(sym) \
141 .text; .globl sym; .type sym,@function; sym:
145 * A leaf routine does
146 * - call no other function,
147 * - never use any register that callee-saved (S0-S8), and
148 * - not use any local stack storage.
151 .globl _C_LABEL(x); \
152 .ent _C_LABEL(x), 0; \
159 * No profilable leaf routine.
161 #define LEAF_NOPROFILE(x) \
162 .globl _C_LABEL(x); \
163 .ent _C_LABEL(x), 0; \
169 * declare alternate entry to leaf routine
172 .globl _C_LABEL(x); \
173 AENT (_C_LABEL(x)); \
178 * A function calls other functions and needs
179 * therefore stack space to save/restore registers.
181 #define NESTED(x, fsize, retpc) \
182 .globl _C_LABEL(x); \
183 .ent _C_LABEL(x), 0; \
185 .frame sp, fsize, retpc; \
189 * NESTED_NOPROFILE(x)
190 * No profilable nested routine.
192 #define NESTED_NOPROFILE(x, fsize, retpc) \
193 .globl _C_LABEL(x); \
194 .ent _C_LABEL(x), 0; \
196 .frame sp, fsize, retpc
200 * declare alternate entry point to nested routine.
203 .globl _C_LABEL(x); \
204 AENT (_C_LABEL(x)); \
209 * Mark end of a procedure.
215 * IMPORT -- import external symbol
217 #define IMPORT(sym, size) \
218 .extern _C_LABEL(sym),size
221 * EXPORT -- export definition of symbol
224 .globl _C_LABEL(x); \
229 * exception vector entrypoint
230 * XXX: regmask should be used to generate .mask
232 #define VECTOR(x, regmask) \
233 .ent _C_LABEL(x),0; \
236 #define VECTOR_END(x) \
241 * Macros to panic and printf from assembly language.
245 jal _C_LABEL(panic); \
249 #define PANIC_KSEG0(msg, reg) PANIC(msg)
251 #define PRINTF(msg) \
253 jal _C_LABEL(printf); \
262 #define ASMSTR(str) \
266 #if defined(__mips_o32)
272 #if defined(__mips_o32) || defined(__mips_o64)
273 #define ALSK 7 /* stack alignment */
274 #define ALMASK -7 /* stack alignment */
279 #define ALSK 15 /* stack alignment */
280 #define ALMASK -15 /* stack alignment */
287 * standard callframe {
288 * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1)
289 * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64)
290 * register_t cf_gp; global pointer (only on n32 and n64)
291 * register_t cf_sp; frame pointer
292 * register_t cf_ra; return address
295 #if defined(__mips_o32) || defined(__mips_o64)
296 #define CALLFRAME_SIZ (SZREG * (4 + 2))
297 #define CALLFRAME_S0 0
298 #elif defined(__mips_n32) || defined(__mips_n64)
299 #define CALLFRAME_SIZ (SZREG * 4)
300 #define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG)
303 #define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG)
305 #define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG)
306 #define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG)
309 * Endian-independent assembly-code aliases for unaligned memory accesses.
311 #if _BYTE_ORDER == _LITTLE_ENDIAN
329 #if _BYTE_ORDER == _BIG_ENDIAN
348 * While it would be nice to be compatible with the SGI
349 * REG_L and REG_S macros, because they do not take parameters, it
350 * is impossible to use them with the _MIPS_SIM_ABIX32 model.
352 * These macros hide the use of mips3 instructions from the
353 * assembler to prevent the assembler from generating 64-bit style
356 #if _MIPS_SZPTR == 32
358 #define PTR_ADDI addi
359 #define PTR_ADDU addu
360 #define PTR_ADDIU addiu
362 #define PTR_SUBI subi
363 #define PTR_SUBU subu
364 #define PTR_SUBIU subu
370 #define PTR_SLLV sllv
372 #define PTR_SRLV srlv
374 #define PTR_SRAV srav
377 #define PTR_WORD .word
378 #define PTR_SCALESHIFT 2
379 #else /* _MIPS_SZPTR == 64 */
381 #define PTR_ADDI daddi
382 #define PTR_ADDU daddu
383 #define PTR_ADDIU daddiu
385 #define PTR_SUBI dsubi
386 #define PTR_SUBU dsubu
387 #define PTR_SUBIU dsubu
393 #define PTR_SLLV dsllv
395 #define PTR_SRLV dsrlv
397 #define PTR_SRAV dsrav
400 #define PTR_WORD .dword
401 #define PTR_SCALESHIFT 3
402 #endif /* _MIPS_SZPTR == 64 */
404 #if _MIPS_SZINT == 32
406 #define INT_ADDI addi
407 #define INT_ADDU addu
408 #define INT_ADDIU addiu
410 #define INT_SUBI subi
411 #define INT_SUBU subu
412 #define INT_SUBIU subu
417 #define INT_SLLV sllv
419 #define INT_SRLV srlv
421 #define INT_SRAV srav
424 #define INT_WORD .word
425 #define INT_SCALESHIFT 2
428 #define INT_ADDI daddi
429 #define INT_ADDU daddu
430 #define INT_ADDIU daddiu
432 #define INT_SUBI dsubi
433 #define INT_SUBU dsubu
434 #define INT_SUBIU dsubu
439 #define INT_SLLV dsllv
441 #define INT_SRLV dsrlv
443 #define INT_SRAV dsrav
446 #define INT_WORD .dword
447 #define INT_SCALESHIFT 3
450 #if _MIPS_SZLONG == 32
452 #define LONG_ADDI addi
453 #define LONG_ADDU addu
454 #define LONG_ADDIU addiu
456 #define LONG_SUBI subi
457 #define LONG_SUBU subu
458 #define LONG_SUBIU subu
463 #define LONG_SLLV sllv
465 #define LONG_SRLV srlv
467 #define LONG_SRAV srav
470 #define LONG_WORD .word
471 #define LONG_SCALESHIFT 2
473 #define LONG_ADD dadd
474 #define LONG_ADDI daddi
475 #define LONG_ADDU daddu
476 #define LONG_ADDIU daddiu
477 #define LONG_SUB dadd
478 #define LONG_SUBI dsubi
479 #define LONG_SUBU dsubu
480 #define LONG_SUBIU dsubu
484 #define LONG_SLL dsll
485 #define LONG_SLLV dsllv
486 #define LONG_SRL dsrl
487 #define LONG_SRLV dsrlv
488 #define LONG_SRA dsra
489 #define LONG_SRAV dsrav
492 #define LONG_WORD .dword
493 #define LONG_SCALESHIFT 3
500 #define REG_ADDU addu
502 #define REG_SLLV sllv
504 #define REG_SRLV srlv
506 #define REG_SRAV srav
509 #define REG_SCALESHIFT 2
514 #define REG_ADDU daddu
516 #define REG_SLLV dsllv
518 #define REG_SRLV dsrlv
520 #define REG_SRAV dsrav
523 #define REG_SCALESHIFT 3
526 #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
527 _MIPS_ISA == _MIPS_ISA_MIPS32
531 #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
532 _MIPS_ISA == _MIPS_ISA_MIPS64
537 #if defined(__mips_o32) || defined(__mips_o64)
540 #define CPRESTORE(r) .cprestore r
541 #define CPLOAD(r) .cpload r
543 #define CPRESTORE(r) /* not needed */
544 #define CPLOAD(r) /* not needed */
552 #define SETUP_GPX(r) \
555 move r,ra; /* save old ra */ \
561 #define SETUP_GPX_L(r,lbl) \
564 move r,ra; /* save old ra */ \
570 #define SAVE_GP(x) .cprestore x
572 #define SETUP_GP64(a,b) /* n32/n64 specific */
573 #define SETUP_GP64_R(a,b) /* n32/n64 specific */
574 #define SETUP_GPX64(a,b) /* n32/n64 specific */
575 #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
576 #define RESTORE_GP64 /* n32/n64 specific */
577 #define USE_ALT_CP(a) /* n32/n64 specific */
578 #endif /* __mips_o32 || __mips_o64 */
580 #if defined(__mips_o32) || defined(__mips_o64)
581 #define REG_PROLOGUE .set push
582 #define REG_EPILOGUE .set pop
584 #if defined(__mips_n32) || defined(__mips_n64)
585 #define REG_PROLOGUE .set push ; .set mips3
586 #define REG_EPILOGUE .set pop
589 #if defined(__mips_n32) || defined(__mips_n64)
590 #define SETUP_GP /* o32 specific */
591 #define SETUP_GPX(r) /* o32 specific */
592 #define SETUP_GPX_L(r,lbl) /* o32 specific */
593 #define SAVE_GP(x) /* o32 specific */
594 #define SETUP_GP64(a,b) .cpsetup $25, a, b
595 #define SETUP_GPX64(a,b) \
602 .cpsetup ra, a, 7b; \
604 #define SETUP_GPX64_L(a,b,c) \
613 #define RESTORE_GP64 .cpreturn
614 #define USE_ALT_CP(a) .cplocal a
615 #endif /* __mips_n32 || __mips_n64 */
617 #define GET_CPU_PCPU(reg) \
618 PTR_L reg, _C_LABEL(pcpup);
621 * Description of the setjmp buffer
623 * word 0 magic number (dependant on creator)
635 * 12 GP (dependent on ABI)
636 * 13 signal mask (dependant on magic)
641 * The magic number number identifies the jmp_buf and
642 * how the buffer was created as well as providing
647 #define _JB_MAGIC__SETJMP 0xBADFACED
648 #define _JB_MAGIC_SETJMP 0xFACEDBAD
650 /* Valid for all jmp_buf's */
662 #define _JB_REG_SP 10
663 #define _JB_REG_S8 11
664 #if defined(__mips_n32) || defined(__mips_n64)
665 #define _JB_REG_GP 12
668 /* Only valid with the _JB_MAGIC_SETJMP magic */
670 #define _JB_SIGMASK 13
671 #define __JB_SIGMASK_REMAINDER 14 /* sigmask_t is 128-bits */
673 #define _JB_FPREG_F20 15
674 #define _JB_FPREG_F21 16
675 #define _JB_FPREG_F22 17
676 #define _JB_FPREG_F23 18
677 #define _JB_FPREG_F24 19
678 #define _JB_FPREG_F25 20
679 #define _JB_FPREG_F26 21
680 #define _JB_FPREG_F27 22
681 #define _JB_FPREG_F28 23
682 #define _JB_FPREG_F29 24
683 #define _JB_FPREG_F30 25
684 #define _JB_FPREG_F31 26
685 #define _JB_FPREG_FCSR 27
688 * Various macros for dealing with TLB hazards
691 * (c) why not used everywhere?
694 * Assume that w alaways need nops to escape CP0 hazard
695 * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment
696 * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture
697 * For Programmers Volume III: The MIPS32 Privileged Resource Architecture"
700 #define HAZARD_DELAY sll $0,3
701 #define ITLBNOPFIX sll $0,3
702 #elif defined(CPU_RMI)
705 #elif defined(CPU_MIPS74K)
706 #define HAZARD_DELAY sll $0,$0,3
707 #define ITLBNOPFIX sll $0,$0,3
709 #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
710 #define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3;
713 #endif /* !_MACHINE_ASM_H_ */