1 /* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
4 * SPDX-License-Identifier: BSD-4-Clause
6 * Copyright 2001 Wasabi Systems, Inc.
9 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
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19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed for the NetBSD Project by
22 * Wasabi Systems, Inc.
23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
24 * or promote products derived from this software without specific prior
27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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42 #ifndef _MACHINE_CACHE_H_
43 #define _MACHINE_CACHE_H_
48 * We define the following primitives:
50 * --- Instruction cache synchronization (mandatory):
52 * icache_sync_all Synchronize I-cache
54 * icache_sync_range Synchronize I-cache range
56 * icache_sync_range_index (index ops)
58 * --- Primary data cache (mandatory):
60 * pdcache_wbinv_all Write-back Invalidate primary D-cache
62 * pdcache_wbinv_range Write-back Invalidate primary D-cache range
64 * pdcache_wbinv_range_index (index ops)
66 * pdcache_inv_range Invalidate primary D-cache range
68 * pdcache_wb_range Write-back primary D-cache range
70 * --- Secondary data cache (optional):
72 * sdcache_wbinv_all Write-back Invalidate secondary D-cache
74 * sdcache_wbinv_range Write-back Invalidate secondary D-cache range
76 * sdcache_wbinv_range_index (index ops)
78 * sdcache_inv_range Invalidate secondary D-cache range
80 * sdcache_wb_range Write-back secondary D-cache range
82 * There are some rules that must be followed:
84 * I-cache Synch (all or range):
85 * The goal is to synchronize the instruction stream,
86 * so you may need to write-back dirty data cache
87 * blocks first. If a range is requested, and you
88 * can't synchronize just a range, you have to hit
91 * D-cache Write-back Invalidate range:
92 * If you can't WB-Inv a range, you must WB-Inv the
96 * If you can't Inv the D-cache without doing a
97 * Write-back, YOU MUST PANIC. This is to catch
98 * errors in calling code. Callers must be aware
99 * of this scenario, and must handle it appropriately
100 * (consider the bus_dma(9) operations).
102 * D-cache Write-back:
103 * If you can't Write-back without doing an invalidate,
104 * that's fine. Then treat this as a WB-Inv. Skipping
105 * the invalidate is merely an optimization.
108 * Valid virtual addresses must be passed to the
111 * Finally, these primitives are grouped together in reasonable
112 * ways. For all operations described here, first the primary
113 * cache is frobbed, then the secondary cache frobbed, if the
114 * operation for the secondary cache exists.
116 * mips_icache_sync_all Synchronize I-cache
118 * mips_icache_sync_range Synchronize I-cache range
120 * mips_icache_sync_range_index (index ops)
122 * mips_dcache_wbinv_all Write-back Invalidate D-cache
124 * mips_dcache_wbinv_range Write-back Invalidate D-cache range
126 * mips_dcache_wbinv_range_index (index ops)
128 * mips_dcache_inv_range Invalidate D-cache range
130 * mips_dcache_wb_range Write-back D-cache range
133 struct mips_cache_ops {
134 void (*mco_icache_sync_all)(void);
135 void (*mco_icache_sync_range)(vm_offset_t, vm_size_t);
136 void (*mco_icache_sync_range_index)(vm_offset_t, vm_size_t);
138 void (*mco_pdcache_wbinv_all)(void);
139 void (*mco_pdcache_wbinv_range)(vm_offset_t, vm_size_t);
140 void (*mco_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
141 void (*mco_pdcache_inv_range)(vm_offset_t, vm_size_t);
142 void (*mco_pdcache_wb_range)(vm_offset_t, vm_size_t);
144 /* These are called only by the (mipsNN) icache functions. */
145 void (*mco_intern_pdcache_wbinv_all)(void);
146 void (*mco_intern_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
147 void (*mco_intern_pdcache_wb_range)(vm_offset_t, vm_size_t);
149 void (*mco_sdcache_wbinv_all)(void);
150 void (*mco_sdcache_wbinv_range)(vm_offset_t, vm_size_t);
151 void (*mco_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
152 void (*mco_sdcache_inv_range)(vm_offset_t, vm_size_t);
153 void (*mco_sdcache_wb_range)(vm_offset_t, vm_size_t);
155 /* These are called only by the (mipsNN) icache functions. */
156 void (*mco_intern_sdcache_wbinv_all)(void);
157 void (*mco_intern_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
158 void (*mco_intern_sdcache_wb_range)(vm_offset_t, vm_size_t);
161 extern struct mips_cache_ops mips_cache_ops;
163 /* PRIMARY CACHE VARIABLES */
164 extern int mips_picache_linesize;
165 extern int mips_pdcache_linesize;
166 extern int mips_sdcache_linesize;
167 extern int mips_dcache_max_linesize;
169 #define __mco_noargs(prefix, x) \
171 (*mips_cache_ops.mco_ ## prefix ## p ## x )(); \
172 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
173 (*mips_cache_ops.mco_ ## prefix ## s ## x )(); \
174 } while (/*CONSTCOND*/0)
176 #define __mco_2args(prefix, x, a, b) \
178 (*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \
179 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
180 (*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \
181 } while (/*CONSTCOND*/0)
183 #define mips_icache_sync_all() \
184 (*mips_cache_ops.mco_icache_sync_all)()
186 #define mips_icache_sync_range(v, s) \
187 (*mips_cache_ops.mco_icache_sync_range)((v), (s))
189 #define mips_icache_sync_range_index(v, s) \
190 (*mips_cache_ops.mco_icache_sync_range_index)((v), (s))
192 #define mips_dcache_wbinv_all() \
193 __mco_noargs(, dcache_wbinv_all)
195 #define mips_dcache_wbinv_range(v, s) \
196 __mco_2args(, dcache_wbinv_range, (v), (s))
198 #define mips_dcache_wbinv_range_index(v, s) \
199 __mco_2args(, dcache_wbinv_range_index, (v), (s))
201 #define mips_dcache_inv_range(v, s) \
202 __mco_2args(, dcache_inv_range, (v), (s))
204 #define mips_dcache_wb_range(v, s) \
205 __mco_2args(, dcache_wb_range, (v), (s))
208 * Private D-cache functions only called from (currently only the
209 * mipsNN) I-cache functions.
211 #define mips_intern_dcache_wbinv_all() \
212 __mco_noargs(intern_, dcache_wbinv_all)
214 #define mips_intern_dcache_wbinv_range_index(v, s) \
215 __mco_2args(intern_, dcache_wbinv_range_index, (v), (s))
217 #define mips_intern_dcache_wb_range(v, s) \
218 __mco_2args(intern_, dcache_wb_range, (v), (s))
220 /* forward declaration */
223 void mips_config_cache(struct mips_cpuinfo *);
225 #include <machine/cache_mipsNN.h>
226 #endif /* _MACHINE_CACHE_H_ */