1 /* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Copyright (C) 1989 Digital Equipment Corporation.
35 * Permission to use, copy, modify, and distribute this software and
36 * its documentation for any purpose and without fee is hereby granted,
37 * provided that the above copyright notice appears in all copies.
38 * Digital Equipment Corporation makes no representations about the
39 * suitability of this software for any purpose. It is provided "as is"
40 * without express or implied warranty.
42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
43 * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish
47 #ifndef _MACHINE_CPU_H_
48 #define _MACHINE_CPU_H_
50 #include <machine/psl.h>
51 #include <machine/endian.h>
53 #define MIPS_CACHED_MEMORY_ADDR 0x80000000
54 #define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000
55 #define MIPS_MAX_MEM_ADDR 0xbe000000
56 #define MIPS_RESERVED_ADDR 0xbfc80000
58 #define MIPS_KSEG0_LARGEST_PHYS 0x20000000
59 #define MIPS_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
60 #define MIPS_PHYS_TO_CACHED(x) ((unsigned)(x) | MIPS_CACHED_MEMORY_ADDR)
61 #define MIPS_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
62 #define MIPS_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MIPS_UNCACHED_MEMORY_ADDR)
64 #define MIPS_PHYS_MASK (0x1fffffff)
65 #define MIPS_PA_2_K1VA(x) (MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK))
67 #define MIPS_VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR)
68 #define MIPS_CACHED_TO_UNCACHED(x) (MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x)))
70 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
71 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
72 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
73 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
75 #define MIPS_IS_KSEG0_ADDR(x) \
76 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
77 ((vm_offset_t)(x) <= MIPS_KSEG0_END))
78 #define MIPS_IS_KSEG1_ADDR(x) \
79 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
80 ((vm_offset_t)(x) <= MIPS_KSEG1_END))
81 #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
82 MIPS_IS_KSEG1_ADDR(x))
87 #define SR_COP_USABILITY 0xf0000000
88 #define SR_COP_0_BIT 0x10000000
89 #define SR_COP_1_BIT 0x20000000
90 #define SR_COP_2_BIT 0x40000000
91 #define SR_RP 0x08000000
92 #define SR_FR_32 0x04000000
93 #define SR_RE 0x02000000
94 #define SR_PX 0x00800000
95 #define SR_BOOT_EXC_VEC 0x00400000
96 #define SR_TLB_SHUTDOWN 0x00200000
97 #define SR_SOFT_RESET 0x00100000
98 #define SR_DIAG_CH 0x00040000
99 #define SR_DIAG_CE 0x00020000
100 #define SR_DIAG_DE 0x00010000
101 #define SR_KX 0x00000080
102 #define SR_SX 0x00000040
103 #define SR_UX 0x00000020
104 #define SR_KSU_MASK 0x00000018
105 #define SR_KSU_USER 0x00000010
106 #define SR_KSU_SUPER 0x00000008
107 #define SR_KSU_KERNEL 0x00000000
108 #define SR_ERL 0x00000004
109 #define SR_EXL 0x00000002
110 #define SR_INT_ENAB 0x00000001
112 #define SR_INT_MASK 0x0000ff00
113 #define SOFT_INT_MASK_0 0x00000100
114 #define SOFT_INT_MASK_1 0x00000200
115 #define SR_INT_MASK_0 0x00000400
116 #define SR_INT_MASK_1 0x00000800
117 #define SR_INT_MASK_2 0x00001000
118 #define SR_INT_MASK_3 0x00002000
119 #define SR_INT_MASK_4 0x00004000
120 #define SR_INT_MASK_5 0x00008000
121 #define ALL_INT_MASK SR_INT_MASK
122 #define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1)
123 #define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK)
127 * The bits in the cause register.
129 * CR_BR_DELAY Exception happened in branch delay slot.
130 * CR_COP_ERR Coprocessor error.
131 * CR_IP Interrupt pending bits defined below.
132 * CR_EXC_CODE The exception type (see exception codes below).
134 #define CR_BR_DELAY 0x80000000
135 #define CR_COP_ERR 0x30000000
136 #define CR_EXC_CODE 0x0000007c
137 #define CR_EXC_CODE_SHIFT 2
138 #define CR_IPEND 0x0000ff00
141 * Cause Register Format:
143 * 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0
144 * ----------------------------------------------------------------------
145 * | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0|
146 * |______________________________________________________________________
149 #define CR_INT_SOFT0 0x00000100
150 #define CR_INT_SOFT1 0x00000200
151 #define CR_INT_0 0x00000400
152 #define CR_INT_1 0x00000800
153 #define CR_INT_2 0x00001000
154 #define CR_INT_3 0x00002000
155 #define CR_INT_4 0x00004000
156 #define CR_INT_5 0x00008000
158 #define CR_INT_UART CR_INT_1
159 #define CR_INT_IPI CR_INT_2
160 #define CR_INT_CLOCK CR_INT_5
163 * The bits in the CONFIG register
165 #define CFG_K0_UNCACHED 2
166 #define CFG_K0_CACHED 3
169 * The bits in the context register.
171 #define CNTXT_PTE_BASE 0xff800000
172 #define CNTXT_BAD_VPN2 0x007ffff0
175 * Location of exception vectors.
177 #define RESET_EXC_VEC 0xbfc00000
178 #define TLB_MISS_EXC_VEC 0x80000000
179 #define XTLB_MISS_EXC_VEC 0x80000080
180 #define CACHE_ERR_EXC_VEC 0x80000100
181 #define GEN_EXC_VEC 0x80000180
184 * Coprocessor 0 registers:
186 #define COP_0_TLB_INDEX $0
187 #define COP_0_TLB_RANDOM $1
188 #define COP_0_TLB_LO0 $2
189 #define COP_0_TLB_LO1 $3
190 #define COP_0_TLB_CONTEXT $4
191 #define COP_0_TLB_PG_MASK $5
192 #define COP_0_TLB_WIRED $6
193 #define COP_0_INFO $7
194 #define COP_0_BAD_VADDR $8
195 #define COP_0_COUNT $9
196 #define COP_0_TLB_HI $10
197 #define COP_0_COMPARE $11
198 #define COP_0_STATUS_REG $12
199 #define COP_0_CAUSE_REG $13
200 #define COP_0_EXC_PC $14
201 #define COP_0_PRID $15
202 #define COP_0_CONFIG $16
203 #define COP_0_LLADDR $17
204 #define COP_0_WATCH_LO $18
205 #define COP_0_WATCH_HI $19
206 #define COP_0_TLB_XCONTEXT $20
207 #define COP_0_ECC $26
208 #define COP_0_CACHE_ERR $27
209 #define COP_0_TAG_LO $28
210 #define COP_0_TAG_HI $29
211 #define COP_0_ERROR_PC $30
214 * Coprocessor 0 Set 1
216 #define C0P_1_IPLLO $18
217 #define C0P_1_IPLHI $19
218 #define C0P_1_INTCTL $20
219 #define C0P_1_DERRADDR0 $26
220 #define C0P_1_DERRADDR1 $27
223 * Values for the code field in a break instruction.
225 #define BREAK_INSTR 0x0000000d
226 #define BREAK_VAL_MASK 0x03ffffc0
227 #define BREAK_VAL_SHIFT 16
228 #define BREAK_KDB_VAL 512
229 #define BREAK_SSTEP_VAL 513
230 #define BREAK_BRKPT_VAL 514
231 #define BREAK_SOVER_VAL 515
232 #define BREAK_DDB_VAL 516
233 #define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
234 #define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
235 #define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
236 #define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
237 #define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
240 * Mininum and maximum cache sizes.
242 #define MIN_CACHE_SIZE (16 * 1024)
243 #define MAX_CACHE_SIZE (256 * 1024)
246 * The floating point version and status registers.
252 * The floating point coprocessor status register bits.
254 #define FPC_ROUNDING_BITS 0x00000003
255 #define FPC_ROUND_RN 0x00000000
256 #define FPC_ROUND_RZ 0x00000001
257 #define FPC_ROUND_RP 0x00000002
258 #define FPC_ROUND_RM 0x00000003
259 #define FPC_STICKY_BITS 0x0000007c
260 #define FPC_STICKY_INEXACT 0x00000004
261 #define FPC_STICKY_UNDERFLOW 0x00000008
262 #define FPC_STICKY_OVERFLOW 0x00000010
263 #define FPC_STICKY_DIV0 0x00000020
264 #define FPC_STICKY_INVALID 0x00000040
265 #define FPC_ENABLE_BITS 0x00000f80
266 #define FPC_ENABLE_INEXACT 0x00000080
267 #define FPC_ENABLE_UNDERFLOW 0x00000100
268 #define FPC_ENABLE_OVERFLOW 0x00000200
269 #define FPC_ENABLE_DIV0 0x00000400
270 #define FPC_ENABLE_INVALID 0x00000800
271 #define FPC_EXCEPTION_BITS 0x0003f000
272 #define FPC_EXCEPTION_INEXACT 0x00001000
273 #define FPC_EXCEPTION_UNDERFLOW 0x00002000
274 #define FPC_EXCEPTION_OVERFLOW 0x00004000
275 #define FPC_EXCEPTION_DIV0 0x00008000
276 #define FPC_EXCEPTION_INVALID 0x00010000
277 #define FPC_EXCEPTION_UNIMPL 0x00020000
278 #define FPC_COND_BIT 0x00800000
279 #define FPC_FLUSH_BIT 0x01000000
280 #define FPC_MBZ_BITS 0xfe7c0000
283 * Constants to determine if have a floating point instruction.
285 #define OPCODE_SHIFT 26
286 #define OPCODE_C1 0x11
289 * The low part of the TLB entry.
291 #define VMTLB_PF_NUM 0x3fffffc0
292 #define VMTLB_ATTR_MASK 0x00000038
293 #define VMTLB_MOD_BIT 0x00000004
294 #define VMTLB_VALID_BIT 0x00000002
295 #define VMTLB_GLOBAL_BIT 0x00000001
297 #define VMTLB_PHYS_PAGE_SHIFT 6
300 * The high part of the TLB entry.
302 #define VMTLB_VIRT_PAGE_NUM 0xffffe000
303 #define VMTLB_PID 0x000000ff
304 #define VMTLB_PID_R9K 0x00000fff
305 #define VMTLB_PID_SHIFT 0
306 #define VMTLB_VIRT_PAGE_SHIFT 12
307 #define VMTLB_VIRT_PAGE_SHIFT_R9K 13
310 * The first TLB entry that write random hits.
312 #define VMWIRED_ENTRIES 1
315 * The number of process id entries.
317 #define VMNUM_PIDS 256
320 * TLB probe return codes.
322 #define VMTLB_NOT_FOUND 0
323 #define VMTLB_FOUND 1
324 #define VMTLB_FOUND_WITH_PATCH 2
325 #define VMTLB_PROBE_ERROR 3
328 * Exported definitions unique to mips cpu support.
332 * definitions of cpu-dependent requirements
333 * referenced in generic code
335 #define COPY_SIGCODE /* copy sigcode above user stack in exec */
337 #define cpu_swapout(p) panic("cpu_swapout: can't get here");
340 #include <machine/frame.h>
342 * Arguments to hardclock and gatherstats encapsulate the previous
343 * machine state in an opaque clockframe.
345 #define clockframe trapframe /* Use normal trap frame */
347 #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
348 #define CLKF_BASEPRI(framep) ((framep)->cpl == 0)
349 #define CLKF_PC(framep) ((framep)->pc)
350 #define CLKF_INTR(framep) (0)
351 #define MIPS_CLKF_INTR() (intr_nesting_level >= 1)
352 #define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0)
353 #define TRAPF_PC(framep) ((framep)->pc)
354 #define cpu_getstack(td) ((td)->td_frame->sp)
357 * CPU identification, from PRID register.
362 #if BYTE_ORDER == BIG_ENDIAN
363 u_int pad1:8; /* reserved */
364 u_int cp_vendor:8; /* company identifier */
365 u_int cp_imp:8; /* implementation identifier */
366 u_int cp_majrev:4; /* major revision identifier */
367 u_int cp_minrev:4; /* minor revision identifier */
369 u_int cp_minrev:4; /* minor revision identifier */
370 u_int cp_majrev:4; /* major revision identifier */
371 u_int cp_imp:8; /* implementation identifier */
372 u_int cp_vendor:8; /* company identifier */
373 u_int pad1:8; /* reserved */
378 #endif /* !_LOCORE */
381 * CTL_MACHDEP definitions.
383 #define CPU_CONSDEV 1 /* dev_t: console terminal device */
384 #define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */
385 #define CPU_DISRTCSET 3 /* int: disable resettodr() call */
386 #define CPU_BOOTINFO 4 /* struct: bootinfo */
387 #define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */
388 #define CPU_MAXID 6 /* number of valid machdep ids */
390 #define CTL_MACHDEP_NAMES { \
392 { "console_device", CTLTYPE_STRUCT }, \
393 { "adjkerntz", CTLTYPE_INT }, \
394 { "disable_rtc_set", CTLTYPE_INT }, \
395 { "bootinfo", CTLTYPE_STRUCT }, \
396 { "wall_cmos_clock", CTLTYPE_INT }, \
400 * MIPS CPU types (cp_imp).
402 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
403 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
404 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
405 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
406 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
407 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
408 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
409 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
410 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
411 #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
412 #define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
413 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
414 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
415 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
416 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
417 #define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
418 #define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */
419 #define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */
420 #define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
421 #define MIPS_RM9000 0x34 /* E9000 CPU */
426 #define MIPS_SOFT 0x00 /* Software emulation ISA I */
427 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
428 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
429 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
430 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
431 #define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */
432 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
433 #define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
434 #define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */
435 #define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
436 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
437 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
438 #define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
439 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
440 #define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
441 #define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */
442 #define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */
443 #define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */
444 #define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */
447 extern union cpuprid cpu_id;
449 #define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp)
450 #define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \
451 cpu_id.cpu.cp_imp = ((type) & 0x00ff))
452 #endif /* !_LOCORE */
454 #if defined(_KERNEL) && !defined(_LOCORE)
455 extern union cpuprid fpu_id;
460 u_int32_t mips_cp0_config1_read(void);
461 int Mips_ConfigCache(void);
462 void Mips_SetWIRED(int);
463 void Mips_SetPID(int);
464 u_int Mips_GetCOUNT(void);
465 void Mips_SetCOMPARE(u_int);
466 u_int Mips_GetCOMPARE(void);
468 void Mips_SyncCache(void);
469 void Mips_SyncDCache(vm_offset_t, int);
470 void Mips_HitSyncDCache(vm_offset_t, int);
471 void Mips_HitSyncSCache(vm_offset_t, int);
472 void Mips_IOSyncDCache(vm_offset_t, int, int);
473 void Mips_HitInvalidateDCache(vm_offset_t, int);
474 void Mips_SyncICache(vm_offset_t, int);
475 void Mips_InvalidateICache(vm_offset_t, int);
477 void Mips_TLBFlush(int);
478 void Mips_TLBFlushAddr(vm_offset_t);
479 void Mips_TLBWriteIndexed(int, struct tlb *);
480 void Mips_TLBUpdate(vm_offset_t, unsigned);
481 void Mips_TLBRead(int, struct tlb *);
482 void mips_TBIAP(int);
485 extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */
486 extern u_int32_t cpu_counter_last; /* Last compare value loaded */
487 extern int num_tlbentries;
490 extern int intr_nesting_level;
492 #define func_0args_asmmacro(func, in) \
493 __asm __volatile ( "jalr %0" \
494 : "=r" (in) /* outputs */ \
495 : "r" (func) /* inputs */ \
498 #define func_1args_asmmacro(func, arg0) \
499 __asm __volatile ("move $4, %1;" \
502 : "r" (func), "r" (arg0) /* inputs */ \
505 #define func_2args_asmmacro(func, arg0, arg1) \
506 __asm __volatile ("move $4, %1;" \
510 : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \
511 : "$31", "$4", "$5");
513 #define func_3args_asmmacro(func, arg0, arg1, arg2) \
514 __asm __volatile ( "move $4, %1;" \
519 : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \
520 : "$31", "$4", "$5", "$6");
522 #define MachSetPID Mips_SetPID
523 #define MachTLBUpdate Mips_TLBUpdate
524 #define mips_TBIS Mips_TLBFlushAddr
525 #define MIPS_TBIAP() mips_TBIAP(num_tlbentries)
526 #define MachSetWIRED(index) Mips_SetWIRED(index)
527 #define MachTLBFlush(count) Mips_TLBFlush(count)
528 #define MachTLBGetPID(pid) (pid = Mips_TLBGetPID())
529 #define MachTLBRead(tlbno, tlbp) Mips_TLBRead(tlbno, tlbp)
530 #define MachFPTrap(sr, cause, pc) MipsFPTrap(sr, cause, pc)
533 * Enable realtime clock (always enabled).
535 #define enablertclock()
538 * Are we in an interrupt handler? required by JunOS
540 #define IN_INT_HANDLER() \
541 (curthread->td_intr_nesting_level != 0 || \
542 (curthread->td_pflags & TDP_ITHREAD))
545 * Low level access routines to CPU registers
548 void setsoftintr0(void);
549 void clearsoftintr0(void);
550 void setsoftintr1(void);
551 void clearsoftintr1(void);
554 u_int32_t mips_cp0_status_read(void);
555 void mips_cp0_status_write(u_int32_t);
557 int disableintr(void);
558 void restoreintr(int);
559 int enableintr(void);
560 int Mips_TLBGetPID(void);
564 void cpu_reset(void);
566 u_int32_t set_intr_mask(u_int32_t);
567 u_int32_t get_intr_mask(void);
568 u_int32_t get_cyclecount(void);
570 #define cpu_spinwait() /* nothing */
573 #endif /* !_MACHINE_CPU_H_ */