1 /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
4 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
33 * 1. Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in the
37 * documentation and/or other materials provided with the distribution.
38 * 3. All advertising materials mentioning features or use of this software
39 * must display the following acknowledgement:
40 * This product includes software developed by Per Fogelstrom.
41 * 4. The name of the author may not be used to endorse or promote products
42 * derived from this software without specific prior written permission
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
59 #ifndef _MACHINE_CPUFUNC_H_
60 #define _MACHINE_CPUFUNC_H_
62 #include <sys/types.h>
63 #include <machine/cpuregs.h>
66 * These functions are required by user-land atomi ops
72 __asm __volatile (".set noreorder\n\t"
88 __asm __volatile (__XSTRING(COP0_SYNC));
94 __asm __volatile ("sync" : : : "memory");
99 mips_read_membar(void)
105 mips_write_membar(void)
111 #if defined(__mips_n32) || defined(__mips_n64)
112 #define MIPS_RDRW64_COP0(n,r) \
113 static __inline uint64_t \
114 mips_rd_ ## n (void) \
117 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
122 static __inline void \
123 mips_wr_ ## n (uint64_t a0) \
125 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
126 __XSTRING(COP0_SYNC)";" \
134 #if defined(__mips_n64)
135 MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
136 MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
137 MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
138 MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
140 MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
142 #undef MIPS_RDRW64_COP0
145 #define MIPS_RDRW32_COP0(n,r) \
146 static __inline uint32_t \
147 mips_rd_ ## n (void) \
150 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
155 static __inline void \
156 mips_wr_ ## n (uint32_t a0) \
158 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
159 __XSTRING(COP0_SYNC)";" \
167 #define MIPS_RDRW32_COP0_SEL(n,r,s) \
168 static __inline uint32_t \
169 mips_rd_ ## n(void) \
172 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
177 static __inline void \
178 mips_wr_ ## n(uint32_t a0) \
180 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
181 __XSTRING(COP0_SYNC)";" \
190 static __inline void mips_sync_icache (void)
195 ".word 0x041f0000\n" /* xxx ICACHE */
202 MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
203 MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
204 MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
205 MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
206 MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
207 MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
208 MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
209 MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
210 MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
211 MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
213 /* XXX: Some of these registers are specific to MIPS32. */
214 #if !defined(__mips_n64)
215 MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
216 MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
217 MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
218 MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
220 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
222 MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
223 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
224 MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
225 MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
226 MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
227 MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
228 MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
229 MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
230 MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
232 MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
233 MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
234 MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
235 MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
237 #undef MIPS_RDRW32_COP0
239 static __inline register_t
244 s = mips_rd_status();
245 mips_wr_status(s & ~MIPS_SR_INT_IE);
247 return (s & MIPS_SR_INT_IE);
250 static __inline register_t
255 s = mips_rd_status();
256 mips_wr_status(s | MIPS_SR_INT_IE);
262 intr_restore(register_t ie)
264 if (ie == MIPS_SR_INT_IE) {
269 static __inline uint32_t
270 set_intr_mask(uint32_t mask)
274 ostatus = mips_rd_status();
275 mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
276 mips_wr_status(mask);
280 static __inline uint32_t
284 return (mips_rd_status() & MIPS_SR_INT_MASK);
290 __asm __volatile ("break");
293 #if defined(__GNUC__) && !defined(__mips_o32)
294 static inline uint64_t
295 mips3_ld(const volatile uint64_t *va)
302 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va));
309 mips3_sd(volatile uint64_t *va, uint64_t v)
314 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va));
318 uint64_t mips3_ld(volatile uint64_t *va);
319 void mips3_sd(volatile uint64_t *, uint64_t);
320 #endif /* __GNUC__ */
324 #define readb(va) (*(volatile uint8_t *) (va))
325 #define readw(va) (*(volatile uint16_t *) (va))
326 #define readl(va) (*(volatile uint32_t *) (va))
328 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
329 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
330 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
336 #define outb(a,v) (*(volatile unsigned char*)(a) = (v))
337 #define out8(a,v) (*(volatile unsigned char*)(a) = (v))
338 #define outw(a,v) (*(volatile unsigned short*)(a) = (v))
339 #define out16(a,v) outw(a,v)
340 #define outl(a,v) (*(volatile unsigned int*)(a) = (v))
341 #define out32(a,v) outl(a,v)
342 #define inb(a) (*(volatile unsigned char*)(a))
343 #define in8(a) (*(volatile unsigned char*)(a))
344 #define inw(a) (*(volatile unsigned short*)(a))
345 #define in16(a) inw(a)
346 #define inl(a) (*(volatile unsigned int*)(a))
347 #define in32(a) inl(a)
349 #define out8rb(a,v) (*(volatile unsigned char*)(a) = (v))
350 #define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v))
351 #define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v))
352 #define in8rb(a) (*(volatile unsigned char*)(a))
353 #define in16rb(a) (__in16rb((volatile uint16_t *)(a)))
354 #define in32rb(a) (__in32rb((volatile uint32_t *)(a)))
356 #define _swap_(x) (((x) >> 24) | ((x) << 24) | \
357 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8))
359 static __inline void __out32rb(volatile uint32_t *, uint32_t);
360 static __inline void __out16rb(volatile uint16_t *, uint16_t);
361 static __inline uint32_t __in32rb(volatile uint32_t *);
362 static __inline uint16_t __in16rb(volatile uint16_t *);
365 __out32rb(volatile uint32_t *a, uint32_t v)
374 __out16rb(volatile uint16_t *a, uint16_t v)
378 _v_ = ((v >> 8) & 0xff) | (v << 8);
382 static __inline uint32_t
383 __in32rb(volatile uint32_t *a)
392 static __inline uint16_t
393 __in16rb(volatile uint16_t *a)
398 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8);
402 void insb(uint8_t *, uint8_t *,int);
403 void insw(uint16_t *, uint16_t *,int);
404 void insl(uint32_t *, uint32_t *,int);
405 void outsb(uint8_t *, const uint8_t *,int);
406 void outsw(uint16_t *, const uint16_t *,int);
407 void outsl(uint32_t *, const uint32_t *,int);
408 u_int loadandclear(volatile u_int *addr);
410 #endif /* !_MACHINE_CPUFUNC_H_ */