1 /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
4 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Per Fogelstrom.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
35 #ifndef _MACHINE_CPUFUNC_H_
36 #define _MACHINE_CPUFUNC_H_
38 #include <sys/types.h>
39 #include <machine/cpuregs.h>
42 * These functions are required by user-land atomi ops
48 __asm __volatile (".set noreorder\n\t"
64 __asm __volatile ("sync" : : : "memory");
67 __asm __volatile("mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
73 mips_read_membar(void)
79 mips_write_membar(void)
89 __asm __volatile ("tlbp");
95 __asm __volatile("mfc0 %0, $12\n" /* MIPS_COP_0_STATUS */
96 "and %1, %0, $~1\n" /* MIPS_SR_INT_IE */
97 "mtc0 %1, $12\n" /* MIPS_COP_0_STATUS */
98 : "=r" (ret), "=r" (tmp));
106 __asm __volatile ("tlbr");
113 __asm __volatile ("tlbwi");
116 __asm __volatile("mfc %0, $12\n" /* MIPS_COP_0_STATUS */
117 "or %0, %0, $1\n" /* MIPS_SR_INT_IE */
118 "mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
126 __asm __volatile ("tlbwr");
131 #if 0 /* XXX mips64 */
133 #define MIPS_RDRW64_COP0(n,r) \
134 static __inline uint64_t \
135 mips_rd_ ## n (void) \
138 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
143 static __inline void \
144 mips_wr_ ## n (uint64_t a0) \
146 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
147 __XSTRING(COP0_SYNC)";" \
155 MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
156 MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
157 MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
158 MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
159 MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
161 #undef MIPS_RDRW64_COP0
164 #define MIPS_RDRW32_COP0(n,r) \
165 static __inline uint32_t \
166 mips_rd_ ## n (void) \
169 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
174 static __inline void \
175 mips_wr_ ## n (uint32_t a0) \
177 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
178 __XSTRING(COP0_SYNC)";" \
187 static __inline void mips_sync_icache (void)
198 MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
199 MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
200 MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
201 MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
202 MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
203 MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
204 MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
206 /* XXX: Some of these registers are specific to MIPS32. */
207 MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
208 MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
209 MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW);
210 MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
211 MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
212 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
213 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
214 MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
216 static __inline uint32_t
217 mips_rd_config_sel1(void)
220 __asm __volatile("mfc0 %[v0], $16, 1 ;"
226 #undef MIPS_RDRW32_COP0
228 static __inline register_t
233 s = mips_rd_status();
234 mips_wr_status(s & ~MIPS_SR_INT_IE);
239 static __inline register_t
244 s = mips_rd_status();
245 mips_wr_status(s | MIPS_SR_INT_IE);
250 #define intr_restore(s) mips_wr_status((s))
255 __asm __volatile ("break");
260 #define readb(va) (*(volatile uint8_t *) (va))
261 #define readw(va) (*(volatile uint16_t *) (va))
262 #define readl(va) (*(volatile uint32_t *) (va))
264 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
265 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
266 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
272 #define outb(a,v) (*(volatile unsigned char*)(a) = (v))
273 #define out8(a,v) (*(volatile unsigned char*)(a) = (v))
274 #define outw(a,v) (*(volatile unsigned short*)(a) = (v))
275 #define out16(a,v) outw(a,v)
276 #define outl(a,v) (*(volatile unsigned int*)(a) = (v))
277 #define out32(a,v) outl(a,v)
278 #define inb(a) (*(volatile unsigned char*)(a))
279 #define in8(a) (*(volatile unsigned char*)(a))
280 #define inw(a) (*(volatile unsigned short*)(a))
281 #define in16(a) inw(a)
282 #define inl(a) (*(volatile unsigned int*)(a))
283 #define in32(a) inl(a)
285 #define out8rb(a,v) (*(volatile unsigned char*)(a) = (v))
286 #define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v))
287 #define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v))
288 #define in8rb(a) (*(volatile unsigned char*)(a))
289 #define in16rb(a) (__in16rb((volatile uint16_t *)(a)))
290 #define in32rb(a) (__in32rb((volatile uint32_t *)(a)))
292 #define _swap_(x) (((x) >> 24) | ((x) << 24) | \
293 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8))
295 static __inline void __out32rb(volatile uint32_t *, uint32_t);
296 static __inline void __out16rb(volatile uint16_t *, uint16_t);
297 static __inline uint32_t __in32rb(volatile uint32_t *);
298 static __inline uint16_t __in16rb(volatile uint16_t *);
301 __out32rb(volatile uint32_t *a, uint32_t v)
310 __out16rb(volatile uint16_t *a, uint16_t v)
314 _v_ = ((v >> 8) & 0xff) | (v << 8);
318 static __inline uint32_t
319 __in32rb(volatile uint32_t *a)
328 static __inline uint16_t
329 __in16rb(volatile uint16_t *a)
334 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8);
338 void insb(uint8_t *, uint8_t *,int);
339 void insw(uint16_t *, uint16_t *,int);
340 void insl(uint32_t *, uint32_t *,int);
341 void outsb(uint8_t *, const uint8_t *,int);
342 void outsw(uint16_t *, const uint16_t *,int);
343 void outsl(uint32_t *, const uint32_t *,int);
344 u_int loadandclear(volatile u_int *addr);
346 #endif /* !_MACHINE_CPUFUNC_H_ */