sys/mips/include/cpufunc.h

   1 /*      $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $    */
   2
   3 /*-
   4  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause
   5  *
   6  * Copyright (c) 2002-2004 Juli Mallett.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29 /*
  30  * Copyright (c) 1995-1999 Per Fogelstrom.  All rights reserved.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  * 3. All advertising materials mentioning features or use of this software
  41  *    must display the following acknowledgement:
  42  *      This product includes software developed by Per Fogelstrom.
  43  * 4. The name of the author may not be used to endorse or promote products
  44  *    derived from this software without specific prior written permission
  45  *
  46  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  48  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  49  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  51  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  52  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  53  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  54  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  55  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  *
  57  *      JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
  58  * $FreeBSD$
  59  */
  60
  61 #ifndef _MACHINE_CPUFUNC_H_
  62 #define _MACHINE_CPUFUNC_H_
  63
  64 #include <sys/types.h>
  65 #include <machine/cpuregs.h>
  66
  67 /*
  68  * These functions are required by user-land atomi ops
  69  */
  70
  71 static __inline void
  72 mips_barrier(void)
  73 {
  74 #if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
  75         __compiler_membar();
  76 #else
  77         __asm __volatile (".set noreorder\n\t"
  78                           "nop\n\t"
  79                           "nop\n\t"
  80                           "nop\n\t"
  81                           "nop\n\t"
  82                           "nop\n\t"
  83                           "nop\n\t"
  84                           "nop\n\t"
  85                           "nop\n\t"
  86                           ".set reorder\n\t"
  87                           : : : "memory");
  88 #endif
  89 }
  90
  91 static __inline void
  92 mips_cp0_sync(void)
  93 {
  94         __asm __volatile (__XSTRING(COP0_SYNC));
  95 }
  96
  97 static __inline void
  98 mips_wbflush(void)
  99 {
 100 #if defined(CPU_CNMIPS)
 101         __asm __volatile (".set noreorder\n\t"
 102                         "syncw\n\t"
 103                         ".set reorder\n"
 104                         : : : "memory");
 105 #else
 106         __asm __volatile ("sync" : : : "memory");
 107         mips_barrier();
 108 #endif
 109 }
 110
 111 #ifdef _KERNEL
 112 /*
 113  * XXX
 114  * It would be nice to add variants that read/write register_t, to avoid some
 115  * ABI checks.
 116  */
 117 #if defined(__mips_n32) || defined(__mips_n64)
 118 #define MIPS_RW64_COP0(n,r)                                     \
 119 static __inline uint64_t                                        \
 120 mips_rd_ ## n (void)                                            \
 121 {                                                               \
 122         int v0;                                                 \
 123         __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";"       \
 124                           : [v0] "=&r"(v0));                    \
 125         mips_barrier();                                         \
 126         return (v0);                                            \
 127 }                                                               \
 128 static __inline void                                            \
 129 mips_wr_ ## n (uint64_t a0)                                     \
 130 {                                                               \
 131         __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";"       \
 132                          __XSTRING(COP0_SYNC)";"                \
 133                          "nop;"                                 \
 134                          "nop;"                                 \
 135                          :                                      \
 136                          : [a0] "r"(a0));                       \
 137         mips_barrier();                                         \
 138 } struct __hack
 139
 140 #define MIPS_RW64_COP0_SEL(n,r,s)                               \
 141 static __inline uint64_t                                        \
 142 mips_rd_ ## n(void)                                             \
 143 {                                                               \
 144         int v0;                                                 \
 145         __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"       \
 146                           : [v0] "=&r"(v0));                    \
 147         mips_barrier();                                         \
 148         return (v0);                                            \
 149 }                                                               \
 150 static __inline void                                            \
 151 mips_wr_ ## n(uint64_t a0)                                      \
 152 {                                                               \
 153         __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"       \
 154                          __XSTRING(COP0_SYNC)";"                \
 155                          :                                      \
 156                          : [a0] "r"(a0));                       \
 157         mips_barrier();                                         \
 158 } struct __hack
 159
 160 #if defined(__mips_n64)
 161 MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
 162 MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
 163 MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
 164 MIPS_RW64_COP0_SEL(userlocal, MIPS_COP_0_USERLOCAL, 2);
 165 #ifdef CPU_CNMIPS
 166 MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6);
 167 MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7);
 168 MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7);
 169 MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0);
 170 MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1);
 171 #endif
 172 #endif
 173 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
 174 MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
 175 MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
 176 #endif
 177 MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
 178
 179 #undef  MIPS_RW64_COP0
 180 #undef  MIPS_RW64_COP0_SEL
 181 #endif
 182
 183 #define MIPS_RW32_COP0(n,r)                                     \
 184 static __inline uint32_t                                        \
 185 mips_rd_ ## n (void)                                            \
 186 {                                                               \
 187         int v0;                                                 \
 188         __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";"        \
 189                           : [v0] "=&r"(v0));                    \
 190         mips_barrier();                                         \
 191         return (v0);                                            \
 192 }                                                               \
 193 static __inline void                                            \
 194 mips_wr_ ## n (uint32_t a0)                                     \
 195 {                                                               \
 196         __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";"        \
 197                          __XSTRING(COP0_SYNC)";"                \
 198                          "nop;"                                 \
 199                          "nop;"                                 \
 200                          :                                      \
 201                          : [a0] "r"(a0));                       \
 202         mips_barrier();                                         \
 203 } struct __hack
 204
 205 #define MIPS_RW32_COP0_SEL(n,r,s)                               \
 206 static __inline uint32_t                                        \
 207 mips_rd_ ## n(void)                                             \
 208 {                                                               \
 209         int v0;                                                 \
 210         __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"        \
 211                           : [v0] "=&r"(v0));                    \
 212         mips_barrier();                                         \
 213         return (v0);                                            \
 214 }                                                               \
 215 static __inline void                                            \
 216 mips_wr_ ## n(uint32_t a0)                                      \
 217 {                                                               \
 218         __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"        \
 219                          __XSTRING(COP0_SYNC)";"                \
 220                          "nop;"                                 \
 221                          "nop;"                                 \
 222                          :                                      \
 223                          : [a0] "r"(a0));                       \
 224         mips_barrier();                                         \
 225 } struct __hack
 226
 227 #ifdef CPU_CNMIPS
 228 static __inline void mips_sync_icache (void)
 229 {
 230         __asm __volatile (
 231                 ".set push\n"
 232                 ".set mips64\n"
 233                 ".word 0x041f0000\n"            /* xxx ICACHE */
 234                 "nop\n"
 235                 ".set pop\n"
 236                 : : );
 237 }
 238 #endif
 239
 240 MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE);
 241 MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG);
 242 MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
 243 MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
 244 MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
 245 #ifdef CPU_CNMIPS
 246 MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
 247 #endif
 248 #ifdef BERI_LARGE_TLB
 249 MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
 250 #endif
 251 #if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
 252 MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
 253 #endif
 254 #if defined(CPU_NLM) || defined(CPU_MIPS1004K) || defined (CPU_MIPS74K) || \
 255     defined(CPU_MIPS24K)
 256 MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
 257 #endif
 258 MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
 259 MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX);
 260 MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
 261 MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
 262 #if !defined(__mips_n64)
 263 MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
 264 #endif
 265 MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
 266 MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3);
 267
 268 /* XXX: Some of these registers are specific to MIPS32. */
 269 #if !defined(__mips_n64)
 270 MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
 271 MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
 272 MIPS_RW32_COP0_SEL(userlocal, MIPS_COP_0_USERLOCAL, 2);
 273 #endif
 274 #ifdef CPU_NLM
 275 MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1);
 276 #endif
 277 #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
 278 MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
 279 MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
 280 #endif
 281 MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
 282 MIPS_RW32_COP0_SEL(cinfo, MIPS_COP_0_PRID, 6);
 283 MIPS_RW32_COP0_SEL(tinfo, MIPS_COP_0_PRID, 7);
 284 /* XXX 64-bit?  */
 285 MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
 286
 287 #if defined(CPU_MIPS24K) || defined(CPU_MIPS34K) ||             \
 288     defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)  ||  \
 289     defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) ||        \
 290     defined(CPU_PROAPTIV)
 291 /* MIPS32/64 r2 intctl */
 292 MIPS_RW32_COP0_SEL(intctl, MIPS_COP_0_INTCTL, 1);
 293 #endif
 294
 295 #ifdef CPU_XBURST
 296 MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0);
 297 MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1);
 298 MIPS_RW32_COP0_SEL(xburst_core_ctl, MIPS_COP_0_XBURST_C12, 2);
 299 MIPS_RW32_COP0_SEL(xburst_core_sts, MIPS_COP_0_XBURST_C12, 3);
 300 MIPS_RW32_COP0_SEL(xburst_reim, MIPS_COP_0_XBURST_C12, 4);
 301 #endif
 302 MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
 303 MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
 304 MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
 305 MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
 306 MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
 307 MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
 308 MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
 309 MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
 310
 311 MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
 312 MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
 313 MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
 314 MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
 315 MIPS_RW32_COP0(hwrena, MIPS_COP_0_HWRENA);
 316
 317 #undef  MIPS_RW32_COP0
 318 #undef  MIPS_RW32_COP0_SEL
 319
 320 static __inline register_t
 321 intr_disable(void)
 322 {
 323         register_t s;
 324
 325         s = mips_rd_status();
 326         mips_wr_status(s & ~MIPS_SR_INT_IE);
 327
 328         return (s & MIPS_SR_INT_IE);
 329 }
 330
 331 static __inline register_t
 332 intr_enable(void)
 333 {
 334         register_t s;
 335
 336         s = mips_rd_status();
 337         mips_wr_status(s | MIPS_SR_INT_IE);
 338
 339         return (s);
 340 }
 341
 342 static __inline void
 343 intr_restore(register_t ie)
 344 {
 345         if (ie == MIPS_SR_INT_IE) {
 346                 intr_enable();
 347         }
 348 }
 349
 350 static __inline uint32_t
 351 set_intr_mask(uint32_t mask)
 352 {
 353         uint32_t ostatus;
 354
 355         ostatus = mips_rd_status();
 356         mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
 357         mips_wr_status(mask);
 358         return (ostatus);
 359 }
 360
 361 static __inline uint32_t
 362 get_intr_mask(void)
 363 {
 364
 365         return (mips_rd_status() & MIPS_SR_INT_MASK);
 366 }
 367
 368 static __inline void
 369 breakpoint(void)
 370 {
 371         __asm __volatile ("break");
 372 }
 373
 374 #if defined(__GNUC__) && !defined(__mips_o32)
 375 #define mips3_ld(a)     (*(const volatile uint64_t *)(a))
 376 #define mips3_sd(a, v)  (*(volatile uint64_t *)(a) = (v))
 377 #else
 378 uint64_t mips3_ld(volatile uint64_t *va);
 379 void mips3_sd(volatile uint64_t *, uint64_t);
 380 #endif  /* __GNUC__ */
 381
 382 #endif /* _KERNEL */
 383
 384 #define readb(va)       (*(volatile uint8_t *) (va))
 385 #define readw(va)       (*(volatile uint16_t *) (va))
 386 #define readl(va)       (*(volatile uint32_t *) (va))
 387 #if defined(__GNUC__) && !defined(__mips_o32)
 388 #define readq(a)        (*(volatile uint64_t *)(a))
 389 #endif
 390
 391 #define writeb(va, d)   (*(volatile uint8_t *) (va) = (d))
 392 #define writew(va, d)   (*(volatile uint16_t *) (va) = (d))
 393 #define writel(va, d)   (*(volatile uint32_t *) (va) = (d))
 394 #if defined(__GNUC__) && !defined(__mips_o32)
 395 #define writeq(va, d)   (*(volatile uint64_t *) (va) = (d))
 396 #endif
 397
 398 #endif /* !_MACHINE_CPUFUNC_H_ */